CN1859358A - Method for series and anti-series link data of equalizing complex strip parallel - Google Patents

Abstract

The invention discloses a protection method for preventing data transmission interruption in multiple parallel SERDES data links. In the method, the chip detects the link state by detecting the data frame, and when an abnormal state occurs in the data link is detected , the system will stop transmitting data through the link that has an abnormal state; when it detects that the data link is back to normal, the system will resume data transmission from the link. The solution of the present invention automatically detects and balances the link state in the parallel transmission scheme of the SERDES link to ensure that the data transmission is not interrupted when some links are abnormal, and the full-speed transmission is automatically restored when the link returns to normal. It is especially suitable for high-speed interconnection with low safety factor. The present invention also provides the feature of reducing the number of high-speed links and the flexible configuration capability, and the user can actively disconnect one or more of the parallel SERDES data links without affecting the normal transmission of data when the service flow is low.

Description

A method of equalizing multiple parallel serial anti-serial link data

technical field

The present invention relates to a SERDES (Serialize and Deserialize, serial anti-serialize) link data protection method, in particular to a method for detecting multiple parallel SERDES link data and balancing services to links with normal states.

Background technique

At present, the development of the digital communication field is advancing by leaps and bounds, and the data transmission rate between chips is also getting faster and faster. For 10 Gigabit routers, data streams are exchanged at a speed of 10Gbps. Currently, there are two types of interfaces that can achieve such a high speed: one is a dedicated standard interface, such as CSIX, SPI4, etc. This interface is generally a parallel bus with a separate clock that supports dynamic adjustment of the phase. However, due to the parallel bus and separate clocks, the number of buses is relatively limited, and a single line can only reach a speed of 1Gbps at most, so it is generally only used for chip interconnection in the board. Another method is to use SERDES technology. This method uses the channel-associated clock. The speed of a single line can reach 3.125Gps at present, and it can be further increased to 10Gps in the future. Moreover, SERDES technology uses differential lines, which has strong anti-interference ability and long transmission distance. It is the preferred transmission method for data transmission between chips, especially through the backplane and optical fiber. In order to achieve a higher data transmission rate, multiple SERDES links are often used for parallel transmission, and multiple SERDES data links are used for concurrent transmission in both the uplink and downlink directions.

In the prior art, the bundling of multiple SERDES links does not consider the disconnection of a certain SERDES data link. The default is that the SERDES link must work normally, and the hardware design must ensure this. XAUIXAUI is a low-pin-count, self-clocking serial bus directly developed from the physical layer of 1000Base-X 10 Gigabit Ethernet. The XAUI interface is 2.5 times faster than 1000Base-X. By adjusting 4 serial lines, this 4bit XAUI interface can support the data throughput of 10 Gigabit Ethernet 10 times that of Gigabit Ethernet. XAUI is a 10G data channel standard using serdes, but there is no automatic recovery mechanism for the serdes link, and the receiving end will forcefully receive data from the channel regardless of whether the SERDES link is normal or not. Regardless of the status of the sending SERDES link, the sending end sends data to all sending SERDES channels. This bundling method of multiple SERDES links is not safe. Once a problem occurs, it will cause the collapse and crash of the entire system. If it is a chip-level SERDES link interconnection in the board, it is acceptable (the probability of disconnection of the PCB trace in the board is negligible), but if it is a SERDES connection between boards or even cross-chassis connections through optical fibers, it is very difficult. Some SERDES cables may be disconnected (for example, a certain optical fiber is accidentally broken or a certain connection board is unplugged). At this time, the cost of system crash is very serious. Especially for carrier-grade backbone routers or switches, it is unacceptable to cause the entire system to collapse due to this reason.

In the SD566/SD567 switching network chip design of Huawei Technologies Co., Ltd., the receiving end of SERDES can detect link abnormality and whether the link is restored, but the system design does not consider directly notifying the peer end through a full-duplex connection , and the upper-layer software must notify the sending end of the opposite end through periodic query or interruption, so that the opposite end can close the link with problems or open the link that returns to normal according to the link status. Does not consider the automatic transfer of the link state and the automatic opening/closing of the link by means of hardware.

This method of software processing has a large delay, at least at the millisecond level. If the link status changes from good to bad, using this technology will cause a large amount of data loss (the peer end does not know the time of the link change. , it will continue to send data through the wrong link). Conversely, if the link status changes from bad to good, the data passing capability cannot be quickly restored by using this technology.

Contents of the invention

The purpose of the invention is to automatically detect SERDES links by means of hardware, eliminate wrong links, and only receive data from normal links. In this way, even when some SERDES links have problems, or users actively disconnect one or more links when the service flow is low, the entire system will automatically balance normal services to the normal lines, and the services will not be interrupted, realizing smooth downgrade. If the system detects that a SERDES line is restored, it will automatically rebalance.

The purpose of the invention of the present invention is achieved like this:

A method for balancing plural parallel SERDES link data, comprising steps:

a) The sending chip fixes the length of the data frame to be sent, and establishes a sequence of frame headers, connection frame number fields, link state fields, and data fields in the data frames;

b) assigning a connection frame number to each data frame, and encapsulating the connection frame number into the data frame;

c) the sending chip sends the data frame to the receiving chip through the SERDES link;

d) The receiving chip detects the received data frame, and when it finds that the state of the SERDES link is abnormal, it notifies the sending chip to transmit the data of this link from other SERDES links.

Described d step specifically comprises the following steps:

d1) After the receiving chip detects that the SERDES link is abnormal, the abnormal state information of the SERDES link is put into the link state field of the frame sent to the sending chip;

d2) After receiving the abnormal state information of the SERDES link, the sending chip stops transmitting data from the abnormal link;

d3) The sending chip transmits the data of this link from other SERDES links.

Described method also comprises the following steps:

e) When the receiving chip detects that the link state of the abnormal SERDES link in step d) returns to normal, it notifies the sending chip to resume transmission of data frames from the link.

Described step e) specifically comprises steps:

e1) After the receiving chip detects the normal state of the SERDES link, the normal state of the link is put into the link state information of the frame sent to the sending chip;

e2) The sending chip transmits the data frame from the link.

The method for detecting SERDES link status comprises steps:

The sending chip sends data frames continuously, and there is no gap between the data frames; if the data frames are insufficient, fill the idle frames between the data frames; the connection frame numbers of the continuously sent frames are continuous;

If the receiving chip does not detect the frame header in every byte of the specified data frame length, or the count of the connection frame number after detecting the frame header is not continuous with the count of the connection frame number detected last time, or detects If there is an error in the physical layer decoding to SERDES (including but not limited to 8B/10B codec), it is judged that the SERDES link status is abnormal.

When the SERDES link status is abnormal, the receiving chip continuously detects the link. If a specified number of frame types and connection frame numbers are received continuously and at normal intervals, and the count of the connection frame number is incremented, and there is no detection If there is an error in the decoding of the physical layer to SERDES (including but not limited to 8B/10B codec), the SERDES link status returns to normal.

With this technical solution, the automatic detection and balance of the link status in the parallel transmission of multiple SERDES links can be realized by means of hardware, so as to ensure that the service is not interrupted when some links are abnormal, and the service is smoothly degraded, and the full speed is automatically restored when the link returns to normal. transmission. When the business flow is low, the user can actively disconnect one or more of the parallel SERDES data links without affecting the normal transmission of data. The technical scheme can make the processing delay reach microsecond level, and is especially suitable for high-speed interconnection with low safety factor (such as remote optical fiber interconnection).

The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. Through the description of the preferred embodiments of the present invention, the advantages of the present invention can be seen and understood more clearly.

Description of drawings

Fig. 1 is the system connection schematic diagram of the present invention

Fig. 2 is a schematic diagram of the data frame structure of the present invention

Detailed ways

As shown in Figure 1, the data link consists of two SERDES parallel links, uplink 0 and uplink 1, respectively. Both the sending chip and the receiving chip have a sending control part and a receiving control part, and there is a channel connection from the receiving control part in the chip to the sending control part to transmit link state information. T0, T1, t0, and t1 in the figure are four SERDES sending units, and R0, R1, r0, r1 are four SERDES receiving units. The data channels in the uplink direction and downlink direction (the two SERDES links from left to right are the uplink direction, and the two SERDES links from right to left are the downlink direction) together form a complete bidirectional digital channel.

The reception of the link state is accomplished by relying on the SERDES reception control part. As shown in FIG. 1 , r0 and r1 can respectively detect the states of the two uplink 0 and uplink 1 links, while R0 and R1 can respectively detect the states of the two downlink 0 and downlink 1 links.

The detection of the link state has multiple means, in order to be as strict as possible, guarantee the normal operation of the link, the present invention adopts the method that SERDES hard core flag signal combines data frame content detection, the structure of data frame is as shown in Figure 2, and data frame is The length is fixed, and the format is fixed. In this embodiment, the length of the data frame is set to 64 bytes. Place a byte of K28.5 character in the frame header, place an increasing connection frame number in the connection frame number field link head, store link state information in the link state field linkstatus, and place data in the data field payload load. The data frames to be transmitted are continuous and there is no gap between them. If the data frames are insufficient, a kind of idle frame is filled to ensure the back-to-back transmission of the data frames on the link. The frame header of the idle frame is a one-byte K28.5 character, and the load on the frame is all 0. Moreover, the frame length of the idle frame is the same as that of the data frame, which is also 64 bytes. The frame length of the idle frame is not calculated by the chip. If the link status is normal, then the K28.5 character should appear every 64 bytes, and the connection frame number behind the K28.5 character must be incremented. Once the receiving chip finds that the above rules are violated, or detects errors in the physical layer decoding of SERDES (including but not limited to 8B/10B codec), it will consider the SERDES link status to be abnormal. After the link status is abnormal, the sending chip still sends idle frames from the abnormal SERDES link, and the receiving control part of the receiving chip continuously detects the link and searches for K28.5 characters. K28.5 characters with normal intervals, the connection frame number after K28.5 characters is also incremented, and there is no SERDES physical layer decoding error, then the link status is considered to be normal. The specified number here can be from 1 to hundreds, depending on the required accuracy.

If the link status is found to be abnormal, the data will stop being transmitted from the abnormal SERDES link and only be transmitted from the normal SERDES link; if the link status is found to be normal, then the data will be transmitted from all normal SERDES links again Transport on the road.

As shown in Figure 2, there is a special link status field (link status) in the data frame structure to place the link status flag. The receiving control part of the receiving chip detects the status of the link and passes these states to the sending control part of the receiving chip, and then the sending control part of the receiving chip inserts the link status into the link status field of the frame sent to the sending chip , the receiving control part of the sending chip extracts the link state and sends it to the sending control part of the sending chip, and then the sending control part of the sending chip re-schedules the sending according to this information, disconnects or resumes the data transmission from this link, Ensure that data is only transmitted from SERDES links that are in a healthy state.

Assume that the status of all 4 links is normal at the beginning, and then the uplink 0 link is suddenly disconnected at a certain moment, and the receiving control part r0 detects that the link status is abnormal immediately, and the receiving control part will no longer The link receives data, and at the same time transmits the link abnormality information to the sending control part t0 and t1; the sending control part t0 and t1 inserts this information into the link state field of the frame sent to the sending chip, through the downlink 0 and t1 The two links of downlink 1 are sent out; the receiving control parts R0 and R1 extract the link information after receiving the frame, and find that the link status corresponding to uplink 0 is abnormal, so they send this information to the sending control parts T0 and T1, The sending control parts T0 and T1 will only send the normal service data flow through the uplink 1 link. In order for the receiving end to re-detect synchronization when the link is restored, idle frames will still be sent on the uplink 0 link at this time. Once the uplink 0 link is restored, follow the above steps to send the information that the link status is normal to the sending control part T0 and T1, and the sending control part T0 and T1 will redistribute the normal service data flow to the uplink 0 and uplink 1. In this way, the automatic balance of the link is realized.

Claims (6)

1. A method for equalizing multiple parallel serial anti-serial SERDES link data, comprising steps: a) The sending chip fixes the length of the data frame to be sent, and establishes a sequence of frame headers, connection frame number fields, link state fields, and data fields in the data frames; b) assigning a connection frame number to each data frame, and encapsulating the connection frame number into the data frame; c) the sending chip sends the data frame to the receiving chip through the SERDES link; d) The receiving chip detects the received data frame, and when it finds that the state of the SERDES link is abnormal, it notifies the sending chip to transmit the data of this link from other SERDES links. 2. method according to claim 1, is characterized in that, described d step specifically comprises the following steps: d1) After the receiving chip detects that the SERDES link is abnormal, the abnormal state information of the SERDES link is put into the link state field of the frame sent to the sending chip; d2) After receiving the abnormal state information of the SERDES link, the sending chip stops transmitting data from the abnormal link; d3) The sending chip transmits the data of this link from other SERDES links. 3. The method according to claim 1, further comprising the steps of: e) When the receiving chip detects that the link state of the abnormal SERDES link in step d) returns to normal, it notifies the sending chip to resume transmission of data frames from the link. 4. method according to claim 3, is characterized in that, described step e) specifically comprises the step: e1) After the receiving chip detects the normal state of the SERDES link, the normal state of the link is put into the link state information of the frame sent to the sending chip; e2) The sending chip transmits the data frame from the link. 5. according to the described method of claim 1 or 3, it is characterized in that, the method for described detection SERDES link status comprises steps: The sending chip sends data frames continuously, and there is no gap between the data frames; if the data frames are insufficient, fill the idle frames between the data frames; the connection frame numbers of the continuously sent frames are continuous; If the receiving chip does not detect the frame header in every byte of the specified data frame length, or detects that the count of the connection frame number is not continuous with the count of the connection frame number detected last time, or detects the physical layer of SERDES If there is an error in decoding, it is judged that the SERDES link status is abnormal; When the status of the SERDES link is abnormal, the sending chip continues to send idle frames on the abnormal SERDES link, and the receiving chip continuously detects the link. number, and the count of the connection frame number is incremented, and there is no SERDES physical layer decoding error, then the SERDES link status returns to normal. 6. The method according to claim 5, wherein the prescribed number is 5 or 8.

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