CN1303654C - Polishing method and device - Google Patents

Abstract

The present invention relates to a polishing method and polishing equipment suitable for the polishing method. In the method, the millstone comprising grinding material granules and abrasive resin pasting the grinding material granules. The millstone with required elastic modulus can be obtained by utilizing the abrasive resin pasting the grinding material granules, and can be used for flattening the surface of a substrate with concave and convex parts, and the dimension of the concave and convex parts is not considered. In addition, the surface of the substrate is firstly polished by a polishing tool with low elastic modulus, and then is polished by a polishing tool with high elastic modulus so as to obtain a polished surface with reduced damage. The method of the present invention can effectively plane various substrates with concave and convex parts.

Description

Polishing methods and equipment

This application is a divisional application of Patent Application No. 95197955.8 filed on September 13, 1995, entitled "Polishing Method and Apparatus".

Field

The present invention relates to a technique for planarizing substrate surface patterns by polishing, and in particular to a polishing method used in the process of manufacturing semiconductor integrated circuits, and polishing equipment used in the polishing method.

Background technique

The semiconductor manufacturing process includes a multi-step process. 1 (a) - 1 (f) to illustrate a wiring process, as a process example of the application of the present invention.

FIG. 1(a) is a cross-sectional view of a wafer with a first wiring layer formed thereon. An insulating film 2 is formed on the surface of a wafer substrate 1 with a transistor portion formed thereon, and a wiring layer 3 such as an aluminum layer is formed on the insulating film 2 . In order to connect this transistor, a contact hole is formed in the insulating film 2, so that the portion of the wiring layer corresponding to the contact hole is somewhat recessed, here indicated by 3'. In the second layer wiring process shown in Figure 1(b), an insulating film 4 and a metal aluminum layer 5 are formed on the first layer, and a photoresist film 6 is coated on the aluminum layer for exposure, so that the aluminum Layers form wiring patterns. Next, as shown in FIG. 1(c), the photoresist film 6 is exposed to light by a stepper 7, thereby transferring the wiring circuit pattern of the second layer. In this case, if the surface of the photoresist film 6 is uneven, the concave and convex portions indicated by 8 on the surface of the photoresist film cannot be focused at the same time, so that the resolution is not satisfactory, which is a serious problem.

In order to avoid the above-mentioned problems, the following planarization process for the substrate surface has been studied. Following the step shown in FIG. 1(a), as shown in FIG. 1(d), after the insulating layer 4 is formed, it is polished by a method that will be described hereafter, so that the layer 4 becomes flat, reaching the level shown by the line 9 in the same figure. level. In this way, the state shown in Fig. 1(e) is obtained. Thereafter, a metal aluminum layer 5 and a photoresist layer 6 are formed, and then exposed using a stepper 7 shown in FIG. 1(f). In this case, the above-mentioned problem of unsatisfactory resolution does not occur.

FIG. 2 shows a chemical mechanical polishing method which has heretofore been generally used to planarize the above-mentioned insulating film pattern. The polishing pad 11 is fixed on the platform 12 and can rotate. As the polishing pad 11, for example, a polishing pad obtained by cutting a foamed urethane resin into a sheet and molding it into a sheet can be used. According to the type of workpiece and the surface roughness to be achieved, select the appropriate material and fine surface structure from various materials and fine surface structures. On the other hand, the wafer 1 to be processed is held on the wafer holder 14 by the elastic mold plate 13 . While the wafer holder 14 is rotating, the wafer is pressed onto the surface of the polishing pad 11, and the polishing suspension 15 is added to the polishing pad, thereby throwing off the protrusion of the insulating film 4 on the wafer surface to obtain a flat surface.

In the case of polishing an insulating film such as a silicon dioxide film, colloidal silica is generally used as a polishing suspension. Colloidal silica is suspended in an alkaline aqueous solution such as potassium hydroxide solution as fine silica particles with a diameter of about 30 nm. Due to the additional chemical action of the alkali, the use of this colloidal silica is distinguished by extremely high treatment efficiency and smooth surfaces with reduced process damage compared to mechanical polishing with abrasives alone. This method of providing a polishing suspension between the polishing pad and the workpiece during processing is known as the free abrasive polishing technique.

In general, conventional wafer planarization techniques using this free abrasive polishing method have two challenges to be solved. One difficulty is that of pattern size related issues, where a satisfactory level of planarization cannot be achieved for certain types of patterns or for certain cases of varying heights. Another challenge is the prohibitive cost of particle consumption required for the polishing process. These issues will be described in detail below.

Generally, patterns having different sizes and different heights are formed on a semiconductor wafer. For example, in the semiconductor memory device, as shown in FIG. Peripheral circuits 17 for accessing the above-mentioned memory cells are formed along the boundaries of the four memory block portions. In the case of a typical dynamic memory, the size of one chip is about 7mm×20mm, and the width of the peripheral circuit 17 is about 1mm. Taking a cross-section of the chip along the line A-A', as shown in FIG. 3(b), the average height of the memory block portion 16H is about 0.5-1 μm higher than that of the peripheral circuit portion 17L. If an insulating film 4 of about 1-2 µm thick is formed on such a stepped pattern, the cross-sectional shape 31 of the surface portion substantially reflects the stepped shape of the underlying pattern.

With the planarization process that the present invention is committed to, the insulating film 4 on the wafer surface becomes flat as shown by the dotted line 32 . However, when using a soft polishing pad generally formed of polyurethane foam for the intended purpose, the desired planarization described above cannot be achieved because of the relationship between the polishing speed and the pattern. More specifically, as shown in FIG. 4, if a soft polishing pad 11L is used, the surface of the polishing pad is deformed by the polishing load as indicated by the solid line 30 in the figure. Because of the concentrated load, it can polish the fine pattern of micron size in a short time, but in the case of large pattern size of millimeter level, the polishing speed is very low because of the distributed load. Therefore, the cross-sectional shape after polishing becomes as shown by the dotted line 34 in the figure, and the height difference d still remains.

Making the polishing pad harder can improve the flatness, but in this case, there are new problems of increased processing non-uniformity within the wafer plane, and process damage problems as will be explained later. The reason for this increased process non-uniformity that occurs when using hard polishing pads is not fully understood. However, it is speculated that the abrasive added to the surface of the polishing pad may be partially captured by the fine structure on the surface of the polishing pad, and the probability of entering the polishing pad and the substrate to be processed changes, and this change will affect the processing. Such uniformity required in the semiconductor wiring process is below ±5%. Currently, the upper limit for polishing pad hardness is a Young's modulus of about 10 kg/mm ² . Therefore, a satisfactory planarization effect cannot be expected in a semiconductor device, such as a memory device, in which various patterns including small patterns and large patterns are mixed on the order of millimeters to micrometers and the like. For this reason, the products of such polishing pads can be limited to semiconductor products not containing very large patterns, such as logic LSIs.

As for a polishing pad having properties intermediate between hard and soft polishing pads, Japanese Patent Laid-Open No. Hei 6-208980 discloses a polishing pad comprising a soft polishing pad and a hard polishing sheet embedded in part of the soft polishing pad. However, the obtained polishing characteristics were almost the same as those of the pads with intermediate hardness.

A second object to be achieved by the semiconductor wafer planarization technology based on the above-mentioned conventional free abrasive polishing method is to reduce the high production cost. The high production costs are due to the low utilization rate of the polishing suspension used in the free abrasive polishing method. More specifically, for ultra-smooth polishing that does not cause scratches, it is necessary to convey a polishing suspension such as colloidal silica at a rate of at least several hundred cc per minute. However, most of the suspension was wasted and did not contribute to actual treatment. However, the cost of the semiconductor high-purity suspension is quite high, and the cost of the planarization polishing process mostly depends on the polishing suspension. Therefore, there is an urgent need for improvement on this point.

As for existing methods other than the ones mentioned above, a bonded abrasive treatment method is described on pages 80-85 of the Proceedings of the First International ABTEC Conference (Seoul, November 1993), in which the abrasive Bonded with metal powder or resin to make a grinding stone that rotates at high speed. However, this method is known to have the disadvantage of often causing scratches on the treated surface. Also, in order to solve this scratching problem, Japanese Patent Laid-Open No. Hei 6-302568 discloses a planarization technique using a fine grinding stone with an extremely small particle size produced by electrophoresis. However, according to this technique, since the grindstone itself is hard, there is still a problem of scratches caused by dust or the like contained in the polishing liquid used or in the processing atmosphere.

In the conventional semiconductor wafer planarization technique using the free abrasive polishing method, as described above, it is not allowed to simultaneously planarize fine patterns whose minimum size is on the order of micrometers and large patterns on the order of millimeters. Therefore, it is still difficult to apply this conventional technique to the manufacture of semiconductor integrated circuits including various large and small patterns such as memory LSIs. Moreover, the cost of the polishing process is quite high, resulting in the fatal disadvantage that it cannot be applied to mass production.

The object of the present invention is to overcome the defects in the above-mentioned prior art, and provide a processing method for flattening large graphics and fine graphics into the same plane without any processing damage, and equipment used in the processing method.

Another object of the present invention is to provide a low-cost treatment method and equipment for said treatment method.

Contents of the invention

The above objects of the present invention can be achieved by using a fixed abrasive treatment method using a polishing tool with a controllable elastic modulus such as a grindstone, instead of a conventional free abrasive polishing process using a polishing pad and a polishing suspension.

Moreover, instead of utilizing one-time processing to planarize all patterns as in the prior art, first only planarize those fine patterns that are easily damaged by using a soft polishing tool, and then utilize a hard polishing tool such as a hard grindstone or a polishing pad to reduce High-power processing efficiently planarizes large graphics, and can solve the problem of processing damage to ultra-fine graphics that is prone to occur when using hard polishing tools.

Since the fixed abrasive processing method of the present invention uses a certain kind of grinding stone and processing conditions most appropriately selected according to the physical properties of the workpiece, even with a hard polishing tool, the planarization processing can be made less dependent on the figure, and the The unevenness of the processing speed on the substrate plane is small and does not cause the unevenness of the processing. In addition, the cost can be kept low since expensive polishing suspensions are not required. Furthermore, cleaning after treatment becomes easier.

In addition, if you first use a low-hardness soft polishing pad to polish, cut and round the corners of ultra-fine graphics that are susceptible to handling damage and the corners of large-size graphics that are easy to throw away, and then use a hard polishing pad with a strong shape to establish With planarization, a satisfactory processing surface can be obtained, and the dependence on the width of the pattern is reduced, and there is no processing damage.

Although it has been described above that the object of application of the present invention is a semiconductor wafer, the present invention can also be applied to thin film display devices and planarization of glass and ceramic substrates.

Brief introduction to the drawings

Fig. 1 (a)-1 (f) is the illustration diagram of the process of planarizing wafer surface;

FIG. 2 is a diagram for explaining a chemical mechanical polishing method;

Fig. 3 (a) is the plan view of semiconductor storage device, and Fig. 3 (b) is its sectional view;

FIG. 4 is a diagram for explaining problems in a polishing method with a soft polishing pad;

Fig. 5 is a diagram explaining the configuration of a grindstone used in the present invention;

FIG. 6 is a diagram for explaining problems in a polishing method with a hard polishing pad;

Fig. 7 (a) is a diagram explaining the polishing conditions of the prior art, and Fig. 7 (b) is a diagram explaining the polishing conditions of the present invention;

8(a)-8(e) are diagrams for explaining an embodiment of the present invention;

Fig. 9 is a diagram showing a structural example of a processing device suitable for implementing the present invention;

10(a)-10(e) are cross-sectional views of a semiconductor device, showing the manufacturing process of the semiconductor device; and

Fig. 11 is a plan view of the device shown in Fig. 10(e).

best practice

Embodiments of the present invention will be described in detail below. The present invention is characterized in that the conventional polishing pad in the apparatus shown in FIG. 2 is replaced with a specific grinding stone with optimally controlled hardness. As described above with respect to the prior art, several techniques are known for planarizing the surface of a semiconductor wafer using fine-grained grindstones. But all these techniques suffer from the disadvantage of causing small scratches on the treated surface. So it still cannot be put into practical application.

So far, it has been believed that the cause of this scratching is mainly due to the particle size being too large. However, research by the present inventors has found that this problem should be attributed to the too large modulus of elasticity of the grinding stone used, rather than a particle size problem.

The present invention is characterized in that an extremely soft grindstone in which particles 21 are loosely bonded to soft resin 22 as shown in FIG. 5 is used instead of the dense and hard grindstone described above. More specifically, the modulus of elasticity of the grindstone is 5-500 kg/mm ² , so that its hardness is one-tenth to one-hundredth that of conventional grindstones. In contrast, it is five to fifty times harder than hard polishing pads such as rigid polyurethane foams that have been used in the field of application of the present invention.

A method of manufacturing such a soft grindstone will be described below with reference to examples. Preferred examples of particles 21 are silica, ceria and alumina particles. Particles with a particle size of 0.01-1 μm enable high treatment rates without causing scratches. As for the resin 22 for binding particles, high-purity organic resins such as phenolic resins are preferable in the present invention. After kneading with the binder resin, the particles are solidified by applying an appropriate pressure, and then, if necessary, subjected to treatment such as thermal curing. With this manufacturing method, the hardness of the resulting grindstone can be controlled by appropriately selecting the type of binder resin and the applied pressure. In the present invention, the hardness of the grindstone used is controlled so that the modulus of elasticity is 5-500 kg/mm ² .

An example of processing using the grindstone produced by the above method will be described below. Satisfactory treated surface can be obtained when a 1 micron thick silica film is treated with a grinding stone with an elastic modulus of 100 kg/ ^mm2 obtained by bonding cerium oxide with a particle size of 1 micron with phenolic resin, the resulting surface is rough The precision is 2nmRa, and the excellent pattern width dependence of 0.3+0.01μm/min relative to all types of pattern processing speed in the range of 10mm-0.5μm. Any unevenness in the surface treatment of the wafer that occurred when the hard polishing pad was used was not observed. This is presumed to be because the process of the present invention uses a different bonded abrasive than the conventional process using no abrasive.

Although only pure water was provided as the polishing liquid in the above processing examples, it goes without saying that alkaline or acidic liquids as in conventional polishing techniques may be provided depending on the type of workpiece. When the workpiece is silica or silicon, an alkaline solution is preferred, and when the workpiece is a metal such as aluminum or tungsten, an acidic solution is preferred.

When a higher level of surface roughness is required, it is obvious that this requirement can be met by finishing the surface of the workpiece with a soft polishing pad after polishing with the above-mentioned grindstone.

If the modulus of elasticity of the grinding stone used exceeds the above range, satisfactory processing cannot be performed. More specifically, if the modulus of elasticity of the grindstone is less than 5 kg/mm ² , only small-width patterns can be quickly polished, that is, the dependence of the pattern width becomes significant, resulting in failure to planarize the memory device. On the contrary, if the modulus of elasticity of the grinding stone used is greater than 500 kg/mm ² , no matter how small the particle size of the grinding stone is, there will still be a scratching problem to be solved. In other words, only when the modulus of elasticity of the grinding stone is in the range of 5-200kg/ ^mm2 suggested here, can it be suitable for semiconductor processing. A more preferred range is 50-150 kg/mm ² .

Even under the above-mentioned conditions of using a grinding stone, if an excessive polishing pressure is applied to the pattern to be polished in consideration of improving the processing efficiency, a processing damage problem different from the above-mentioned scratch problem will occur, depending on the pattern to be polished. shape. The problem of dealing with damage will be explained below.

As shown in FIG. 6 , when polishing is performed with a hard grindstone or a polishing pad 11H, the surface of the polishing tool will only contact the convex portion of the step-shaped pattern during the polishing process. At this time, if excessive polishing pressure is added on the figure, the end 35 of the figure is subjected to the moment introduced by the frictional force, and peeling or collapse will occur as shown by the dotted line 36, or fine grains will occur at the base of the figure. The Crack 37 . Although it varies depending on the processing conditions, the depth of the fissure 37 is often greater than the desired level of planarization, adversely affecting the reliability of polished products such as semiconductor devices. Due to the damage problem of such fine patterns, planarization work needs to be carried out slowly with low pressure using a hard polishing tool, which requires a considerable processing time.

The above-mentioned problems can be solved by a method that will be described below. The cause of the above pattern damage and the basic idea of the present invention for preventing such damage will be described below with reference to FIG. 7. FIG. In the same figure, the upper two figures show the situation where the raised pattern on the wafer substrate is pressed onto the hard polishing pad 11H, and the lower two figures show the stress distribution acting on the pattern. Just after polishing begins, the pattern ends are still angled, so the stress is concentrated at each end of the wide pattern 101, as indicated by 102, reaching a maximum value of more than ten times the average stress. In addition, the stress 104 acting on the narrow pattern 103 is also close to the stated maximum value. In this case, if relative motion occurs between the polishing pad and the wafer substrate, frictional forces proportional to the aforementioned stresses will act on different parts of the pattern. If these frictional forces are greater than the mechanical strength of the pattern material, the ends of the pattern may peel off or fine patterns may collapse. This is what causes graphics damage.

The problem of pattern damage due to the above-mentioned stress concentration at the initial stage of processing can be solved by removing in advance corner portions of the pattern that cause stress concentration and removing fine patterns. More specifically, the problem can be solved by rounding corner portions 105 of wide patterns as shown in FIG. The stress distribution of this pattern does not concentrate, as shown in the lower part of the same figure, so that a large polishing pressure can be applied even with a polishing tool harder than the prior art polishing tool. As a result, it is possible to realize processing with minimal dependence on the pattern width in a short time.

The above basic idea can be realized by two polishing steps. Here, specific examples will be described in detail below with reference to FIGS. 8( a ) to 8 ( e ). The first step (Fig. 8 (a) and 8 (b)), utilizes soft polishing pad 11L (the pad that fine hole is arranged on the pad surface, for example SUPREMERN, the product of RODEL NITTA company) and polishing suspension (not shown) , the wafer surface 31 needs to be processed for about one minute for polishing. As the polishing suspension, any of the most commonly used ones such as colloidal silica, cerium oxide, and alumina can be used. As shown in FIG. 8( c ), the submicron-scale fine pattern parts that existed before the treatment were removed by polishing, and the corners of the large patterns were rounded.

Next, in the second step, use a hard polishing tool 11H with a strong planarization effect, such as a grindstone with the configuration shown in FIG. 5, to polish for about 3 minutes. Since the fine patterns that are vulnerable to damage have been removed in the first step above, even if a polishing tool harder than the first step is used, cracks will not occur at the base of the fine patterns, and a damage-free planarization process can be performed, as shown in Figure 8(c ) shown.

The polishing tool used in the second polishing step is not particularly limited as long as it can polish the wafer surface flatly and at high speed. Not only polishing stones can be used, but also the very common combination of conventional hard polishing pads formed of polyurethane foam with colloidal silica. However, using a grinding stone with an elastic modulus in the range of 5-500kg/ ^mm2 , a flat and crack-free polished surface can be obtained in a short time.

In this way, by first removing the easy-to-crack pattern portion with a soft tool, and then performing a planarization process with a high-rigidity hard tool with a strong shape establishing effect, a substantially non-damaged polished surface can be obtained. This effect was discovered for the first time through specific experiments conducted by the present inventors. The technique of using multiple polishing steps to obtain a finished surface has been known heretofore, as disclosed in Japanese Patent Laid-Open Nos. Sho 1-42823 and Hei 2-267950. In all these known methods, a smoothing step intended to remove the damage produced during the polishing step is generally followed by a high-efficiency but damaging polishing step. For this reason, the polishing pad used in the first step is harder than the polishing pad used in the second step. The present invention, on the contrary, intends to remove the factors causing this processing damage at first, so the technical idea of the present invention is quite different from the known methods.

10(a)-(e) show an example of the fabrication process of the present invention for a memory cell including a transistor and a capacitor. Fig. 10 is a sectional view taken along line A-A' in Fig. 11. In these drawings, numeral 110 denotes a source region, numeral 120 denotes a drain region, numerals 111 and 121 denote connecting portions of the connection regions 110 and 120, respectively, numeral 210 denotes a capacitor lower electrode, numeral 230 denotes a capacitor upper electrode, and numeral 106 denotes a bit line. , numeral 141 denotes a gate electrode.

Figure 10(a) is a cross-sectional view of a P-type silicon substrate 101, on which a silicon oxide element isolation film 102 with a thickness of 800 nm has been formed for electrical isolation between memory cells, and a silicon oxide element isolation film 102 has been formed on the substrate by selective oxidation. A silicon oxide film used as a gate insulating film of a switching MOS transistor. Thereafter, boron is doped by ion implantation to control the threshold voltage of the MOS transistor, and a 300 nm thick polysilicon film is deposited as the gate electrode 141 by chemical vapor deposition (hereinafter simply referred to as CVD). Next, as shown in FIG. 10( b ), using a known photoetching technique, the gate electrode 141 and the gate insulating film 130 of the MoS transistor are formed. Phosphorus is doped into the polysilicon film to make it conductive. Subsequently, arsenic is doped by ion implantation to form the source region 110 and the drain region 120 of the MOS transistor.

Next, as shown in FIG. 10(c), a 500nm thick PSG (phosphorous glass) film 103 is deposited on the substrate surface by CVD as an interlayer insulating film, and then planarized to about 200nm. The modulus of elasticity of the grindstone used to polish the PSG film 103 is 50 kg/mm ² .

Then, a connection portion 111 is formed on the PSG film, and a bit line 106 is formed (FIG. 11).

Next, as shown in FIG. 10(d), a PSG film 104 with a thickness of 500nm is deposited by CVD as an interlayer insulating film, and then planarized polishing is performed, and a window is opened by photoetching to form a connection portion 121. The modulus of elasticity of the grindstone used to polish the PSG film 104 is 50 kg/mm ² . If the polishing of the PSG film is performed with a grinding stone with an elastic modulus of 50 kg/ ^mm2 by polishing the same film with a conventional soft polishing pad, the damage in polishing can be reduced.

Subsequently, a polysilicon film serving as the capacitor lower electrode 210 is formed by CVD and processed into a desired shape. In addition, phosphorus is doped in this polysilicon film to make the film conductive. Next, a capacitive insulating film 220 and a capacitive electrode 230 are formed on the polysilicon film (FIG. 10(e)).

Using the above method, the surface of the memory cell can be made flatter than in the prior art, and a semiconductor device with fine structure and high reliability can be obtained.

The configuration of a processing apparatus suitable for carrying out the present invention will be described below with reference to FIG. 9 . The device is actually a two-platen, two-head structure polishing device, but is characterized by the polishing tools on the platen and the method of operating them. Both the grindstone platen 51 with the above-mentioned low elastic modulus grindstone bonded to its upper surface and the polishing platen 52 with the polishing pad bonded to its upper surface rotate at a constant speed of about 20 rpm. The handling manipulator 54 will take out the wafer 55 to be processed from the loading box 53, and place it on the load ring 57 carried on the direct acting carrier 56. Then, the direct acting carrier 57 moves to the left in the figure to reach the loading/unloading position, on which the polishing arm A58 rotates, and the wafer 55 is vacuum-clamped on the lower side of the wafer polishing fixture (holding) device 59 provided at the end of the polishing arm. Next, the polishing arm A58 is rotated so that the fixer 59 is positioned on the polishing pad platen 52 . The wafer 55 attached to the lower side of the holder is pushed down onto the polishing pad 52 while the holder 59 rotates, so that the wafer is polished for about 1 minute while a polishing suspension (not shown) is supplied. Through this polishing operation, sub-micron-scale fine pattern portions on the wafer surface, which are susceptible to handling damage as previously described, are removed, and corner portions of large-sized patterns are rounded.

After the above-mentioned first polishing step is completed, the polishing arm A58 is rotated so that the wafer polishing holder 59 is positioned on the grindstone platen 51 . Then, while the holder 59 is rotated, the wafer 55 held on the lower side of the holder is pushed down onto the grindstone platen 51, a polishing suspension (not shown) is supplied in the same manner as above, and the wafer 55 is ground. About two minutes. After the second polishing step finished, the polishing arm A58 was rotated again so that the wafer polishing fixture 59 was positioned at the position of the polishing platen 52, and the wafer 55 was polished for about one minute in the same manner as above. This polishing operation after the grinding process is used to remove minor scratches etc. caused in the grinding process. Of course, the polishing process in question can be omitted, depending on the grinding conditions or desired surface roughness level.

The polishing process is completed through the above three-step polishing, and then the wafer is cleaned through the cleaning process. The polishing arm A58 is rotated so that the wafer polishing holder 59 is positioned above the cleaning position where the rotating brush 60 is located. When rotating, the rotating brush 60 cleans the processing surface of the wafer 55 sandwiched under the holder 59 by the rinse brush. After the cleaning is finished, the direct acting carrier 56 moves upwards to the above-mentioned cleaning position to receive the wafer released from the vacuum chuck of the holder 59 .

The rotary brushing used above may be replaced by a cleaning method using water nozzles under the action of ultrasonic waves.

Then, when the direct acting carrier 56 returns to the loading/unloading position, the wafer handling manipulator 54 clamps the processed wafer and loads it into the unloading box 61 . These are one operating cycle of polishing arm A58. Simultaneously with these operations, the polishing arm B62 also works in the same manner. Of course, this requires efficient use of both polishing platforms in a time-sharing fashion. The operation sequence of polishing arm B62 is the same as that of polishing arm A58, but its phase lags by half a period. That is, the buffing arm B62 starts operating in synchronization with the above-mentioned second buffing step.

The structure of the above embodiment is applicable to the situation where there are two polishing arms. In this configuration, if there is a point where the rotational paths of the two polishing arms intersect or touch each other, and if there is provided a stop position for a pair of cleaning brushes and a direct action loading/unloading carrier at that point, the two polishing arms can achieve their related functions.

Although the above-described embodiment employs two polishing arms, it goes without saying that only one polishing arm may be used for simplification of the structure. On the contrary, in order to improve the output of equipment, more than three polishing arms can be used, or a plurality of wafer polishing holders can be fixed on a single polishing arm, and although two independent rotating platforms for pads and grinding stones are used , but only one rotating platform can be used. In this case, the ring-shaped grinding stone is arranged on the periphery of the rotating platform, and the polishing pad is placed in the middle of the platform. The rotating platform can also be tilted to reduce the vertical foot of the equipment (the raised area of the installation).

The invention can be applied not only to semiconductor devices, but also to liquid crystal display devices, microfabrication, disk substrates, optical disk substrates, Fresnel lenses, and other optical components with fine surface structures.

Claims (6)

1. A method for manufacturing a semiconductor device, which is used to planarize a film that is formed on a semiconductor substrate surface and has a concave-convex pattern by utilizing at least a first polishing tool and a second polishing tool step by step, comprising the following steps: alternately pressing the semiconductor substrate with the concavo-convex pattern formed on its surface against the surface of the first polishing tool and the surface of the second polishing tool; and causing relative motion between the surface of the semiconductor substrate and the surfaces of the first polishing tool and the second polishing tool; Wherein, the modulus of elasticity of the first polishing tool used first is smaller than the modulus of elasticity of the second polishing tool used subsequently. 2. The semiconductor device manufacturing method according to claim 1, wherein the first polishing tool used is a polishing pad including a resin. 3. The semiconductor device manufacturing method according to claim 1, wherein the second polishing tool includes abrasive grains and a material for bonding and fixing the abrasive grains. 4. The semiconductor device manufacturing method according to claim 3, wherein the elastic modulus of the second polishing tool is 5-500 kg/mm ² . 5. semiconductor device manufacture method as claimed in claim 3, it is characterized in that the abrasive particle as a kind of component of this second polishing tool is any one or their mixture in silicon dioxide, cerium oxide and aluminum oxide particle. 6. The semiconductor device manufacturing method according to claim 3, wherein the abrasive grains which are a component of the second polishing tool have a particle diameter of not less than 0.01 micrometer and not more than 1 micrometer.

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