CN1383207A - Electrostatic discharge protection circuit triggered by high current - Google Patents

Abstract

A high current triggered ESD protection circuit. Which is electrically coupled to the contact and a reference potential to discharge an electrostatic discharge current generated at the contact. The electrostatic discharge protection circuit comprises a substrate in a first conductive shape, a well region in a second conductive shape, a first doped region in the first conductive shape and a second doped region in the second conductive shape. The substrate is electrically coupled to a reference potential. The well region is arranged on the substrate and electrically coupled to the contact. The first doped region is electrically floated on the surface of the well region. The second doped region is disposed on the substrate and electrically coupled to a reference potential. The ESD current of the contact provides voltage to make the interface between the well region and the substrate collapse, and trigger the lateral bipolar transistor formed by the well region, the substrate and the second doped region to release the electrostatic discharge current. The first doped region reduces a potential difference from the contact to a reference potential when the ESD current is greater than a predetermined current.

Description

Electrostatic discharge protection circuit triggered by high current

The present invention relates to an electrostatic discharge (electrostatic discharge, ESD) protection circuit, especially a kind of ESD protection circuit triggered by high current, the ESD protection circuit of the present invention can provide good electrostatic discharge protection on the one hand, can avoid ESD on the other hand The protective circuit latches up during normal operation.

Generally speaking, in order to protect the finished semiconductor chip from being damaged by the high voltage generated by external static-charged objects, an ESD protection circuit is provided between the input and output ports and the power port of the current semiconductor chip. According to the requirements on the circuit, the ESD protection circuit should be in an open state during normal operation, so that the power port and the input and output ports can maintain normal operation; only when an ESD event occurs at one end of the ESD protection circuit, the ESD protection The circuit presents a state close to short circuit, which is used to release the ESD current to protect the internal circuit of the semiconductor chip.

The known ESD protection circuits can be roughly divided into two types, one is based on a bipolar transistor (bipolar transistor), and the other is based on a semiconductor control rectifier (SCR).

The bipolar transistors in the ESD protection circuit are generally composed of parasitic bipolar transistors generated by the source/base/drain of the MOS transistor in the output port. Because the MOS transistor at the output port must have a lot of thrust, the parasitic bipolar transistor can also dissipate a large amount of current in the event of an electrostatic discharge event. However, in terms of the ESD protection circuit between the input port and the power line, such a method will increase a very large chip area. Moreover, the holding voltage Vh (holding voltage) of the bipolar transistor is generally relatively high, about 7 volts or more. Therefore, under the flow of a large amount of ESD current, high heat will be generated on the bipolar transistor. If the ESD current only flows through a local area of the MOS transistor, it is easy to cause the MOS transistor to burn out. Therefore, it is very difficult to design an electrostatic protection circuit based on bipolar transistors.

The current popular ESD protection circuit uses SCR as the main component, which has the advantages of low holding voltage Vh (~1.6 volts), low trigger current and small semiconductor chip area consumption. However, when the ESD protection circuit designed in this way is subjected to a system-level electromagnetic compatibility (EMC) ESD test, problems may arise. The EMC/ESD test is performed after the entire system is installed and the power supply is provided. When the EMC/ESD test is performed, the SCR can indeed discharge the ESD current on an input and output port. However, the power supply generally has a voltage greater than 3 volts. If the original voltage on the I/O port before the EMC/ESD test is close to the power supply voltage (~3V), then after the EMC/ESD test, the SCR will maintain the voltage on the I/O port at the holding voltage Vh (~1.6 volts), which will cause a shutdown of the entire system, and even burn some of the semiconductor chips.

In order to overcome the deficiencies in the prior art, the purpose of the present invention is to provide a high-current trigger ESD protection circuit, which has the characteristics of small area occupied by semiconductor chips, low holding voltage and high trigger current, so as to solve the above-mentioned problems. question.

According to the above purpose, the present invention proposes a high current trigger ESD protection circuit. The ESD protection circuit of the present invention is electrically coupled to a contact point and a reference potential, and is used for releasing the electrostatic discharge current generated from the contact point. The electrostatic discharge protection circuit includes a substrate of a first conductivity type, a well region of a second conductivity type, a first doped region of the first conductivity type and a second doped region of the second conductivity type. The substrate is electrically coupled to the reference potential. The well region is disposed on the substrate and electrically coupled to the contact. The first doped region is electrically floating on the surface of the well region. The second doped region is disposed on the substrate and electrically coupled to the reference potential. Wherein, the ESD current on the contact provides a voltage to collapse the junction between the well region and the substrate, and triggers a lateral bipolar transistor formed by the well region, the substrate and the second doped region, to discharge the electrostatic discharge current. The first doped region is used to reduce the potential difference between the contact point and the reference potential when the electrostatic discharge current is greater than a predetermined current.

From the viewpoint of the circuit, the present invention further provides a high-current trigger ESD protection circuit coupled to a contact and a reference potential for releasing the ESD current generated from the contact. The electrostatic discharge protection circuit of the present invention includes a bipolar transistor and a first doped region of a first conductivity type. The bipolar transistor includes an emitter, a base and a collector. Wherein the emitter and the base are both electrically coupled to the reference potential, and the collector is formed by a collector region of a second conductivity type and is electrically coupled to the contact. The first doped region is floatingly arranged in the collector region and forms a junction with the collector region. Wherein, the electrostatic discharge current causes the junction between the base and the collector to collapse, triggering the lateral bipolar transistor to discharge the electrostatic discharge current. Wherein, the first doped region is used to reduce the potential difference between the contact point and the reference potential when the electrostatic discharge current is greater than a predetermined current.

When an ESD event occurs on the junction, the junction between the base and the collector collapses first and triggers the bipolar transistor. The potential on the contact is then maintained at a first clamping potential. If the current continues to increase above a predetermined current, the floating first doped region will act together to maintain the potential on the contact at a lower second clamping potential. The first clamping potential and the predetermined current can be adjusted according to layout variations, and the second clamping potential is approximately equal to 1.6 volts.

For the same reason, the present invention further provides a high-current-triggered electrostatic discharge protection circuit. The electrostatic discharge protection circuit of the present invention is electrically coupled to a contact point and a reference potential for releasing the electrostatic discharge current generated from the contact point. The electrostatic discharge protection circuit includes a substrate of a first conductivity type, a well region of a second conductivity type, a first doped region of the first conductivity type and a second doped region of the second conductivity type. The substrate is electrically coupled to the reference potential. The well region is set on the substrate and is electrically coupled to the contact. The first doped region is arranged on the surface of the well region and is electrically coupled to the contact. The second doped region is electrically floating on the substrate.

As far as the circuit is concerned, the present invention also provides a high-current trigger ESD protection circuit coupled to a contact and a reference potential to release the ESD current generated from the contact. The ESD protection circuit includes a dual A polarity transistor and a second doped region of a second conductivity type. The bipolar transistor includes an emitter, a base and a collector. Both the emitter and the base are electrically coupled to the contact, and the collector is formed with a collector region of a first conductivity type and is electrically coupled to the reference potential. The second doping region is floatingly arranged in the collector region and forms a junction with the collector region.

The first conductivity type can be n-type, while the second conductivity type is p-type; on the contrary, if the first conductivity type can be p-type, and the second conductivity type is n-type.

A first advantage of the present invention is that the area of the ESD protection circuit is small. Because the second clamping potential is quite low, the power consumed in the ESD protection circuit can be quite small, and the area occupied by the ESD protection circuit can be small without burning out the components therein.

The second advantage of the present invention is that no latch-up event occurs during EMC/ESD testing. As long as the first clamping potential is greater than the potential during normal operation and the predetermined current is greater than the maximum current during the EMC/ESD test, no latch-up event will occur during the EMC/ESD test.

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, a preferred embodiment is specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Brief description of the drawings:

Fig. 1 is the chip sectional schematic diagram of the first embodiment of ESD protection circuit of the present invention:

2A and 2B are schematic circuit diagrams of FIG. 1;

Fig. 3 is the current-voltage curve diagram of the ESD protection circuit in Fig. 1 and the ESD protection circuit that known SCR constitutes;

Fig. 4 is the current-voltage curve drawn by the experimental data of different distances between the first doped region and the third doped region;

Figure 5A and Figure 5B are the second embodiment and the third embodiment of the ESD protection circuit of the present invention;

6A to 6C are the fourth embodiment of the ESD protection circuit of the present invention;

Fig. 7A is the fifth embodiment of the ESD protection circuit of the present invention;

FIG. 7B is a schematic circuit diagram of FIG. 7A;

8 is an embodiment of the ESD protection circuit of the present invention when the first conductivity type is n-type and the second conductivity type is p-type;

FIG. 9 is an embodiment of the ESD protection circuit of the present invention when the floating region is disposed on the substrate;

Fig. 10A or Fig. 10B is the equivalent circuit diagram of Fig. 9;

Figure 11A or Figure 11B are two ways to reduce the trigger voltage of the ESD protection circuit in Figure 9

Example;

FIG. 12A or FIG. 12B are two embodiments in which n-type MOS transistors are used to reduce the trigger voltage of the ESD protection circuit in FIG. 9;

13A to 13D are embodiments in which a p-type sixth doped region is disposed on the junction between the well region and the substrate; and

FIG. 14 is another embodiment of the ESD protection circuit of the present invention when the first conductivity type is n-type and the second conductivity type is p-type.

Description of figure number:

10, 40 contact 12, 42 base

14, 44 well region 16, 46 first doped region

18, 48 second doping region 20, 50 third doping region

22, 52 fourth doped region 28, 58 fifth doped region

30, 60 field oxide layer 78 sixth doped region

Example:

Please refer to FIG. 1 . FIG. 1 is a schematic cross-sectional view of a first embodiment of the ESD protection circuit of the present invention. The present invention provides an ESD protection circuit for releasing the ESD current on the contact 10 to a reference potential, such as VSS in FIG. 1 . The ESD protection circuit comprises a substrate 12 of a first conductivity type, a well region 14 of a second conductivity type, a first doped region 16 of a first conductivity type, a second doped region 18 of a second conductivity type and a A third doped region 20 of the second conductivity type and a fourth doped region 22 of the first conductivity type. For the convenience of explanation, the first conductive type is p-type, and the second conductive type is n-type. The substrate 12 is electrically coupled to the reference potential VSS through the fourth doped region 22 . That is, the fourth doped region 22 is disposed on the surface of the substrate 12 as an ohmic contact of the substrate 12 , and the fourth doped region 22 is electrically coupled to the reference potential VSS. The well region 14 is electrically coupled to the contact 10 through the third doped region 20 . That is, the third doped region 20 is disposed in the well region 14 as an ohmic contact of the well region 14 , and the third doped region 20 is electrically coupled to the contact 10 . The first doped region 16 is electrically floating and disposed on the surface of the well region 14 . The first doped region 16, the well region 14 and the substrate 12 constitute a vertical pnp bipolar transistor. The second doped region 18 is disposed on the surface of the substrate 12 and electrically coupled to the reference potential VSS. The well region 14, the substrate 12 and the second doped region 18 constitute a lateral npn bipolar transistor. The substrate 12 includes a parasitic resistor R-sub, and the opposite well region 14 also includes a parasitic resistor R-well, as shown in FIG. 1 .

Please refer to FIG. 2A or FIG. 2B , both of which are schematic circuit diagrams of FIG. 1 . From a circuit point of view, the well region 14 (collector region), the substrate 12 and the second doped region 18 constitute the collector, base and emitter of the lateral npn bipolar transistor, respectively. (emitter). The collector is electrically coupled to the contact point 10 through the resistor R-well, the base is electrically coupled to the reference potential VSS through the resistor R-sub, and the emitter is directly electrically coupled to the reference potential VSS. The collector and base of the vertical pnp bipolar transistor are electrically coupled to the base and collector of the lateral npn bipolar transistor respectively, and the emitter of the vertical pnp bipolar transistor is not connected to any contact, presenting The floating state is shown in Figure 2A. From another perspective, there is a reverse diode between the resistor R-well and the emitter of the vertical pnp bipolar transistor, as shown in Figure 2B.

Please refer to FIG. 3. FIG. 3 is a current-voltage curve (IV curve) of the ESD protection circuit in FIG. 1 and the ESD protection circuit formed by the known SCR. The solid line in FIG. 3 represents the IV curve of the ESD protection circuit in FIG. 1 . When the first doped region 16 in FIG. 1 is directly electrically coupled to the contact 10, the entire circuit becomes a known ESD protection circuit composed of SCRs, and the dotted line represents the IV curve of the ESD protection circuit composed of SCRs. The IV curve of the SCR is already a known result, and will not be described here. However, the IV curve of the ESD protection circuit of the present invention is different from the result of the known SCR. Here, it is divided into sections I, II, III and IV for explanation.

Section I is the same as the I-V curve of the known SCR. When the potential of the contact 10 reaches the breakdown voltage (that is, the trigger potential Vt) of the junction between the well region 14 and the substrate 12, the lateral npn bipolar transistor is connected. Triggered by the surface leakage current, the current starts to rise with the voltage. The actual physical principle of the second section is not yet clear, one possible reason is that the first doped region 16 and the third doped region 20 start to conduct and generate a parasitic SCR, but the total current gain required by the parasitic SCR (current gain) β has not reached 1, so the potential of the contact 10 is clamped at a first clamping potential Vhl, as shown in section II. Because during clamping, only one lateral npn bipolar transistor is turned on in the present invention, while two bipolar transistors are turned on in the SCR, so the first clamping potential Vhl is higher than the clamping potential Vh-SCR of the SCR.

When the current is greater than a predetermined current IL, the well region 14 will form a high injection status, that is, the concentration product of electrons and holes in the well region 14 is greater than the square of the intrinsic concentration. At this time, a large amount of electron holes are formed on the junction between the first doped region 16 and the well region 14, the electrical isolation effect of the junction gradually decreases, and the current gain β of the parasitic SCR gradually approaches 1, so The potential on the contact 10 gradually drops, as shown in section III in FIG. 3 . When a large amount of current flows from the well region 14 into the first doped region 16 , the voltage drop across the well region 14 from the first doped region 16 may be greater than 0.7 volts and trigger the vertical pnp bipolar transistor to turn on. When both the vertical pnp bipolar transistor and the lateral npn bipolar transistor are turned on, the ESD protection circuit of the present invention can clamp the potential of the contact 10 at a very low second clamping potential, which is about 1.6 volts, as shown in the first Section IV is shown. The predetermined current IL required to generate the third section can be controlled through empirical values and layout.

Please refer to FIG. 4, which is a schematic diagram drawn according to four sets of experimental data. The curves generated by the four sets of experimental data are L1, L2, L3 and L4 respectively. The distances between the first doped region 16 and the third doped region 20 in the ESD protection circuit that generate the L1, L2 and L3 curves are 1um, 2um and 3um respectively, while the L4 curve is without the first doped region 16 result of the ESD protection circuit. It can be clearly seen that the L4 curve is the IV curve of the collector after the emitter and base of a simple bipolar transistor are grounded. The trends of the curves L1 to L3 can be explained as follows. When the distance between the first doped region 16 and the floating third doped region 20 is farther, it means that the conduction chance of the first doped region 16 and the third doped region 20 is lower, that is, more The current can make the first doped region 16 and the third doped region 20, as shown in the right half of FIG. 4 . At the same time, when the distance between the first doped region 16 and the floating third doped region 20 is farther, it means that the R-well is larger, that is to say, a smaller current is required to make the first doped region 16 The voltage drop between the third doped region 20 reaches 0.7 volts to trigger the SCR, as shown in the left half of FIG. 4 .

The ESD protection circuit of the present invention has two controllable parameters, the first clamping potential Vhl and the predetermined current IL. A suggested state is to make the first clamping potential Vhl greater than the supply potential of the power supply when the chip operates normally, and the predetermined current IL is between the general ESD test current and the maximum current during EMC/ESD testing. In this way, when performing EMC/ESD testing, the ESD protection circuit of the present invention can release the ESD current through the first section and the second section, and after the EMC/ESD test, because the power supply potential is lower than the first clamping potential Vhl , so the ESD protection circuit will return to the closed state. When conducting general ESD tests in human body mode and machine mode, a large amount of current can be released through the IV section of the IV curve, providing good ESD protection.

Please refer to FIG. 5A or FIG. 5B . FIG. 5A or FIG. 5B are the second embodiment and the third embodiment of the ESD protection circuit of the present invention. In order to reduce the trigger potential Vt, the present invention provides two other embodiments, as shown in FIG. 5A or FIG. 5B . An n-type fifth doped region 28 is disposed on the junction formed by the well region 14 and the substrate 12 . Because the doping concentration of the fifth doped region 28 is higher than that of the well region 14, relatively, the breakdown voltage of the pn junction formed by the fifth doped region 28 will be lower, so the overall trigger voltage Vt of the ESD protection circuit can be lowered. In FIG. 5B , an additional field oxide layer 30 is added on the surface of the substrate 12 next to the fifth doped region 28 . The substrate 12 below the field oxide layer 30 usually increases the doping concentration, so the breakdown voltage of the pn junction at the junction of the edge of the field oxide layer 30 and the fifth doped region 28 will be lower, so the trigger voltage Vt also decreases accordingly.

Please refer to FIG. 6A , which is a fourth embodiment of the ESD protection circuit of the present invention. The ESD protection circuit of the present invention may further include a MOS transistor M1, which is disposed on the substrate 12 and includes a gate and two sources/drains. Wherein, one source/drain is electrically coupled to the well region 14 , and the other gate and the gate are electrically coupled to the reference potential VSS. For example, one source/drain of M1 is formed by the fifth doped region 28 , and the other source/drain of M1 is formed by the second doped region 18 , as shown in FIG. 6A . 6B and 6C are equivalent circuit diagrams of FIG. 6A . A source/drain of M1 has two expressions in the circuit, as shown in Figure 6B, one is directly connected to the contact 10, and the other is electrically coupled to the contact 10 through the resistor R-well, as shown in Figure 6B 6C. M1 can reduce the trigger voltage Vt, which is widely known in the prior art and will not be explained here.

Please refer to FIG. 7A and FIG. 7B , FIG. 7A is a fifth embodiment of the present invention, and FIG. 7B is a schematic circuit diagram of FIG. 7A . The gate of M1 can use an RC delay circuit to identify the ESD event and trigger the ESD protection circuit, as shown in FIG. 7A . The ESD protection circuit also includes a resistor RG and a capacitor CG. Two ends of the resistor RG are respectively electrically coupled to the gate of M1 and the reference potential VSS, and two ends of the capacitor CG are respectively electrically coupled to the gate of M1 and the contact 10 . As for the circuit diagram, it is only Figure 6B or Figure 6C plus an RC delay circuit, as shown in Figure 7B. When an ESD event occurs at the contact point 10, the gate potential of M1 will be increased due to the electrical coupling effect of the capacitor CG, thereby triggering the conduction of the lateral npn bipolar transistor early to release the ESD current.

Of course, the use of n-type or p-type semiconductors as the first conductivity type is only an engineer’s choice. Figures 1 to 7 are examples where the first conductivity type is p-type and the second conductivity type is n-type. Figure 8 It is an embodiment in which the first conductivity type is n-type and the second conductivity type is p-type. As shown in Figure 8, the electrostatic protection circuit of the present invention includes an n-type substrate 12b, a p-type well region 14b, an n-type first doped region 16b, and a p-type second doped region 18b And a p-type third doped region 20b and an n-type fourth doped region 22b. The first doped region 16b, the well region 14b and the substrate 12b constitute an npn bipolar transistor. The well region 14b, the substrate 12b and the second doped region 18b constitute a pnp bipolar transistor. The first doped region 16b is still floating. The well region 14b is coupled to the contact 10b through the third doped region 20b. The second doped region 18b is coupled to a reference potential VDD. The substrate 12b is coupled to the reference potential VDD through the fourth doped region 22b. Such an arrangement can also meet the requirements of the ESD protection circuit.

The present invention also provides an ESD protection circuit to realize the concept of a collector region plus an electrically opposite floating region, as shown in FIG. 9 . The electrostatic discharge protection circuit of the present invention is electrically coupled to a contact 40 and a reference potential VSS for releasing the electrostatic discharge current generated from the contact 40 . The electrostatic discharge protection circuit includes a p-type substrate 42, an n-type well region 44, a p-type first doped region 46, an n-type second doped region 48, an n-type third doped region region 50 and a p-type fourth doped region 52 . The substrate 42 is electrically coupled to the reference potential VSS through the ohmic contact formed by the fourth doped region 52 . The well region 44 is disposed on the substrate 42 and electrically coupled to the contact 40 . The first doped region 46 is disposed on the surface of the well region 44 and is electrically coupled to the contact 40 through the ohmic contact formed by the third doped region 50 . The second doped region 48 is electrically floating and disposed on the substrate 42 . The first doped region 46 , the well region 44 and the substrate 42 respectively form the emitter, base and collector of a pnp bipolar transistor, so the substrate 42 is also called the collector region. The second doped region 48 is floatingly disposed in the collector region and forms a junction with the collector region. 10A and 10B are equivalent circuit diagrams of FIG. 9 . Such an ESD protection circuit can also achieve the result of the IV curve shown in FIG. 3 , and its function has been explained in the previous examples, so it will not be repeated here.

Of course, in order to reduce the trigger voltage Vt of the ESD protection circuit, the ESD protection circuit in FIG. 9 can be changed in many ways. The first variation is to dispose an n-type fifth doped region 58 on the junction formed between the well region 44 and the substrate 42 , as shown in FIG. 11A . Because the concentration of the fifth doped region 58 is higher, the breakdown voltage of the formed junction is lower. The second variation is to provide a field oxide layer 60 next to the fifth doped region 58, as shown in FIG. 11B. The substrate 42 under the field oxide layer 60 is generally heavily doped, so the breakdown voltage at the edge of the field oxide layer 60 (that is, at the junction with the fifth doped region 58 ) is further reduced. The third variation is to dispose an n-type MOS transistor on the substrate 42, as shown in FIG. 12A. The gate 60 of the n-type MOS transistor is coupled to a reference potential VSS. A source/drain is the fifth doped region 58 coupled to the contact 40 through the well region 44 . The breakdown voltage of the source/drain of the n-type MOS transistor to the base (substrate) is lower than the breakdown voltage of the well region 44 to the substrate 42. It is a state known in the art, so the arrangement of FIG. 12A can reduce the ESD protection circuit. The trigger voltage Vt. The gate 60 of the n-type MOS transistor may not be directly connected to the reference potential VSS, but is connected to the reference potential VSS through a resistor RG, and a capacitor CG is provided between the gate 60 and the contact 40, as shown in FIG. 12B Show. The RC circuit formed by the capacitor CG and the resistor RG can be used to detect an ESD event on the contact 40 and then provide a voltage to the gate 60 to trigger the ESD protection circuit.

As shown in FIG. 13A, if the n-type fifth doped region 58 is replaced by the p-type sixth doped region 78, the effect of reducing the trigger voltage of the ESD protection circuit still exists. The p-type doping concentration in the sixth doped region 78 is higher than that of the substrate 42 . Therefore, the breakdown voltage of the junction formed by the sixth doped region 78 and the well region 44 is also lower than that of the original junction between the substrate 42 and the well region 44 . Similarly, a field oxide layer 60 may also be disposed on the surface of the well region 44 and next to the sixth doped region 78 , as shown in FIG. 13B . Most of the well region 44 under the field oxide layer 60 will have relatively dense doping to form a channel stopper (channel stopper), so the breakdown voltage of the pn junction at the edge of the field oxide layer will be higher than that of the pn junction on the surface of the general well region 44 Crash voltage is low. A p-type MOS transistor disposed in the well region 44 can also reduce the trigger voltage of the ESD protection circuit of the present invention, as shown in FIG. 13C . The gate 72 of the p-type MOS transistor is coupled to the contact 40 , and the two sources/drains of the p-type MOS transistor are the first doped region 46 and the sixth doped region 78 respectively. An RC delay circuit (RC delay circuit) can also be added to the circuit in Figure 13C as a detector for detecting ESD events, as shown in Figure 13D. The gate 72 of the p-type MOS transistor is coupled to the contact 40 through a resistor RG, and a capacitor CG is provided between the gate of the p-type MOS transistor and the reference potential VSS. When an ESD event first occurs, the gate of the p-type MOS transistor will be coupled by the capacitor CG to be at a relatively low potential, thereby triggering the entire ESD protection circuit.

Of course, the use of n-type or p-type semiconductors with the first conductivity type is only an engineer’s choice. Figures 9 to 13 are examples where the first conductivity type is p-type and the second conductivity type is n-type, and Figure 14 is An embodiment in which the first conductivity type is n-type and the second conductivity type is p-type. As shown in Figure 8, the electrostatic protection circuit of the present invention includes an n-type substrate 42b, a p-type well region 44b, an n-type first doped region 46b, and a p-type second doped region 48b , a p-type third doped region 50b and an n-type fourth doped region 52b. The first doped region 46b, the well region 44b and the substrate 42b constitute an npn bipolar transistor. The well region 44b, the substrate 42b and the second doped region 48b constitute a pnp bipolar transistor. The second doped region 48b is still floating. The well region 44b is coupled to the contact 40b through the third doped region 50b. The first doped region 46b is coupled to the contact 40b. The substrate 52b is coupled to the reference potential VDD through the fourth doped region 52b. Such an arrangement can also meet the requirements of the ESD protection circuit.

In general, the subject matter of the present invention is to provide an ESD protection circuit mainly using a bipolar transistor. The bipolar transistor may be an npn bipolar transistor or a pnp bipolar transistor. Moreover, in the collector of the bipolar transistor, a floating region with a conductivity type opposite to that of the collector is provided, that is, a floating diode, to achieve the purpose of reducing the clamping potential at high current.

Compared with the known SCR-based ESD protection circuit, the first clamping potential Vhl of the present invention is higher than the power supply potential, so the latch-up problem that must be faced by the SCR-based ESD protection circuit can be avoided. Compared with the known ESD protection circuit mainly based on bipolar transistors, the present invention sets a floating first doped region in the collector region of the lateral npn transistor, so in the high current ESD test, it can obtain A very low second clamping potential. The power consumption of the ESD protection circuit of the present invention can be reduced, so it can be manufactured with a smaller chip area and save costs.

Although the present invention has been disclosed above with a number of preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims in combination with the specification and drawings.

Claims (33)

1. the electrostatic storage deflection (ESD) protection circuit of a high current trigger is electrically coupled to a contact and a reference potential, and in order to discharge the static discharge current that produces from this contact, this electrostatic storage deflection (ESD) protection circuit includes:

The substrate of one first conduction shape is electrically coupled to this reference potential;

The well region of one second conduction shape is located in this substrate, and is electrically coupled to this contact;

First doped region of one first conduction shape, electricity floats is located at this well region surface; And

Second doped region of one second conduction shape is located in this substrate, and is electrically coupled to this reference potential;

Wherein, the static discharge current on this contact provides a voltage that the face that connects between this well region and this substrate is collapsed, and triggers the side direction bipolar transistor that this well region, this substrate and this second doped region are constituted, to discharge this static discharge current;

Wherein, this first doped region is in this static discharge current during greater than a scheduled current, in order to reduce the potential difference of this contact to this reference potential.

2. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 3rd doped region of one second conduction shape, is located in this well region, is electrically coupled to this contact, as the ohmic contact of this well region.

3. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 4th doped region of one first conduction shape, is located at this substrate surface of contiguous this well region, be electrically coupled to this reference potential, as the ohmic contact of this substrate.

4. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this first conduction shape is to be p shape, and this second conduction shape is a n shape.

5. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 5th doped region of one second conduction shape, is located at connecing on the face of this well region and this substrate formation, in order to reduce the breakdown voltage of the face that connects between this well region and this substrate.

6. electrostatic storage deflection (ESD) protection circuit as claimed in claim 5, wherein, this electrostatic storage deflection (ESD) protection circuit also includes a field oxide, is located at the substrate surface that is next to the 5th doped region.

7. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this electrostatic storage deflection (ESD) protection circuit also includes one first conduction shape MOS transistor, be located in this substrate, include a grid and two source/drain electrodes, wherein a source/drain electrode is electrically coupled to this well region, and another source/drain electrode is electrically coupled to this reference voltage with this grid system.

8. as claim 4 or 7 described electrostatic storage deflection (ESD) protection circuit, wherein, a source/drain electrode of this first conduction shape MOS transistor is constituted with the 5th doped region, and another source/drain electrode of this first conduction shape MOS transistor is constituted with this second doped region.

9. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this electrostatic storage deflection (ESD) protection circuit also includes:

One first conduction shape MOS transistor is located in this substrate, include a grid and

Two source/drain electrodes, wherein a source/drain electrode is electrically coupled to this well region, and another source/electric coupling drains

Be bonded to this with reference to electric potential;

One resistance, its two ends are electrically coupled to this grid and this reference potential respectively; And

One electric capacity, its two ends are electrically coupled to this grid and this contact respectively.

10. the electrostatic storage deflection (ESD) protection circuit of a high current trigger is coupled in a contact and a reference potential, and in order to discharge the static discharge current that produces from this contact, it includes:

One bipolar transistor includes an emitter, a base stage and a collector electrode, and wherein this emitter and this base stage all are electrically coupled to this reference potential, and this collector electrode is that the collector area with one second conduction shape is constituted and is electrically coupled to this contact; And

First doped region of one first conduction shape, unsteady is located in this collector area, and connects face with this collector area formation one;

Wherein, this static discharge current make this base stage and this collector electrode between the face that connects collapse, trigger this bipolar transistor, to discharge this static discharge current;

Wherein, this first doped region is in this static discharge current during greater than a scheduled current, in order to reduce the potential difference of this contact to this reference potential.

11. electrostatic storage deflection (ESD) protection circuit as claimed in claim 10, wherein, this electrostatic storage deflection (ESD) protection circuit also includes one first conduction shape MOS transistor, include a grid and two source/drain electrodes, wherein a source/drain electrode is electrically coupled to this collector electrode, and another source/drain electrode is to be electrically coupled to this reference voltage with this grid.

12. electrostatic storage deflection (ESD) protection circuit as claimed in claim 10, wherein, this electrostatic storage deflection (ESD) protection circuit also includes:

One first conduction shape MOS transistor includes a grid and two source/drain electrodes, and wherein a source/drain electrode is electrically coupled to this contact, and another source/drain electrode system is electrically coupled to this with reference to electric potential;

One resistance, its two ends are electrically coupled to this grid and this reference potential respectively; And

One electric capacity, its two ends are electrically coupled to this grid and this contact respectively.

13. electrostatic storage deflection (ESD) protection circuit as claimed in claim 10, wherein, this first conduction shape is to be p shape, and this second conduction shape is to be n shape.

14. as claim 1 or 10 described electrostatic storage deflection (ESD) protection circuit, wherein, this first conduction shape is to be n shape, and this second conduction shape is to be p shape.

15. the electrostatic storage deflection (ESD) protection circuit of a high current trigger is electrically coupled to a contact and a reference potential, in order to discharge the static discharge current that produces from this contact, this electrostatic storage deflection (ESD) protection circuit includes:

The substrate of one first conduction shape is electrically coupled to this reference potential;

The well region of one second conduction shape is located in this substrate, and is electrically coupled to this contact;

First doped region of one first conduction shape is located at this well region surface, and is electrically coupled to this contact; And

Second doped region of one second conduction shape, what electricity floated is located in this substrate;

Wherein, the static discharge current on this contact provide a voltage make this well region and this substrate between the face that connects collapse, and trigger this first doped region, this well region and bipolar transistor that this substrate constituted, to discharge this static discharge current:

Wherein, this second doped region is in this static discharge current during greater than a scheduled current, in order to reduce the potential difference of this contact to this reference potential.

16. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 3rd doped region of one second conduction shape, is located in this well region, is electrically coupled to this contact, as the ohmic contact of this well region.

17. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 4th doped region of one first conduction shape, is located at this substrate surface of contiguous this well region, be electrically coupled to this reference potential, as the ohmic contact of this substrate.

18. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 5th doped region of one second conduction shape, is located at connecing on the face of this well region and this substrate formation, in order to reduce this well region and this substrate between the breakdown voltage of the face that connects.

19. electrostatic storage deflection (ESD) protection circuit as claimed in claim 18, wherein, this electrostatic storage deflection (ESD) protection circuit also includes a field oxide, is located at the substrate surface that is next to the 5th doped region.

20. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit also includes one first conduction shape MOS transistor, be located in this substrate, include a grid and two source/drain electrodes, wherein a source/drain electrode is electrically coupled to this well region, and another source/drain electrode is to be electrically coupled to this reference voltage with this grid.

21. as described in the claim 18 or 20 described electrostatic storage deflection (ESD) protection circuit, wherein, source/drain electrode of this first conduction shape MOS transistor is constituted with the 5th doped region, and another source/drain electrode of this MOS transistor is constituted with this second doped region.

22. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit also includes:

One first conduction shape MOS transistor is located in this substrate, includes a grid and two source/drain electrodes, and wherein a source/drain electrode is electrically coupled to this well region, and another source/drain electrode is electrically coupled to this with reference to electric potential;

One resistance, its two ends are electrically coupled to this grid and this reference potential respectively; And

One electric capacity, its two ends are electrically coupled to this grid and this contact respectively.

23. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit includes the 6th doped region of one first conduction shape in addition, is located at connecing on the face of this well region and this substrate formation, in order to reduce the breakdown voltage of the face that connects between this well region and this substrate.

24. electrostatic storage deflection (ESD) protection circuit as claimed in claim 23, wherein, this electrostatic storage deflection (ESD) protection circuit includes a field oxide in addition, is located at the well region surface that is next to the 6th doped region.

25. electrostatic storage deflection (ESD) protection circuit as claimed in claim 24, wherein, this electrostatic storage deflection (ESD) protection circuit includes one second conduction shape MOS transistor in addition, be located on this well region, include a grid and two source/drain electrodes, wherein a source/drain electrode is electrically coupled to this substrate, and another source/drain electrode is to be electrically coupled to this contact with this grid.

26. as claim 25 or 16 described electrostatic storage deflection (ESD) protection circuit, wherein, a source/drain electrode of this second conduction shape MOS transistor is constituted with the 6th doped region, and another source/drain electrode of this MOS transistor is constituted with the 3rd doped region.

27. electrostatic storage deflection (ESD) protection circuit as claimed in claim 23, wherein, this electrostatic storage deflection (ESD) protection circuit includes in addition:

One second conduction shape MOS transistor includes a grid and two source/drain electrodes, and wherein a source/drain electrode is electrically coupled to this contact, and another source/drain electrode is to be electrically coupled to this with reference to electric potential;

One electric capacity, its two ends are electrically coupled to this grid and this reference potential respectively; And

One resistance, its two ends are electrically coupled to this grid and this contact respectively.

28. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this first conduction shape is to be p shape, and this second conduction shape is to be n shape.

29. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this first conduction shape is to be n shape, and this second conduction shape is to be p shape.

30. the electrostatic storage deflection (ESD) protection circuit of a high current trigger is coupled in a contact and a reference potential, in order to discharge the static discharge current that produces from this contact, it includes:

One bipolar transistor includes an emitter, a base stage and a collector electrode, and wherein this emitter and this base stage all are electrically coupled to this contact, and this current collection polar system is constituted with the collector area of one first conduction shape and is electrically coupled to this reference potential; And

Second doped region of one second conduction shape, unsteady is located in this collector area, and connects face with this collector area formation one;

Wherein, this static discharge current make this base stage and this collector electrode between the face that connects collapse, trigger this bipolar transistor, to discharge this static discharge current;

Wherein, this second doped region is in this static discharge current during greater than a scheduled current, in order to reduce the potential difference of this contact to this reference potential.

31. electrostatic storage deflection (ESD) protection circuit as claimed in claim 30, wherein, this electrostatic storage deflection (ESD) protection circuit includes one first conduction shape MOS transistor in addition, include a grid and two source/drain electrodes, wherein a source/drain electrode is electrically coupled to this collector electrode, and another source/drain electrode is electrically coupled to this reference voltage with this grid system.

32. electrostatic storage deflection (ESD) protection circuit as claimed in claim 30, wherein, this electrostatic storage deflection (ESD) protection circuit includes in addition:

One first conduction shape MOS transistor includes a grid and two source/drain electrodes, and wherein a source/drain electrode is electrically coupled to this contact, and another source/drain electrode is to be electrically coupled to this with reference to electric potential;

One resistance, its two ends are electrically coupled to this grid and this reference potential respectively; And

One electric capacity, its two ends are electrically coupled to this grid and this contact respectively.

33. electrostatic storage deflection (ESD) protection circuit as claimed in claim 30, wherein, this first conduction shape is to be p shape, and this second conduction shape is to be n shape.

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