CN1225784C - Ballgrid array parkaging body - Google Patents

Abstract

The invention discloses a wire bonding ball grid array package, wherein, a power ring corresponding to a core circuit of a chip on a substrate is arranged inside a power ring corresponding to an input/output circuit of the chip, so when the chip is connected by wires When the packaging method is changed to flip-chip packaging, the corresponding power supply pins can be applied to the circuit board originally used to assemble the flip-chip BGA package. In addition, the present invention also discloses a flip-chip bonded ball grid array package, wherein the power ring corresponding to the core circuit of a chip on a substrate is arranged outside the power ring corresponding to the input/output circuit of the chip, so when the When the chip is changed from the flip-chip packaging method to the lead packaging method, the corresponding power supply pins can be applied to the circuit board originally used to assemble the wire-bonded ball grid array package.

Description

Ball Grid Array Package

technical field

The invention relates to a ball grid array package, in particular to a ball grid array package that can be configured with the same power supply pin in lead package and flip-chip package.

Background technique

In the modern information society, microprocessor systems composed of integrated circuits have long been widely used in all aspects of life. All automated home appliances, mobile communication equipment, and personal computers all have traces of integrated circuits, and the main body of integrated circuits is chips (die) produced by using existing semiconductor processes. The process of manufacturing a chip starts with the production of a wafer (wafer), divides a plurality of regions on a wafer, and uses semiconductor technology to form various circuits on each region, and finally performs a process on each region on the wafer. Cut into individual chips. When the chip is obtained, the chip must be electrically connected to a circuit board, such as a printed circuit board (PCB), through a certain method, so that the chip can obtain the required operating voltage through the circuit board to perform A predetermined operation, for example, the chip is an encoding circuit (encoder circuit), when the voltage required for the operation of the encoding circuit is provided, the chip can perform encoding operations on the data signals input by the circuit board, and finally output the code signal to the board. Generally speaking, the way the chip is electrically connected to the circuit board can be a bare chip configuration method in which the chip is directly electrically connected to the circuit board, or the chip is first packaged in a package and then passed through the package. The circuit is electrically connected to the circuit board to receive power and transmit signals.

The main function of the package is to provide the signal transmission interface between the chip and the circuit board and to protect the chip. In addition, due to the current trend of electronic products gradually developing towards thinner, smaller and higher computing speeds, the input/output interface required by the package The number of pins (package pin count) also increases, and the thickness must be thinner and smaller, and the area must be smaller and smaller. In the past, the packaging technology of pin through hole (PTH) was limited by the corresponding board. The size of the insertion hole is limited, so the size of the package body cannot be further reduced, and the number of input/output pins is also limited at the same time, so the packaging technology of surface mount technology (SMT) will gradually replace the package where the pin is inserted. technology to reduce the size of the package body, but the above-mentioned pin insertion and surface mount packaging technologies are all peripheral packaging methods, so there are still disadvantages in reducing the volume of the package body and increasing the number of input/output pins. Inherent limitations. For example, for the packaging technology of surface mount, when the number of pins arranged around the periphery increases, the distance (pitch) between adjacent pins is correspondingly shortened, so when the package is mounted on the circuit board, the Because the distance between adjacent pins is too short, resulting in poor assembly yield, area array (area array) packaging technology has emerged, such as ball grid array (ball grid array, BGA) package, which due to The input/output pins are converted from the peripheral arrangement to the surface matrix arrangement. Not only can the distance between adjacent pins be expanded to improve the assembly pass rate when the package is installed on the circuit board, but the number of input/output pins can also be increased. A substantial increase. According to the electrical connection method of the chip, the BGA package can be mainly divided into a wire bonding BGA package and a flip chip bonding BGA package.

Please refer to FIG. 1 . FIG. 1 is a first schematic diagram of a conventional wire bonding BGA package 10 . The wire bonding BGA package 10 includes a die 11 and a substrate 12 . The chip 11 includes a core circuit (core circuit) 13 for performing a predetermined operation, a plurality of input/output circuits 14a, 14b, 14c for controlling each signal input and output to the core circuit 13, and a plurality of bonding pads (bonding pad ) 18 is used to electrically connect the chip 11 and the substrate 12 . Substrate 12 is provided with a plurality of power rings (power ring) 20a, 20b, 20c, 20d respectively to provide different operating voltages, and a plurality of welding points 22, and power rings 20a, 20b, 20c, 20d and welding points 22 are set on the same first wiring layer 28 . For example, when the package body 10 is a north bridge chip (north bridge chip) of a computer system, the chip 11 is used to control signal transmission between high-speed peripheral devices (such as memory and display card) and a microprocessor, That is, the above-mentioned functions are performed by the core circuit 13. In addition, the input/output circuits 14a, 14b, and 14c are used to control a memory, a display card, and signal reception and transmission between a microprocessor and the core circuit 13, respectively. The operating voltages of the memory, display card, and microprocessor are not consistent. For example, the operating voltage of the memory is 2.6 volts, the display card uses accelerated graphics port (AGP) and it needs to use the operating voltage of 1.5 volts, and the microprocessor The operating voltage is 1.2 volts, that is, the memory uses 2.6 volts to represent the high logic level "1" and the ground voltage to represent the low logic level "0", so the corresponding input/output circuit 14a must also use 2.6 volts to It is used as its operating voltage to correctly judge and determine the logic level of the signal, and to smoothly transmit the signal to the memory and receive the output signal from the memory. Similarly, the input/output circuit 14b must also use 1.5 volts as its operating voltage to judge and determine the logic level of the signal, and correctly transmit the signal to the display card and receive the output signal from the display card, while the input/output The circuit 14c must also use 1.2 volts as its operating voltage to judge and determine the logic level of the signal, and correctly transmit the signal to the microprocessor and receive the output signal from the microprocessor. In addition, the working voltage of the core circuit 13 may be different from that of the input/output circuits 14a, 14b, 14c, so the required working voltage (for example, 2.5 volts) must be provided through the substrate 12 . The power rings 20a, 20b, 20c, and 20d are respectively used to provide the operating voltages of the input/output circuits 14a, 14b, 14c and the core circuit 13. Please note that the pads 18 correspond to the input/output circuits 14a, 14b, 14c and the core circuit. The circuit 13 can be used to transmit signals and transmit power. In FIG. 1, the bonding wires 16a, 16b, 16c, and 16d are used to connect the pads 18 and the power rings 20a, 20b, 20c, and 20d to respectively input voltages to the input/output circuits 14a, 14b, 14c and the core circuit 13, In addition, the soldering wire 16e connects the soldering pad 18 and the soldering point 22 for signal transmission. For the convenience of illustration, FIG. 1 does not show all the connections between the soldering wire and the soldering point (sloder joint) 22 . Therefore, with the aid of the bonding wires 16 a , 16 b , 16 c , 16 d , 16 e , the chip 11 can obtain the required operating voltage from the substrate 12 , and the chip 11 and the substrate 12 can transmit signals to each other.

Please refer to FIG. 2 and FIG. 3, FIG. 2 is a second schematic view of the wire bonding BGA package 10 shown in FIG. 1, and FIG. 3 is a wire bonding BGA package 10 shown in FIG. 3' section view. The package body 10 includes a plurality of pins 24 arranged in a matrix on a second wiring layer 30, wherein the second wiring layer 30 includes a plurality of conductive blocks 26a, 26b, 26c, 26d, The pins 24 on the conductive blocks 26a, 26b, 26c, and 26d are respectively used to connect a circuit board to supply power to the input/output circuits 14a, 14b, 14c and the core circuit 13. As shown in FIG. 3, the first wiring The layer 28 and the second wiring layer 30 are respectively disposed on the upper and lower layers of the wire bonding ball grid array package 10 . Please note that FIG. 1 and FIG. 2 are top views, so the conductive blocks 26a, 26b, 26c, 26d and the corresponding power rings 20a, 20b, 20c, 20d are connected to each other through vias (via) 32, so When the package 10 is mounted on a circuit board via its bottom solder ball (solder ball) 34, the pin 24 corresponding to the solder ball is electrically connected to the circuit board, so when a voltage is input from the circuit board, the The voltage then drives the input/output circuits 14a, 14b, 14c and the core circuit 13, similarly, when a signal is input by the circuit board, the signal is then input to the The input/output circuits 14a, 14b, 14c, and when a signal is output by the input/output circuits 14a, 14b, 14c, the signal passes through the pad 18, the welding line 16e, the welding point 22, the through hole 32, the pin 24, And solder balls 34 are output to the circuit board.

Please refer to FIG. 4, FIG. 5 and FIG. 6, FIG. 4 is a first schematic diagram of a conventional flip-chip bonding ball grid array package 40, and FIG. 6 is a cross-sectional view of the flip-chip bonded BGA package 40 shown in FIG. 4 along the line 6-6'. The flip-chip bonding ball grid array package 40 includes a chip 41 and a substrate 42. The chip 41 includes a core circuit 43 and a plurality of input/output circuits 44a, 44b, 44c. The substrate 42 is provided with a plurality of power rings 50a, 50b , 50c , 50d are respectively used to provide different working voltages, and the power rings 50a , 50b , 50c , 50d are arranged on the same first wiring layer 58 . The operation of the core circuit 43 , the input/output circuits 44 a , 44 b , 44 c , and the power rings 50 a , 50 b , 50 c , 50 d are the same as those of the same-named components of the wire bonded BGA package 10 described above, and thus will not be described again. It can be seen from FIG. 5 that the package body 40 includes a plurality of pins 54, which are arranged in a matrix on a second wiring layer 60, wherein the second wiring layer 60 includes a plurality of conductive blocks 56a, 56b, 56c, 56d, the pins 54 on the conductive blocks 56a, 56b, 56c, 56d are respectively used to connect a circuit board to input the working voltage of the input/output circuits 44a, 44b, 44c and the core circuit 43. The main difference between the flip-chip bonded BGA package 40 and the wire-bonded BGA package 10 is that the chip 41 is the flipped state of the chip 11 (as shown in FIG. 1 ), that is, the bonding pads on the chip 11 18 (as shown in FIG. 3 ) is located on the upper surface of the chip 11, and the bonding pad 48 (as shown in FIG. 6 ) on the chip 41 is located on the lower surface of the chip 41, and a metal bump (bump) is formed on the bonding pad 48. ) 66 , such as tin-lead bumps (solder bumps) or gold bumps (gold bumps), so as to be connected to the pads 68 on the first wiring layer 58 of the substrate 42 . In addition, the power rings 50a, 50b, 50c, 50d and the bonding pads 68 (that is, the first wiring layer 58) are all connected to a third wiring layer 70 through a via (via) 62, and through the third wiring layer 70 Wiring (trace), so that the power supply rings 50a, 50b, 50c, 50d can output the operating voltage to the core circuit 43 and the input/output circuits 44a, 44b, 44c through the corresponding pads 68. Similarly, the third wiring layer 70 and The second wiring layer 60 is also electrically connected to each other through the via hole 62. Therefore, the pin 62 can be used to transmit signals and power to the chip 41, just like the wire bonding BGA package 10, flip-chip bonding the BGA package 40. Tin lead balls 64 are also used to connect to the circuit board.

Please refer to FIG. 1 and FIG. 4 , the wire-bonded BGA package 10 and the flip-chip-bonded BGA package 40 correspond to different power ring configurations. For the wire-bonded BGA package 10 , it corresponds to the input/output circuit. The power rings 20a, 20b, 20c of 14a, 14b, 14c are arranged inside the power ring 20d corresponding to the core circuit 13, and on the contrary, for the flip-chip bonding ball grid array package 40, corresponding to the input/output circuits 44a, 44b The power rings 50a, 50b, and 50c of , 44c are arranged outside the power ring 50d corresponding to the core circuit 43, so that the power pins of the wire-bonded ball grid array package 10 and the flip-chip bonded ball grid array package 40 correspond to different power pins. Positional configuration (as shown in FIG. 2 and FIG. 5 ), in other words, when chips with the same function use different packaging technologies to correspond to the structure of the wire-bonded BGA package 10 and the flip-chip-bonded BGA package 40 respectively At this time, different circuit boards (with different circuit layouts) must be used to assemble the wire bonded BGA package 10 and the flip-chip bonded BGA package 40 respectively due to the different configurations of the power supply pins. When the packaging technology changes, such as changing from wire bonding BGA package 10 to flip chip bonding BGA package 40, the flip chip bonding BGA package 40 cannot be used due to incompatible pin configurations. On the circuit board originally suitable for the wire bonding BGA package 10, if the circuit board supplier changes the design of the circuit board to assemble the flip-chip bonded BGA package 40, the cost of the circuit board supplier will increase. Specifically, if the circuit board supplier does not change the original circuit board design, because the flip-chip bonded BGA package 40 produced by the package supplier cannot be purchased and used, the production cost of the package supplier will increase.

Contents of the invention

Therefore, the main task of the present invention is to provide a wire-bonded BGA package and a flip-chip-bonded BGA package corresponding to the same power pin configuration, so as to solve the above-mentioned problems.

To this end, the present invention provides a wire-bonded ball grid array package with power pins in flip-chip packaging, which includes: a substrate with a first surface and a second surface, which includes: a first surface A power ring, set on the first surface of a substrate, used to transmit a first operating voltage; a second power ring, set on the first surface of the substrate, used to transmit a second operating voltage; a plurality of The first pins are used to connect the circuit board on which the ball grid array package is assembled, the circuit board inputs the first operating voltage, the plurality of first pins are arranged on the second surface of the substrate, and Electrically connected to the first power ring; and a plurality of second pins, used to connect to the circuit board assembled with the ball grid array package, the second operating voltage is input from the circuit board, and the plurality of second pins are set on the second surface of the substrate and electrically connected to the second power ring; and a chip disposed on the first surface of the substrate, which includes: a core circuit for performing a predetermined operation; and at least one The input/output circuit is electrically connected to the core circuit, and is used to control signal input and output to the core circuit; and wherein, the first power ring and the second power ring are respectively welded to the core circuit and the I/O circuit of the chip; Wherein the first power ring is set between the second power ring and the chip; wherein the first pin corresponding to the first power ring is set inside the second pin corresponding to the second power ring.

The present invention also provides a wire-bonded ball grid array package with flip-chip power supply pins, which includes: a substrate having a first surface and a second surface, which includes: a first power supply ring, arranged on the first surface of a substrate, for transmitting a first operating voltage; a second power supply ring, arranged on the first surface of the substrate, for transmitting a second operating voltage; a plurality of first The pins are used to connect the circuit board on which the ball grid array package is assembled, and the circuit board inputs the first operating voltage. The plurality of first pins are arranged on the second surface of the substrate and are electrically connected to the first A power ring; a plurality of second pins, used to connect to the circuit board on which the ball grid array package is assembled, and the second operating voltage is input from the circuit board, and the plurality of second pins are arranged on the second side of the substrate. On the surface, and electrically connected to the second power supply ring; and a chip, which includes: a core circuit, used to perform a predetermined operation; at least one input/output circuit, electrically connected to the core circuit, used to control signal input and outputting the core circuit; and wherein, the first power ring and the second power ring are respectively welded to the core circuit and the I/O circuit of the chip; wherein the second power ring is arranged inside the first power ring; wherein The second pin corresponding to the second power ring is disposed inside the first pin corresponding to the first power ring.

The invention provides a ball grid array (ball grid array, BGA) package (package), which includes a substrate (substrate) and a chip (die). The substrate includes a first power ring (first power ring), which is arranged on the first wiring layer of the substrate, and is used to transmit a first operating voltage; a second power ring (second power ring), which is arranged on the first On the wiring layer, it is used to transmit a second working voltage; a plurality of first pins (first ballout), is used to connect the circuit board assembled with the ball grid array package to input the first working voltage from the circuit board, the A plurality of first pins are disposed on the first conductive block of the second wiring layer of the substrate, and the first conductive block is electrically connected to the first power ring through at least one first via (first via); and a plurality of A second pin (second ballout) is used to connect the circuit board assembled with the ball grid array package to input the second operating voltage from the circuit board, and the plurality of second pins are arranged on the first wiring layer of the second wiring layer. On the two conductive blocks, the second conductive block is electrically connected to the second power ring through at least one second via. The chip is disposed on the first wiring layer of the substrate, and includes a core circuit (core circuit) for performing a predetermined operation; at least one input/output circuit (I/O circuit), electrically connected to the A core circuit, used to control signal input and output from the core circuit; and a plurality of bonding pads (bonding pads), arranged on the surface of the chip, respectively connected to the first and second power supplies via a plurality of bonding wires (bonding wires) The loop is used to respectively transmit the first working voltage to the core circuit and transmit the second working voltage to the input/output circuit. In addition, the first power ring is arranged between the second power ring and the chip.

The present invention further provides a ball grid array (BGA) package, which includes a substrate and a die. The substrate includes a first power ring arranged on a first wiring layer for transmitting a first operating voltage; a second power ring arranged on the first wiring layer , used to transmit a second operating voltage; a plurality of contacts are arranged on the first wiring layer, and are respectively electrically connected to the first wiring layer through a third wiring layer between the first wiring layer and the second wiring layer. One and the second power supply ring; a plurality of first pins (first ballout), used to connect the circuit board on which the ball grid array package is assembled, so as to input the first operating voltage from the circuit board, and the plurality of first ballouts The feet are arranged on the first conductive block of a second wiring layer, and the first conductive block is electrically connected to the first power supply ring through at least one first via (first via); and a plurality of second pins ( second ballout), used to connect the circuit board on which the ball grid array package is assembled, so as to input the second operating voltage from the circuit board, and the plurality of second pins are arranged on the second conductive block of the second wiring layer Above, the second conductive block is electrically connected to the second power ring through at least one second via (second via). The chip includes a core circuit (core circuit), which is used to perform a predetermined operation; at least one input/output circuit (I/O circuit), which is electrically connected to the core circuit, is used to control signal input and output to the core circuit and a plurality of bonding pads (bonding pads), arranged on the surface of the chip, the plurality of bonding pads are respectively connected to the plurality of contacts for transmitting the first operating voltage to the core circuit and transmitting the second operating voltage to the input/output circuit. In addition, the second power ring is arranged inside the first power ring.

Description of drawings

FIG. 1 is a first schematic diagram of a conventional wire bonded BGA package.

FIG. 2 is a second schematic diagram of the wire bonding BGA package shown in FIG. 1 .

FIG. 3 is a cross-sectional view of the wire bonded BGA package shown in FIG. 1 along line 3 - 3 ′.

FIG. 4 is a first schematic view of a conventional flip-chip bonded BGA package.

FIG. 5 is a second schematic diagram of the flip-chip bonded BGA package shown in FIG. 4 .

FIG. 6 is a cross-sectional view of the flip-chip bonded BGA package shown in FIG. 4 along line 6 - 6 ′.

FIG. 7 is a first schematic view of the wire bonded BGA package of the present invention.

FIG. 8 is a second schematic diagram of the wire bonding BGA package shown in FIG. 7 .

FIG. 9 is a cross-sectional view of the wire bonded BGA package shown in FIG. 7 along line 9 - 9 ′.

FIG. 10 is a first schematic view of the flip-chip bonded BGA package of the present invention.

FIG. 11 is a second schematic diagram of the flip-chip bonded BGA package shown in FIG. 10 .

FIG. 12 is a cross-sectional view of the flip-chip bonded BGA package shown in FIG. 10 along line 12 - 12 ′.

Explanation of reference signs

10 and 80 are wire bonding ball grid array packages;

12, 42, 82, 112 are substrates;

14a, 14b, 14c, 44a, 44b, 44c, 84a, 84b, 84c, 114a, 114b, 114c are input/output circuits;

18, 48, 68, 88, 128 are welding pads;

22 and 92 are welding points;

26a, 26b, 26c, 26d, 56a, 56b, 56c, 56d, 96a, 96b, 96c, 96d, 126a, 126b, 126c, 126d are conductive blocks;

30, 60, 100, 130 are the second wiring layer;

34, 64, 104, 134 are solder balls;

66 and 136 are metal bumps;

11, 41, 81, 11 are chips;

13, 43, 83, 113 are core circuits;

16a, 16b, 16c, 16d, 86a, 86b, 86c, 86d are welding lines;

20a, 20b, 20c, 20d, 50a, 50b, 50c, 50d, 90a, 90b, 90c, 90d, 120a, 120b, 120c, 120d are power rings;

24, 54, 94, 124 are pins;

28, 58, 98, 128 are the first wiring layer;

32, 62, 102, 132 are through holes;

40, 110 are flip-chip bonded ball grid array packages; and

70 and 140 are the third wiring layer.

Detailed ways

Please refer to FIG. 7 . FIG. 7 is a first schematic diagram of a wire bonding BGA package 80 of the present invention. The package 80 includes a chip 81 and a substrate 82. The chip 81 includes a core circuit 83 for performing a predetermined operation, a plurality of input/output circuits 84a, 84b, 84c for controlling signal input and output of the core circuit 83, and multiple A bonding pad 88 is used to electrically connect the chip 81 and the substrate 82 . The first wiring layer 98 of the substrate 82 is provided with a plurality of power supply rings 90a, 90b, 90c, 90d to provide the working voltage required for the operation of the chip 81 and a plurality of welding points 92 to transmit signals. In addition, the chip 81 and the substrate 82 are electrically connected to each other via a plurality of welding wires 86a, 86b, 86c, 86d, wherein the welding wires 86a, 86b, 86c are respectively connected to the power supply rings 90a, 90b, 90c, 90d to transmit different voltages to the chip 81, and Bonding wires 86e are connected between bonding points 92 and corresponding bonding pads 88 to transmit signals. For example, if the package body 80 is a north bridge chip of a computer system, the chip 81 is used to control the signal transmission between high-speed peripheral devices (such as memory and display card) and a microprocessor (such as a central processing unit (CPU)) , that is, the core circuit 83 of the chip 81 is used to perform the above functions. On the other hand, the input/output circuits 84a, 84b, and 84c are respectively used to control a memory, a display card, and signal transmission between the CPU and the core circuit 83 . As mentioned above, the input/output circuit 84a corresponds to the memory, the input/output circuit 84b corresponds to the display card, the input/output circuit 84c corresponds to the microprocessor, and the core circuit 13 needs different operating voltages to work normally. Therefore, the power rings 90 a , 90 b , 90 c , and 90 d need to provide required operating voltages to the input/output circuits 84 a , 84 b , 84 c and the core circuit 83 respectively. Please note that, without affecting the technical disclosure of the present invention, FIG. 7 does not show all the connections of the welding lines 86 and the welding points 92 for the sake of illustration. The pads 88 correspond to the input/output circuits 84a, 84b, 84c and the core circuit 83, and can be used to transmit signals and voltages. In FIG. 7, welding wires 86a, 86b, 86c, 86d are respectively used to connect pads 88 and power rings 90a, 90b, 90c, 90d to input voltages to input/output circuits 84a, 84b, 84c and core circuit 83 respectively. . In addition, the bonding wire 86e connects the bonding pad 88 and the bonding point 92 for transmitting signals. Therefore, with the assistance of the bonding wires 86a, 86b, 86c, 86d, 86e, the chip 81 can obtain the required operating voltage from the substrate 82, and the chip 81 and the substrate 82 can transmit signals to each other.

Please refer to FIG. 8 and FIG. 9, FIG. 8 is a second schematic view of the wire bonding BGA package body 80 shown in FIG. 7, and FIG. 9 is a wire bonding BGA package body 80 shown in FIG. 9' section view. The BGA package 80 includes a plurality of pins 94 arranged in a matrix on a second wiring layer 100, wherein the second wiring layer 100 includes a plurality of conductive blocks 96a, 96b, 96c, 96d, The pins 94 on the conductive blocks 96 a , 96 b , 96 c , and 96 d are respectively used to connect a circuit board to input proper working voltages of the input/output circuits 84 a , 84 b , 84 c and the core circuit 83 . As shown in FIG. 9 , the first wiring layer 98 and the second wiring layer 100 are respectively disposed on the upper and lower layers of the wire bonding ball grid array package 80 . Please note that FIG. 7 and FIG. 8 are top views, so the conductive blocks 96a, 96b, 96c, 96d and the corresponding power rings 90a, 90b, 90c, 90d are connected to each other through vias (via) 102, so When the BGA package 80 is mounted on a circuit board via metal conductive balls on the bottom thereof, such as solder balls 104 , the pins 94 corresponding to the solder balls 104 are electrically connected to the circuit board. Therefore, when a voltage is input from the circuit board to the BGA package body 80, the input voltage passes through solder balls 104, pins 94, through holes 102, power rings 90a, 90b, 90c, 90d, and welding wires 86a, 86b. , 86c, 86d, and pad 88 to drive the input/output circuits 84a, 84b, 84c and the core circuit 83, respectively. Similarly, when a signal is input from the circuit board to the input/output circuits 84a, 84b, 84c, the signal passes through the solder ball 104, the pin 94, the through hole 102, the solder joint 92, the solder wire 86e, and the pad 88 to the input/output circuits 84a, 84b, 84c. When a signal is output by the input/output circuit 84a, 84b, 84c, the signal is transmitted to the circuit via the pad 88, the bonding wire 86e, the bonding point 92, the via 102, the pin 94, and the solder ball 104. plate.

It can be clearly seen from FIGS. 7 and 8 that in this embodiment, the power supply ring 90d is on the first wiring layer, and is arranged between the power supply rings 90a, 90b, 90c and the chip 81, so the corresponding power supply ring 90d The pins are disposed on the inside of the corresponding power pins of the power rings 90a, 90b, 90c and thus correspond to the pins of the power ring 90d with respect to the circuit board used to assemble the wire bonded ball grid array package 80. The solder joints are also arranged on the inside of the pins corresponding to the power supply rings 90a, 90b, 90c so as to be bonded smoothly. When the chip 81 changes its packaging method, for example, it is packaged in a flip-chip manner, as shown in FIGS. 4 and 5 , now The configuration of the power ring and the corresponding pin configuration of the flip-chip bonding BGA package 40 are the same as those of the wire-bonding BGA package 80 of the present invention, so when the chip 81 is packaged in a flip-chip manner, it is used to provide The relevant pins of the working voltage of the chip 81 can also be applied to the circuit board originally used to assemble the wire-bonded ball grid array package 80. Therefore, for manufacturers supplying the package 80, the competitiveness of their products can be improved, and the circuit board can be provided. Manufacturers do not have to significantly change the circuit layout of the board.

Please refer to FIG. 10, FIG. 11 and FIG. 12. FIG. 10 is a first schematic diagram of a flip-chip bonding BGA package 110 of the present invention, and FIG. 11 is a second schematic diagram of a flip-chip bonding BGA package 110 shown in FIG. 12 is a cross-sectional view of the flip-chip bonded BGA package 110 shown in FIG. 10 along the line 12 - 12 ′. Flip-chip bonding ball grid array package 110 includes a chip 111 and a substrate 112. The chip 111 includes a core circuit 113 and a plurality of input/output circuits 114a, 114b, 114c. The substrate 112 is provided with a plurality of power rings. ) 120a, 120b, 120c, 120d are respectively used to provide different operating voltages, and the power rings 120a, 120b, 120c, 120d are arranged on the same first wiring layer 128. The operations of the core circuit 113, the input/output circuits 114a, 114b, 144c, and the power rings 120a, 120b, 120c, 120d are the same as those of the same-named components of the wire bonding BGA package 80 of the present invention, so the description will not be repeated. It can be seen from FIG. 11 that the package 110 includes a plurality of pins 124, which are arranged in a matrix on a second wiring layer 130, wherein the second wiring layer includes a plurality of conductive blocks 126a, 126b, 126c, 126d, the pins 124 on the conductive blocks 126a, 126b, 126c, 126d are respectively used to connect a circuit board to input the working voltage of the input/output circuits 114a, 114b, 114c and the core circuit 113 . The main difference between the flip-chip bonding BGA package 110 and the wire-bonding BGA package 80 is that the chip 111 is the state after the chip 81 is reversed, that is, the bonding pad 48 on the chip 111 (as shown in FIG. 12 ) is located on the lower surface of the chip 111 instead of the solder pad 88 shown in FIG. solder bump) or gold bump (gold bump) to connect with the corresponding pad 138 on the first wiring layer 128 of the substrate 112 . In addition, the power rings 120a, 120b, 120c, 120d and the pads 188 (that is, the first wiring layer 58) are all connected to a third wiring layer 140 through a via 132, and through the wiring on the third wiring layer 140 (trace), so that the power ring 120a, 120b, 120c, 120d can output the operating voltage to the core circuit 113 and the input/output circuit 114a, 114b, 114c through the appropriate pad 138. Similarly, the third wiring layer 140 and the second wiring layer Layers 130 are also electrically connected to each other via vias 132. Therefore, pins 124 can be used to transmit signals and power to chip 111. Like wire bonded BGA package 80, flip-chip bonded BGA package 110 also uses tin lead balls 134. Such as metal conductive balls to connect the circuit board.

It can be seen from Figs. 10 and 11 that in this embodiment, the power rings 120a, 120b, 120c are arranged on the first wiring layer 128 between the power ring 120d and the bonding pad 138 of the corresponding chip 111, thus corresponding to the power ring 90d The power pins of the power rings 90a, 90b, 90c are arranged outside the corresponding power pins of the power rings 90a, 90b, 90c, so for the circuit board used to assemble the flip-chip bonding ball grid array package 110, it corresponds to the power ring 90d. The solder joints of the power supply pins are also arranged on the outside of the pins corresponding to the power supply rings 90a, 90b, 90c so that the two can be bonded smoothly. When the chip 111 changes its original packaging method, for example, it is packaged by wire, as shown in Figure 1 , 2, the power ring configuration and the corresponding pin configuration of the existing wire bonding ball grid array package 10 are the same as the flip chip bonding ball grid array package 110 of the present invention, so when the chip 111 is packaged by wire Finally, the relevant pins used to provide the operating voltage of the chip 111 can be applied to the contacts on the circuit board originally used to assemble the wire-bonded ball grid array package 80, so that the manufacturers supplying the package 110 can enhance their product competition. power, and the manufacturer that provides the circuit board does not have to significantly change the circuit layout of the circuit board.

Compared with the prior art, the present invention discloses a wire bonding ball grid array package, wherein the power ring corresponding to the core circuit of a chip on a substrate is arranged inside the power ring corresponding to the input/output circuit of the chip , so when the chip is changed from wire-bonded packaging to flip-chip packaging, the relevant pins used to provide the operating voltage of the chip can be applied to the circuit board originally used to assemble the wire-bonded ball grid array package. Similarly, this The invention also discloses a flip-chip bonding ball grid array package, wherein the power ring corresponding to the core circuit of a chip on a substrate is arranged outside the power ring corresponding to the input/output circuit of the chip, so when the chip is When the flip-chip packaging method is changed to the lead packaging method, the relevant pins used to provide the working voltage of the chip can be applied to the circuit board originally used to assemble the flip-chip bonding ball grid array package. When the manufacturer supplying the above-mentioned package changes the original packaging method of the chip due to its own cost or other factors, the manufacturer providing the circuit board does not need to greatly change the circuit layout on the circuit board. Therefore, for packages using different packaging methods Generally speaking, they all use the same pin configuration and are suitable for corresponding contacts on the same circuit board, so the product competitiveness of the package body can be greatly improved. In addition, for the electronic product corresponding to the circuit board and the package, since the circuit board with the same power pin configuration can be applied to packages produced by different packaging technologies, during the manufacturing process of the electronic product, the overall The production cost will not be greatly increased due to the use of different packaging technologies for the package of one of the components. Therefore, compared with the prior art, the present invention can reduce the overall production cost.

The above descriptions are only preferred embodiments of the present invention, and any adjustments and changes that fall within the scope of the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

1. A wire-bonded ball grid array package with flip-chip power pins, comprising: A substrate having a first surface and a second surface, comprising: A first power ring, arranged on the first surface of a substrate, for transmitting a first working voltage; a second power ring, disposed on the first surface of the substrate, for transmitting a second operating voltage; A plurality of first pins are used to connect the circuit board on which the ball grid array package is assembled, and the first operating voltage is input from the circuit board, and the plurality of first pins are arranged on the second surface of the substrate , and electrically connected to the first power ring; and A plurality of second pins are used to connect the circuit board on which the ball grid array package is assembled, and the second operating voltage is input from the circuit board, and the plurality of second pins are arranged on the second surface of the substrate, and electrically connected to the second power ring; and A chip, disposed on the first surface of the substrate, includes: a core circuit for performing a predetermined operation; and at least one input/output circuit, electrically connected to the core circuit, for controlling signal input and output to the core circuit; and Wherein, the first power ring and the second power ring are respectively welded to the core circuit and the I/O circuit of the chip; wherein the first power ring is arranged between the second power ring and the chip; Wherein the first pin corresponding to the first power ring is disposed inside the second pin corresponding to the second power ring. 2. The ball grid array package as claimed in claim 1, wherein the plurality of first pins and the plurality of second pins are connected to the circuit board through metal conductive balls. 3. The BGA package of claim 1, wherein the chip is a wire bond package or a flip chip package. 4. The BGA package of claim 1, further comprising a plurality of bonding pads on the surface of the chip. 5. A wire-bonded ball grid array package with power pins in flip-chip packaging, comprising: A substrate having a first surface and a second surface, comprising: A first power ring, arranged on the first surface of a substrate, for transmitting a first working voltage; a second power ring, disposed on the first surface of the substrate, for transmitting a second operating voltage; A plurality of first pins are used to connect the circuit board on which the ball grid array package is assembled, and the first operating voltage is input from the circuit board, the plurality of first pins are arranged on the second surface of the substrate, and electrically connected to the first power ring; A plurality of second pins are used to connect the circuit board on which the ball grid array package is assembled, and the second operating voltage is input from the circuit board, the plurality of second pins are arranged on the second surface of the substrate, and electrically connected to the second power ring; and A chip, which includes: a core circuit for performing a predetermined operation; at least one input/output circuit, electrically connected to the core circuit, for controlling signal input and output to the core circuit; and Wherein, the first power ring and the second power ring are respectively welded to the core circuit and the I/O circuit of the chip; wherein the second power ring is arranged inside the first power ring; Wherein the second pin corresponding to the second power ring is disposed inside the first pin corresponding to the first power ring. 6. The ball grid array package as claimed in claim 5, wherein the first pin and the second pin are connected to the circuit board through metal conductive balls. 7. The ball grid array package as claimed in claim 5, wherein the chip further comprises a plurality of metal bumps respectively formed on the plurality of bonding pads for connecting the plurality of bonding pads and the plurality of contacts . 8. The BGA package of claim 5, wherein the chip is a wire bond package or a flip chip package. 9. The ball grid array package as claimed in claim 5 , further comprising a plurality of contacts disposed on the first wiring layer, the contacts passing through a third wiring layer between the first and second wiring layers electrically connected to the first and second power rings. 10. The BGA package of claim 5, further comprising a plurality of bonding pads on the surface of the chip.

Images