CN1221022C - Floating gate manufacturing method and structure of a fast memory - Google Patents

Abstract

The present invention relates to a manufacturing method and a structure of a floating gate with a high capacitance coupling rate and automatic alignment diffusion of a rapid storage. The manufacturing method comprises: firstly, a substrate is provided, the substrate has a first channel so as to form a first insulator in the first channel, the first insulator is projected out of the surface of the substrate, and a second channel is formed in the substrate; secondly, a second insulation layer is formed on the surface of the substrate, and a first conductor layer is conformably formed on the surface of the first insulator and the surface of the second insulation layer; thirdly, a side wall spacer is formed on the first conductor layer at both sides of the second channel, and a second conductor layer is formed on the surface of the side wall spacer and the surface of the first conductor layer; finally, a part of the second conductor layer and a part of the first conductor layer are simultaneously removed so as to form a plug conductor layer between the side wall spacer and form a pad conductor layer on the surface of the second channel.

Description

Floating gate manufacturing method and structure of a fast memory

technical field

The invention relates to a manufacturing method and structure of a floating gate of a fast memory, in particular to a manufacturing method and a structure of a floating gate capable of increasing coupling efficiency.

Background technique

In fast memory, coupling efficiency is one of the important factors affecting the performance of fast memory. During operation of a flash memory, this coupling factor strongly affects the voltage of the floating gate obtained from the control gate. The greater the coupling efficiency, the greater the floating gate voltage, and thus the better performance of the fast memory. Typically coupling efficiency is defined as the amount of floating gate voltage coupled from the control gate voltage. Taking a capacitor as an example, the coupling efficiency can be defined as the ratio of the capacitance between the floating gate and the control gate to the capacitance of the memory cell. It can be seen from this that a larger overlapping area is required between the floating gate and the control gate in order to obtain a higher coupling efficiency.

Referring to FIG. 1, there is shown a cross-sectional view for describing the structure of a floating gate of a conventional flash memory.

As shown in FIG. 1, reference numeral 20 represents a substrate, reference numeral 25' represents a tunneling insulating layer, reference numeral 29 represents an inner layer insulating layer, and reference numerals 31 and 32 represent floating gates and control gates, respectively. In the above-mentioned traditional fast memory, the overlapping area of the floating gate 31 and the control gate 32 is only the two sides and the upper surface, as shown by the oblique lines in the figure, which cannot provide high coupling efficiency, resulting in the programming and access speed of the fast memory. bad. While reducing the thickness of the inner insulating layer 29 to improve the coupling efficiency, there will be data retention limitations. Increasing the thickness of the floating gate oxide layer to improve the coupling efficiency will reduce the Fowler-Nordhein tunneling (F-Ntunneling) efficiency. In this way, as the size of the memory device shrinks, the surface area of the floating gate will also shrink accordingly, reducing the effective capacitance between the floating gate 31 and the control gate 32 , resulting in a significant drop in coupling efficiency. Low capacitive coupling efficiency means poor programming and access efficiency.

In order to improve the programming and access efficiency of the fast memory, the coupling efficiency can be increased by increasing the capacitance between the control gate 32 and the floating gate 31 . Therefore, it is an important subject in the manufacturing process flow of fast memory.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a method for manufacturing a floating gate of a fast memory that can increase coupling efficiency.

Another object of the present invention is to provide a method for fabricating a flash memory with self-aligned floating gates.

In order to achieve the above object, the method for manufacturing the floating gate of the above-mentioned flash memory of the present invention includes the following steps: first, a substrate is provided, and the substrate has a first trench; a first insulator is formed in the first trench, and the first insulator protrudes from the surface of the substrate, thereby forming a second trench beside the first insulator and on the substrate; secondly, forming a second insulating layer and a first conductor on the surface of the substrate in sequence layer and the sacrificial insulating layer; next, remove part of the sacrificial insulating layer to form a sidewall spacer, the sidewall spacer is located on both sides of the second trench and on the first conductor layer; a second conductor is formed layer to fill the space between the sidewall spacers and on the surface of the first conductor layer; finally, part of the second conductor layer and part of the first conductor layer are simultaneously removed to form a plug conductor layer on the Between the sidewall spacers and the pad conductor layer are on the surface of the second trench.

Wherein, due to the above-mentioned process of combining the pad conductor layer and the plug conductor layer, the floating gate structure in the fast memory device manufacturing method of the present invention is formed without using the lithography manufacturing process flow, so the floating gate of the present invention The formation has the characteristics of self-alignment.

Further, after the formation of the plug conductor layer and the pad conductor layer, the following steps are also included:

removing the sidewall spacer and a portion of the first insulator;

sequentially forming an inner insulating layer and a third conductor layer on the plug conductor layer and the pad conductor layer; and

Etching defines the third conductor layer, the inner insulating layer, the plug conductor layer and the pad conductor layer, so that the third conductor layer is converted into a word line control gate, and the plug conductor layer and the pad conductor layer The layer is converted into a floating gate; the substrate is a silicon substrate; the first insulator, the second insulating layer and the sacrificial insulating layer are all oxide layers; the first conductor layer, the second conductor layer and the third The conductor layer is a polysilicon layer; the plug conductor layer and the pad conductor layer are polysilicon layers; the inner insulating layer is an oxide/nitride/oxide layer;

The present invention also provides a floating gate structure, which includes:

a base;

a plurality of first insulators located in the base and protruding from the base surface;

a second insulating layer located on the surface of the substrate; and

A floating gate portion is located on the second insulating layer and between two adjacent first insulators, wherein the floating gate portion includes:

a pad conductor layer located on the second insulating layer and extending upward along opposite sides of the two adjacent first insulators; and

A plug conductor layer is located on the pad conductor layer and spaced a distance from the upwardly extending portion of the pad conductor layer.

The first insulator and the second insulating layer are oxides; the pad conductor and the plug conductor layer are polysilicon layers.

Compared with the manufacturing method of the floating gate of the traditional fast memory, the floating gate manufacturing method of the fast memory according to the above-mentioned present invention has the following advantages:

Because the extra sidewall area of the floating gate of the present invention overlaps with the control gate, the overlapping area of the traditional floating gate and the control gate is increased by 4 times, thereby increasing the coupling efficiency.

Because the floating gate of the present invention has high coupling efficiency, it can reduce the applied voltage on the control gate to realize the programmable and erasable functions of the fast memory.

Description of drawings

FIG. 1 shows a structural diagram of a conventional floating gate;

Figure 2-1 to Figure 9-1 are top views, Figure 2-2 to Figure 9-2 are XX' cross-sectional views of Figure 2-1 to Figure 9-1, Figure 2-3 to Figure 9-3 are Figure 2- 1 to YY' sectional view of FIG. 9-1 , which show the manufacturing method of the floating gate according to the embodiment of the present invention.

Detailed ways

In order to make the above-mentioned and other purposes, features, and advantages of the present invention more clearly understood, the preferred embodiments are specially cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Example:

Please also refer to FIGS. 9-1, 9-2, and 9-3, which respectively represent the top view, XX' sectional view and YY' sectional view of the structure of the floating gate of the flash memory device of the present invention. The floating gate structure of the present invention includes: a substrate 20, which has a first trench 22 in the substrate 20; a first insulator 21 is located in the first trench 22 and protrudes from the surface of the substrate 20; a second The trench 24 is located in the first insulator 21 on the substrate 20; a second insulating layer 25 is located on the surface of the substrate 20; a pad conductor layer 26' is conformally located on the sidewall and bottom of the second trench 24 , and the pad conductor layer 26 ′ located on the sidewall of the second trench 24 extends upward; and a plug conductor layer 28 ′, located in the second trench 24 , and the The pad conductor layer 26 ′ is connected to and separated from the pad conductor layer 26 ′ on the sidewall of the second trench 24 by a distance.

Please refer to FIG. 2 to FIG. 9 . FIG. 2 to FIG. 9 show a method for manufacturing a floating gate of a flash memory device of the present invention in an embodiment of the present invention. Among them, Figure 2-1 to Figure 9-1 are top views, and Figure 2-2 to Figure 9-2, Figure 2-3 to Figure 9-3 are respectively along XX' and YY in Figure 2-1 to Figure 9-1 'Section diagram.

As shown in Figure 2-1, 2-2 and 2-3, they have shown the initial step of the present invention, as shown in the figure, at first provide substrate 20, it is a semiconductor material (for example has the P of N type well) type silicon substrate). Secondly, the active region 23 is isolated by shallow trench isolation (STI), and a first insulator (for example: an oxide layer) 21 is formed in the first trench 22, and the first insulator 21 The surface of the substrate 20 is protruded, and a second groove 24 is formed on the substrate 20 .

As shown in FIGS. 3-1, 3-2, and 3-3, a second insulating layer 25 is formed on the surface of the substrate 20 with a thickness of approximately 50 angstroms to 105 angstroms. Afterwards, a first conductive layer 26 is conformably formed on the surface of the first insulator 21 and the second insulating layer 25 with a thickness of about 200 angstroms to 400 angstroms. Next, a sacrificial insulating layer 27 with a thickness of approximately 100 angstroms to 500 angstroms is conformally formed on the first conductive layer 26 .

The second insulating layer 25 is used as the material of the subsequent gate oxide layer, so it is usually formed in a high temperature environment such as 900° C. by a thermal oxidation manufacturing process such as dry oxidation. The first conductive layer 26 can be a polycrystalline silicon layer, for example, silane (SiH ₄ ) is used as the main reactant, and is produced by a low-pressure chemical vapor deposition (LPCVD) manufacturing process. The sacrificial insulating layer 27 can be (tetra-ethyl-ortho-silicate, TEOS) as the main reactant, and is produced by a low-pressure chemical vapor deposition (LPCVD) manufacturing process.

As shown in Figures 4-1, 4-2, and 4-3, the sacrificial insulating layer 27 is etched back in an anisotropic etching manner, which controls the etching depth to stop on the first conductive layer 26 to form sidewall spacers Object 27 ′ is on the first conductor layer 26 on the sidewall of the second trench 24 .

As shown in Figures 5-1, 5-2, and 5-3, a second conductor layer 28 with a thickness of about 1000 angstroms to 2000 angstroms is formed on the surface of the first conductor layer 26 and the sidewall spacer 27', and The first conductor layer 26 is connected. The second conductive layer 28 can be a polysilicon layer, for example, silane (SiH ₄ ) is used as the main reactant, and is produced by a low-pressure chemical vapor deposition (LPCVD) manufacturing process.

As shown in Figures 6-1, 6-2, and 6-3, part of the second conductor layer 28 and part of the first conductor are simultaneously removed by etch back or chemical mechanical polishing (CMP). layer 26 to form a plug conductor layer 28 ′ between the sidewall spacers 27 ′, and to form a pad conductor layer 26 ′ on the surface of the second trench 24 .

Wherein, because the above-mentioned process does not use the lithography process, but the pad conductor layer 26' and the plug conductor layer 28' are combined to form the floating gate structure in the fast memory device manufacturing method of the present invention, so the floating gate structure of the present invention The formation of the grid has the feature of self-alignment.

As shown in Figures 7-1, 7-2, and 7-3, the sidewall spacers and part of the first insulator 21 are removed with hydrofluoric acid (HF) or (buffer oxide etchant, BOE) etching solution, so that The plug conductor layer 28' and the pad conductor layer 26' are exposed. Wherein, the pad conductor layer 26 ′ located on the sidewall of the second trench 24 extends upward, and the plug conductor layer 28 ′ is located in the second trench 24 and connected to the pad conductor layer 26 ′ at the bottom of the second trench 24 , And there is a distance from the pad conductor layer 26 ′ on the sidewall of the second trench 24 .

As shown in Figures 8-1, 8-2, and 8-3, the inner insulating layer 29 and the third conductor layer 30 are sequentially and conformally formed on the surface of the plug conductor layer 28' and the pad conductor layer 26'. . The inner insulating layer 29 can also be a silicon oxide/silicon nitride/silicon oxide layer (its thickness is about ~60 angstroms/~60 angstroms/~60 angstroms), and the third conductive layer 30 can be silane (SiH ₄ ) As the main reactant, a polysilicon layer is formed by a low-pressure chemical vapor deposition (LPCVD) manufacturing process.

As shown in Figures 9-1, 9-2, and 9-3, the third conductor layer 30, the inner insulating layer 29, the plug conductor layer 28' and the pad conductor layer 26' are defined by a lithographic etching process, The third conductor layer 30 is transformed into a word line control gate pattern, and the plug conductor layer 28 ′ and pad conductor layer 26 ′ are transformed into a floating gate 31 .

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore The protection scope of the present invention should be defined according to the scope of the claims of the present invention.

Claims (10)

1. A method for manufacturing a floating gate of a fast memory, comprising the following steps: providing a substrate having a first groove therein; forming a first insulator within the first trench, the first insulator protruding from the surface of the substrate, thereby forming a second trench next to the first insulator and on the substrate; sequentially forming a second insulating layer, a first conductor layer and a sacrificial insulating layer on the surface of the base; removing part of the sacrificial insulating layer to form a sidewall spacer, the sidewall spacer is located on both sides of the second trench and on the first conductor layer; forming a second conductor layer to fill the space between the sidewall spacers and on the surface of the first conductor layer; and At the same time, part of the second conductor layer and part of the first conductor layer are removed to form a plug conductor layer between the sidewall spacers, and a pad conductor layer on the surface of the second trench. 2. The method for manufacturing a floating gate of a flash memory according to claim 1, further comprising the following steps after forming the plug conductor layer and the pad conductor layer: removing the sidewall spacer and a portion of the first insulator; sequentially forming an inner insulating layer and a third conductor layer on the plug conductor layer and the pad conductor layer; and Etching defines the third conductor layer, the inner insulating layer, the plug conductor layer and the pad conductor layer, so that the third conductor layer is converted into a word line control gate, and the plug conductor layer and the pad conductor layer layer to a floating gate. 3. The method for manufacturing a floating gate of a flash memory according to claim 1, wherein the substrate is a silicon substrate. 4. The method for manufacturing a floating gate of a flash memory according to claim 1, wherein the formed first insulator, second insulating layer and sacrificial insulating layer are oxide layers. 5. The method for manufacturing a floating gate of a flash memory according to claim 1, wherein the first conductor layer, the second conductor layer and the third conductor layer are polysilicon layers. 6. The method for manufacturing a floating gate of a flash memory according to claim 1, wherein the plug conductor layer and the pad conductor layer are polysilicon layers. 7. The method for manufacturing a floating gate of a flash memory according to claim 1, wherein the inner insulating layer is an oxide/nitride/oxide layer. 8. A floating gate structure of a fast memory, comprising: a base; a plurality of first insulators located in the base and protruding from the base surface; a second insulating layer located on the surface of the substrate; and A floating gate portion is located on the second insulating layer and between two adjacent first insulators, wherein the floating gate portion includes: a pad conductor layer located on the second insulating layer and extending upward along opposite sides of the two adjacent first insulators; and A plug conductor layer is located on the pad conductor layer and spaced a distance from the upwardly extending portion of the pad conductor layer. 9. The floating gate structure of a flash memory according to claim 8, wherein the first insulating material and the second insulating layer are oxides. 10. The floating gate structure of a flash memory according to claim 8, wherein the pad conductor layer and the plug conductor layer are polysilicon layers.

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