CN1218393C - Metal interconnect structure with partial slit and method of manufacturing the same - Google Patents

Abstract

The invention provides a metal interconnect structure with local slits and a method for fabricating the same. The structure comprises: a lower layer metal line; a dielectric layer on the lower metal line and having a dual damascene opening composed of a lower dielectric layer hole and an upper trench; and a metal layer filled in the dual damascene opening to form a metal plug on the lower metal line and an upper metal line on the metal plug. The upper or lower metal line has a local slit, which is filled with dielectric and located near the via hole. By arranging the local slits on the upper layer or the lower layer metal wire and near the dielectric layer hole, the stress of the upper layer metal wire and the lower layer metal wire near the dielectric layer hole can be reduced, and electric leakage is avoided.

Description

Metal interconnect structure with partial slit and method of manufacturing the same

technical field

The present invention relates to a metal interconnection of an integrated circuit and a manufacturing method thereof.

technical background

In integrated circuit technology, in order to improve the integration of components and the speed of information transmission, the process technology has entered the range of quarter-micron or even finer size from sub-micron. However, when the line width is getting smaller and smaller, the aluminum wire can no longer meet the speed requirements. Therefore, it is the current trend to use metal copper with high conductivity as the wire to reduce the RC delay.

However, copper metal cannot be used to define patterns by dry etching, because the copper chloride (CuCl ₂ ) produced by the reaction of copper metal with chlorine plasma gas has a very high boiling point (about 1500 ° C), so the production of copper wires requires damascene. process to proceed. The dual damascene process refers to forming a trench for a copper wire and a via opening thereunder, and simultaneously filling it with copper metal.

Referring to FIG. 1 to FIG. 3 , there are shown cross-sectional views of traditionally forming a dual damascene interconnection structure. Referring to FIG. 1 , a lower layer metal line 200 , a first dielectric layer 300 , an etch stop layer 310 , and a second dielectric layer 320 are sequentially arranged on a semiconductor substrate 100 .

Then, referring to FIG. 2 , a first photolithography process is performed to selectively etch the second dielectric layer 320 , the etch stop layer 310 , and the first dielectric layer 300 to form a via hole 400 . A second lithography process is then performed to etch the second dielectric layer 320 until the etching stop layer 310 is exposed to form a trench 420 . In this way, a dual damascene opening composed of the via hole 400 and the trench 420 is formed.

Next, referring to FIG. 3, the metal is filled into the via hole 400 and the trench 420, and then chemical mechanical polishing (CMP; chemical mechanical polishing) is performed to form the upper layer metal line 520, and at the same time, the upper layer and the lower layer metal line 520 are formed. and 220 through the via plug 500 .

Since the upper layer metal line 520 is very wide and long, a large stress is caused, which is not conducive to the CMP. Therefore, in the current copper interconnection process, some slits (Slots) are often arbitrarily opened on the wide and long large copper interconnection to relieve the stress of the entire upper layer copper interconnection, so as to facilitate the CMP. Generally speaking, for copper interconnects with a width ≥ 12 μm, the size of the slit is generally ≥ 3 μm in width and ≥ 3 μm in length.

However, this method of arbitrarily opening slits on a large copper interconnection line cannot solve the stress near the via hole 400 , so there will be a problem of localized stress migration. For a large piece of lower metal line 200 with a large width, due to the stress of the lower metal line 200 near the via hole 400, the lower layer metal line 200 will have a hump-like protrusion at the position of the via hole 400. , as shown at A in Figure 3. Furthermore, for a large piece of upper metal line 520 with a large width, due to the stress of the upper metal line 520 near the via hole 400, the upper layer metal line 520 will be pulled back upwards at the position of the via hole 400. (pullback) phenomenon, as shown in Figure 4 at B. Therefore, there will be a gap between the via plug 500 and the underlying metal line 200 , resulting in electric leakage.

Contents of the invention

In view of this, the object of the present invention is to provide a metal interconnection structure with local slits and a manufacturing method thereof which can relieve the stress of the copper interconnection in order to solve the above problems.

The purpose of the present invention is achieved like this:

A metal interconnection structure with local slits, characterized in that it includes:

lower layer metal wire;

a dielectric layer overlying the lower metal line, having a dual damascene opening formed by a via hole below and a trench above; and

A metal layer is filled in the dual damascene opening to form a metal plug on the lower metal line and an upper metal line on the metal plug,

Wherein the upper layer or the lower layer metal line has a partial slit, the partial slit is filled with dielectric and is located near the via hole.

The partial slit is square, rectangular, L-shaped, U-shaped or bow-shaped.

The size range of the partial slit is: the length is 0.1 μm to 5 μm, and the width is 0.1 μm to 5 μm.

The width of the upper metal line ranges from 0.5 μm to 10 μm.

The width of the lower metal line ranges from 0.5 μm to 10 μm.

The material of the upper metal wire is Cu, Al, W, Au, Ag, or alloys thereof.

A method of manufacturing a metal interconnection with partial slits, comprising the following steps:

Form the lower metal line;

forming a dielectric layer on the underlying metal line;

forming a dual damascene opening comprising vias and trenches in the dielectric layer; and

filling metal into the dual damascene opening to form a metal plug in the via hole and an upper layer metal line in the trench,

Wherein the upper layer or the lower layer metal line has a local slit, and the local slit is filled with dielectric and is located near the via hole.

The lower metal line has the local slit, and the method for forming the lower metal line and the dielectric layer includes:

forming an underlying metal line having a slit adjacent to a via to be formed next; and

A dielectric layer is formed on the lower metal line, and the dielectric is filled into the slit of the lower metal line.

The upper metal line has the local slit, and the method of forming a dual damascene opening and filling metal includes:

Forming a dual damascene opening consisting of a via hole and a trench in the dielectric layer, and forming a slit by leaving a portion of the dielectric layer near the via hole while forming the trench; and

Metal is filled into the dual damascene opening, a metal plug is formed in the via hole, and an upper layer metal line with a slit is formed in the trench.

Both the upper and lower metal lines have the local slits, and the method includes:

forming a lower layer metal line with a first slit, the first slit is located near a via hole to be formed next;

forming a dielectric layer on the lower metal line, and filling the dielectric into the first slit of the lower metal line;

forming a dual damascene opening formed by a via hole and a trench in the dielectric layer, and forming a second slit while forming the trench while leaving a part of the dielectric layer near the via hole; and

Metal is filled into the dual damascene opening, a metal plug is formed in the via hole, and an upper layer metal line with a second slit is formed in the trench.

By above scheme, positive effect of the present invention is as follows:

In order to achieve the purpose of the present invention, the metal interconnection structure with local slits provided by the present invention includes: a lower layer metal line; a dielectric layer, which is located on the lower layer metal line, and has a dielectric layer from below. A dual damascene opening formed by layer holes and trenches above; and a metal layer filled in the dual damascene opening to become a metal plug on the lower metal line and an upper metal line on the metal plug. There is a local slit on the upper or lower metal line, and the local slit is filled with dielectric and is located near the via hole. The invention also provides a method for relieving the stress of metal interconnection lines by using local slits, which includes the following steps: forming a lower layer metal line, and forming a dielectric layer on the lower layer metal line. Next, a dual damascene opening consisting of via holes and trenches is formed in the dielectric layer. Finally, metal is filled into the dual damascene opening, a metal plug is formed in the via hole, and an upper layer metal line is formed in the trench. There is a local slit on the upper or lower metal line, and the local slit is filled with dielectric and is located near the via hole. The partial slits of the present invention can be provided only on the upper metal wires, or only on the lower layer metal wires, or can be provided on both the upper and lower layer metal wires. According to a specific embodiment of the present invention, when slits are provided on the upper and lower metal lines at the same time, the method includes the following steps: forming a lower layer metal line with a first slit, the first slit is located at the next to be formed Near the interlayer hole. Next, a dielectric layer is formed on the lower metal line, and the dielectric is filled into the first slit of the lower metal line. Next, a dual damascene opening formed by a via hole and a trench is formed in the dielectric layer, and while the trench is formed, a part of the dielectric layer is reserved near the via hole to form a second slit. Finally, metal is filled into the dual damascene opening, a metal plug is formed in the via hole, and an upper layer metal line with the second slit is formed in the trench. To sum up, the present invention can reduce the stress of the upper and lower metal lines near the via holes and avoid electric leakage by providing local slits near the upper or lower layer metal lines and the via holes.

Description of drawings

1 to 4 are schematic cross-sectional schematic diagrams of the traditional process of forming a dual damascene metal interconnection structure;

5 to 9 are schematic cross-sectional views of the process of forming a dual damascene metal interconnection structure with partial slits according to a preferred embodiment of the present invention;

10 to 13 are shapes of partial slits on metal wires according to a preferred embodiment of the present invention.

Label description:

100 semiconductor substrate

200 lower metal wires

300 first dielectric layer 310 etch stop layer

320 second dielectric layer

400 Via 420 Groove

500 Via plug 520 Upper metal wire

10 Semiconductor substrate

S1 first slit

S2 second slit

d1 the distance between the first slit S1 and the via hole 40

d2 the distance between the second slit S2 and the via hole 40

20 lower metal wire

30 First Dielectric Layer 31 Etch Stop Layer

32 second dielectric layer

40 via hole 42 groove;

80 photoresist layer

82 The groove part of the photoresist layer 80 80S The raised part of the photoresist

50 metal plugs

52 upper metal wire

Detailed ways

5 to 9 are schematic cross-sectional diagrams illustrating the process of forming a dual damascene metal interconnection structure with partial slits according to a preferred embodiment of the present invention.

Referring to FIG. 5 , a lower layer metal line 20 having a first slit S1 is formed on a semiconductor substrate 10, and the first slit S1 is located near a via hole to be formed next, for example, a distance from the via layer to be formed next The position of the hole is 0 to 1 μm.

Next, a first dielectric layer 30 is formed on the lower metal line 20 , and the dielectric is filled into the first slit S1 of the lower metal line 20 . The first dielectric layer 30 can be silicon oxide or silicon nitride deposited by CVD, or low dielectric constant materials, such as FLARE, PAE-2, SILK and other organic polymer materials, or FSG, HSQ hydrogen sulfide (hydrogen Non-organic materials such as silsesquioxane), or black diamonds. Then, an etching stop layer 31 and a second dielectric layer 32 are sequentially formed on the first dielectric layer 30 . This etch stop layer 31 can be silicon nitride (silicon nitride) or silicon oxynitride (siliconoxynitride), the second dielectric layer 32 can be silicon oxide or silicon nitride, or low dielectric constant material (such as FLARE, PAE-2 , SILK, FSG, HSQ, black diamond, etc.).

Next, referring to FIG. 6, the first lithography process is carried out to selectively etch the second dielectric layer 32, the etch stop layer 31, and the first dielectric layer 30 to form a via hole 40, exposing the underlying metal line 20. The first slit S1 on the lower metal line 20 is near the via hole 40 , for example, the distance d1 between the first slit S1 and the via hole 40 is between 0 and 1 μm. Selective etching can use an anisotropic etching method, for example, etching by reactive ion etching (RIE; reactive ion etching).

Next, referring to FIG. 7 , a photoresist layer 80 is formed on the second dielectric layer 32 , and the photoresist layer 80 has a groove portion 82 for defining a trench of a dual damascene opening. Moreover, there is a photoresist protrusion 80S in the groove portion 82, and the position of the photoresist protrusion 80S is near the via hole 40, for example, the distance d2 between the photoresist protrusion 80S and the via hole 40 It can be between 0 and 1 μm, and is used to define the slits to be formed on the upper metal lines later.

Next, referring to FIG. 8 , using the photoresist layer 80 as a mask, a second lithography process is performed to etch the second dielectric layer 32 by RIE until the surface of the etch stop layer 31 is exposed. In this way, a trench 42 is formed in the second dielectric layer 32 , and the via hole 40 in the first dielectric layer 30 and the trench 42 in the second dielectric layer 32 together form a dual damascene opening. It should be noted that since the photoresist protrusion 80S exists in the groove portion 82 of the photoresist layer 80, the dielectric protrusion S2, also called the second dielectric protrusion S2, is defined in the groove 42 of the second dielectric layer 32. Two slits S2 are located near the via hole 40 , that is, the distance d2 between the second slit S2 and the via hole 40 may be between 0 and 1 μm.

Next, referring to FIG. 9 , metal is filled into the dual damascene opening, a metal plug 50 is formed in the via hole 40 , and an upper layer metal line 52 having the first slit S2 is formed in the trench 42 . The upper metal wire 52 can be Cu, Al, W, Au, Ag, or alloys thereof.

The above-mentioned specific embodiment is an example where both the upper and lower layer metal lines have slits near the via hole (distance from 0 to 1 μm), but the scope of the present invention is not limited thereto. It is also possible that only the lower metal lines have slits near the via holes, but the upper metal lines do not. Alternatively, only the upper metal lines have slits near the via holes, but the lower metal lines do not. The stress of the upper and lower metal lines near the via hole can be relieved by the method of setting local slits on the upper and/or lower layer metal lines near the via hole. Therefore, between the via plug 50 and the underlying metal line 20, there is no hump-like protrusion or pull back in the prior art, as shown at C in FIG. 9 , thus avoiding leakage.

The shape of the local slits of the upper layer and/or the lower layer metal lines near the via holes is not limited. Taking the slit S2 in the upper metal line 52 in FIG. 9 as an example, its shape can be square, rectangular, L-shaped, U-shaped, or bow-shaped. 10 to 13 are top views showing various possible shapes of the slit S2, and FIG. 9 is a cross-sectional view along line 2e-2e.

The size range of the partial slit of the present invention may be: the length is 0.1 μm to 5 μm, and the width is 0.1 μm to 5 μm. The width of the upper metal line may be 0.5 μm to 10 μm, and the width of the lower metal line may be 0.5 μm to 10 μm.

To sum up the above, the present invention can reduce the stress of the metal wire near the via hole and avoid electric leakage by having a local dielectric slit near the via hole.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in this art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be based on the scope defined by the claims of the present invention.

Claims (10)

1. A metal interconnection structure with local slits, characterized in that it includes: lower layer metal wire; a dielectric layer overlying the lower metal line, having a dual damascene opening formed by a via hole below and a trench above; and A metal layer is filled in the dual damascene opening to form a metal plug on the lower metal line and an upper metal line on the metal plug, Wherein the upper layer or the lower layer metal line has a partial slit, the partial slit is filled with dielectric and is located near the via hole. 2. The metal interconnection structure with partial slits according to claim 1, wherein the partial slits are square, rectangular, L-shaped, U-shaped, or bow-shaped. 3. The metal interconnection structure with partial slits as claimed in claim 1, wherein the size of the partial slits ranges from 0.1 μm to 5 μm in length and 0.1 μm to 5 μm in width. 4. The metal interconnection structure with partial slits as claimed in claim 1, wherein the width of the upper metal line is in the range of 0.5 μm to 10 μm. 5. The metal interconnection structure with local slits as claimed in claim 1, wherein the width of the underlying metal line is in the range of 0.5 μm to 10 μm. 6. The metal interconnection structure with local slits as claimed in claim 1, wherein the material of the upper metal wire is Cu, Al, W, Au, Ag, or an alloy thereof. 7. A method of manufacturing a metal interconnection with partial slits as claimed in claim 1, comprising the following steps: Form the lower metal line; forming a dielectric layer on the underlying metal line; forming a dual damascene opening comprising vias and trenches in the dielectric layer; and filling metal into the dual damascene opening to form a metal plug in the via hole and an upper layer metal line in the trench, Wherein the upper layer or the lower layer metal line has a local slit, and the local slit is filled with dielectric and is located near the via hole. 8. The method according to claim 7, wherein the lower metal line has the local slit, and the method of forming the lower metal line and the dielectric layer comprises: forming an underlying metal line having a slit adjacent to a via to be formed next; and A dielectric layer is formed on the lower metal line, and the dielectric is filled into the slit of the lower metal line. 9. The method according to claim 7, wherein the upper metal line has the partial slit, and the method of forming a dual damascene opening and filling metal comprises: A dual damascene opening consisting of a via hole and a trench is formed in the dielectric layer, and at the same time as the trench is formed, a part of the dielectric layer is left near the via hole to form a slit: and Metal is filled into the dual damascene opening, a metal plug is formed in the via hole, and an upper layer metal line with a slit is formed in the trench. 10. The method according to claim 7, wherein both the upper and lower metal lines have the partial slits, the method comprising: forming a lower layer metal line with a first slit, the first slit is located near a via hole to be formed next; forming a dielectric layer on the lower metal line, and filling the dielectric into the first slit of the lower metal line; A dual damascene opening consisting of a via hole and a trench is formed in the dielectric layer, and while the trench is formed, a part of the dielectric layer is reserved near the via hole to form a second slit; and the metal filling into the dual damascene opening, a metal plug is formed in the via hole, and an upper layer metal line with a second slit is formed in the trench.

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