CN120300106A

CN120300106A - A semiconductor device

Info

Publication number: CN120300106A
Application number: CN202510279416.XA
Authority: CN
Inventors: 蔡仙清; 林科闯; 刘胜厚; 卢益锋; 张辉; 孙希国
Original assignee: Xiamen Sanan Integrated Circuit Co Ltd
Current assignee: Xiamen Sanan Integrated Circuit Co Ltd
Priority date: 2021-12-07
Filing date: 2021-12-07
Publication date: 2025-07-11
Also published as: CN114420677A; CN114420677B

Abstract

The invention discloses a semiconductor device, which comprises a protective structure, wherein the protective structure comprises an ion implantation region formed on a semiconductor epitaxial layer and an ohmic contact metal layer laminated above the ion implantation region, at least one layer of metal layer is laminated on the ohmic contact metal layer, the ion implantation region surrounds the periphery of the semiconductor device region in a top view, the ion implantation region and the semiconductor device region are separated by a passive region, the metal layer on the top layer is connected with a source electrode of the semiconductor device, the metal layer on the top layer is in a non-closed-loop structure, the metal layer on the top layer is connected with the source electrode of the semiconductor device, an electrostatic diffusion channel is formed, and the source electrode of the semiconductor device is grounded, so that electric charge generated by ESD (electro-static discharge) can be released, and the yield of the device in the process is improved.

Description

Semiconductor device

The application relates to a division application of an application patent with the name of a protection structure of a GaN device and a manufacturing method thereof, wherein the application number of the application is 202111485518.5 which is filed by the applicant 'Xiamen City Sanan integrated circuit Limited company' on the application day 2021, 12 and 07.

Technical Field

The present invention relates to the field of semiconductors, and more particularly, to semiconductor devices.

Background

Since GaN materials exhibit many advantages in the fields of high temperature, photoelectrons, high power, microwave radio frequency, etc., gaN semiconductor technology has been rapidly developed in more than 20 years. Particularly, the development of GaN material epitaxy technology enables GaN-based devices to be developed rapidly. AlGaN/GaN High Electron Mobility Transistors (HEMTs) have wide application prospects in the fields of microwave radio frequency and high power due to high breakdown electric fields and excellent electron transmission characteristics. Although GaN-based HEMT devices have a very high breakdown field, existing electrostatic discharge (ESD) tests on GaN-based HEMT devices have shown that GaN-based HEMT devices are also vulnerable to ESD.

At present, the existing anti-static mode in the manufacturing process of the GaN-based HEMT device is mainly controlled by machine parameters, an ion fan and the like are added, damage of ESD to the device in the manufacturing process can be prevented, the device yield is improved, but the existing anti-static mode has limited electrostatic protection effect on the GaN-based HEMT device. Particularly, the HEMT device is easily broken down due to static electricity accumulation in the electrical test and packaging processes, so that the HEMT device is damaged.

The existing ESD protection ring is generally arranged independently and adopts devices such as a transistor, a diode or a capacitor to form an ESD protection circuit, so that a certain device area can be occupied, the device area is increased, the structure is complex, and the cost is high.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide a semiconductor device with EDS protection.

In order to achieve the above object, the technical scheme of the present invention is as follows:

The semiconductor device comprises a protective structure, wherein the protective structure comprises an ion implantation region formed on a semiconductor epitaxial layer and an ohmic contact metal layer laminated above the ion implantation region, at least one metal layer is laminated on the ohmic contact metal layer, the ion implantation region surrounds the periphery of the semiconductor device region when seen from a top view, the ion implantation region and the semiconductor device region are separated by a passive region, the metal layer on the top layer is connected with a source electrode of the semiconductor device, and the metal layer on the top layer is of a non-closed-loop structure.

Further, preferably, the ion implantation region is in a ring structure, and the metal layer of the top layer is connected with the source electrode pad of the semiconductor device.

Further, preferably, the ion implantation region has a ring structure with a ring width of 20-50 μm.

Drawings

Fig. 1 is a cross-sectional view of a guard structure of a GaN device of an embodiment of the invention;

fig. 2 is a top view of a guard structure of a GaN device according to an embodiment of the invention.

Detailed Description

The invention is further explained below with reference to the drawings and specific embodiments. The drawings of the present invention are merely schematic to facilitate understanding of the present invention, and specific proportions thereof may be adjusted according to design requirements. The definition of the context of the relative elements and the front/back of the figures described herein should be understood by those skilled in the art to refer to the relative positions of the elements and thus all the elements may be reversed to represent the same elements, which are all within the scope of the present disclosure.

Examples

The following describes the protection structure of the GaN device and the manufacturing method thereof in detail by taking the GaN-based HEMT device as an example.

Referring to fig. 1 and 2, the protection structure of the embodiment of the present application includes an ion implantation region 1, and an ohmic contact metal layer 2 and an interconnection structure 3 sequentially stacked above the ion implantation region 1, wherein the interconnection structure under the ion implantation region 1, the ohmic contact metal layer 2 and a metal layer 32 'of an uppermost interconnection structure 3' is a ring structure surrounding the HEMT device 4. The ohmic contact metal layer 2 and the interconnection structure 3 form metal connection to form an electrostatic diffusion channel and are finally connected to the source electrode of the HEMT device 4, so that electrostatic shielding can be realized, and the yield is improved. The ion implantation region 1 is defined at the periphery of the HEMT device 4, and as the ion implantation region 1 is used as an active region and can be conducted to the source electrode for grounding, the breakdown voltage of the device can be effectively improved, and the leakage current of the device can be reduced. An ohmic contact metal layer 2 is arranged on the ion implantation region 1, a plurality of sequentially laminated interconnection structures 3 are arranged on the ohmic contact metal layer 2, the ohmic contact metal layer 2 and the interconnection structures 3 are manufactured above the ion implantation region 1, and metals of the ohmic contact metal layer 2 and the interconnection structures 3 can be interconnected with 2DEG of the HEMT device 4. The ion implantation region 1 is an annular region surrounding the periphery of the HEMT device 4, and the annular region comprises an inner edge and an outer edge, and the width between the inner edge and the outer edge is 20-50 micrometers. An inactive region (i.e., an insulating region) is disposed between the ion implantation region 1 and the GaN device, and the ion implantation region 1 is an active region, so that ESD generated during the process can be conducted into the protection structure to be grounded. The annular structure formed above the ion implantation region 1 not only can realize an anti-ESD effect, but also can protect GaN devices from damage caused by a wafer cutting process, and can prevent chemical damage caused by water vapor or other pollutants.

In a specific embodiment, the ohmic contact metal layer 2 is disposed between an inner edge and an outer edge of the annular region, and two sides of the ohmic contact metal layer 2 are spaced from the inner edge and the outer edge by 1-3 micrometers, preferably 1 micrometer, respectively. A plurality of interconnection structures 3 are sequentially formed above the ohmic contact metal layer 2 in a stacked manner, wherein each interconnection structure 3 is composed of a dielectric layer 31 and a metal layer 32 above the dielectric layer 31, the dielectric layer 31 is provided with a through hole 5, the through hole 5 is arranged above the metal layer of the interconnection structure of the next layer or the upper surface of the ohmic contact metal layer 2, the width range is 10-30 micrometers, and the projection area of the through hole 5 on the ion implantation area 1 is annular, in particular to a closed annular through hole corresponding to the surrounding range of the annular structure. The metal layers 32 are filled in the through holes 5 of the dielectric layers 31 and extend to the dielectric layers 31 at two ends of the through holes 5, the metal layers 32 between two adjacent interconnection structures 3 are sequentially overlapped, and the metal layers 32 filled in the through holes 5 enable the interconnection structures 3 at the upper layer and the lower layer to form electrical connection, so that an electrostatic diffusion channel is formed, and electrostatic shielding is realized. In a preferred embodiment, the ohmic contact metal layer 2 and the metal layer 32 are Ti/Pt/Au/Ti, and the dielectric layer 31 is SiN, siO2 or SiON. The interconnection structure 3 comprises a lowest interconnection structure and an uppermost interconnection structure 3', the ohmic contact metal layer 2 is connected with the lowest interconnection structure and the adjacent two interconnection structures 3 through the metal layer 32, and the metal layer 32' of the uppermost interconnection structure 3' is connected with the source electrode of the HEMT device 4.

In a specific embodiment, the dielectric layer of the lowest interconnection structure covers the ohmic contact metal layer 2, not only covers the upper surface and the side wall of the ohmic contact metal layer 2, but also extends to the ion implantation region 1, and the through hole 5 is arranged on the upper surface of the ohmic contact metal layer 2, and the side edge of the through hole 5 is 2-4 micrometers, preferably 2 micrometers, away from the side edge of the ohmic contact metal layer 2. The metal layer of the lowest interconnection structure is covered above the dielectric layer, is filled in the through hole 5 and extends to the dielectric layers at two sides of the through hole 5, the projection edge of the metal layer of the lowest interconnection structure on the ion implantation region 1 is positioned on the dielectric layer of the lowest interconnection structure and the ohmic contact metal layer 2, and the side edge of the metal layer of the lowest interconnection structure is 1-3 microns, preferably 1 micron away from the side edge of the ohmic contact metal layer 2.

Specifically, at least an uppermost interconnect structure 3 'is located above a lowermost interconnect structure, and in other embodiments, a plurality of adjacent interconnect structures 3 are located between the lowermost interconnect structure and the uppermost interconnect structure 3'. The greater the number of layers of the interconnect structure 3, the better the anti-ESD effect. The two adjacent interconnection structures 3 comprise a first interconnection structure and a second interconnection structure below the first interconnection structure, wherein the projection edge of the metal layer of the first interconnection structure on the ion implantation area 1 is positioned on the metal layer of the second interconnection structure, and the side edge of the metal layer of the first interconnection structure is 1-3 microns away from the side edge of the metal layer of the second interconnection structure. The side of the through hole of the dielectric layer of the first interconnection structure is 2-4 micrometers, preferably 2 micrometers, away from the side of the metal layer of the second interconnection structure. The ohmic contact metal layer 2 and the interconnection structure film layer under the metal layer 32 'of the uppermost interconnection structure 3' are ring-shaped structures arranged in the ring-shaped region. The metal layers 32 of the interconnect structures 3 have closed loop openings therein, and the closed loop openings of the annular structures of the metal layers 32 of adjacent two interconnect structures 3 are not positioned in agreement. Since wet etching is required to strip the photoresist after the evaporation process, the metal layer 32 of the interconnect structure 3 cannot be set to a complete closed loop, otherwise the photoresist cannot be stripped, in order that the etching solution can flow into the annular structure through the closed loop opening during the wet etching to etch the photoresist.

In a specific embodiment, the metal layer 32 'of the uppermost interconnection structure 3' includes a surrounding portion 321 and an external connection portion 322, the surrounding portion 321 is disposed above the dielectric layer 31 'of the uppermost interconnection structure 3', and surrounds two semi-annular structures that are spaced from each other above the ion implantation region 1, the external connection portion 322 is formed by extending from two ends of each semi-annular structure to the source electrode of the HEMT device 4, one end of the external connection portion 322 is connected with the source electrode pad 41 of the HEMT device 4, and the other end of the external connection portion 322 is respectively connected with the ends of the semi-annular structures, so that the metal layer 32 'of the uppermost interconnection structure 3' is finally connected to the source electrode pad 41 of the HEMT device 4. During the electrical test of the HEMT device manufacturing process, the source electrode pad 41 of the HEMT device 4 is grounded, so that all layers in the protective structure have equal potential, and therefore, the electric charge generated by the ESD during the manufacturing process can be grounded, the electric charge generated by the ESD can be released, the HEMT device 4 is protected from being damaged by static electricity, the device yield in the manufacturing process is improved, and the HEMT device yield is improved to 90%. The protection structure in the embodiment of the application can be arranged at the periphery of other GaN devices besides the HEMT device.

Corresponding to the above mentioned protection structure of the GaN device, the embodiment of the invention further provides a method for manufacturing the protection structure of the GaN device, and the following specific description will be given by taking the HEMT device as an example, where the manufacturing method includes the following steps:

1) Providing a wafer structure with a HEMT device, forming an ion implantation region on a GaN epitaxial layer of the wafer structure by adopting an ion implantation process, wherein the implanted ions are N or He, the ion implantation region is an annular region surrounding the HEMT device, a passive region (namely an insulating region) is arranged between the annular region and the HEMT device, the annular region is provided with an inner edge and an outer edge, and the width range between the inner edge and the outer edge is 20-50 microns;

2) Coating photoresist on an ion implantation area, defining an ohmic contact metal layer pattern through development and exposure, depositing metal on the ion implantation area by adopting an evaporation process, wherein the deposited metal is Ti/Pt/Au/Ti, stripping the photoresist by using chemical liquid medicine such as N-methyl pyrrolidone and the like, and leaving the required metal pattern to form the ohmic contact metal layer, wherein the width of the ohmic contact metal layer is 1-3 microns smaller than that of the ion implantation area;

3) Depositing a dielectric layer in a PECVD (plasma enhanced chemical vapor deposition) mode, defining a through hole pattern by using photoresist, etching the dielectric layer by using a dry etching method to form a through hole, and stripping the photoresist, wherein the through hole is arranged above the upper surface of the ohmic contact metal layer or the metal layer of the next layer, and the distance between the side edge of the through hole and the side edge of the ohmic contact metal layer or the metal layer of the next layer is 2-4 microns, preferably 2 microns;

4) Coating photoresist on an ion implantation area, defining a metal layer pattern through development and exposure, adopting an evaporation process to deposit metal, stripping the deposited metal which is Ti/Pt/Au/Ti by using chemical liquid medicines such as N-methyl pyrrolidone and the like, and leaving the required metal pattern to form a metal layer, wherein the metal layer is filled in the through hole and extends to the medium layers on two sides of the through hole, a projection area of the metal layer on the ion implantation area is positioned in a projection area of an ohmic contact metal layer or a metal layer of a next layer on the ion implantation area, and the distance between the side edge of the metal layer and the side edge of the metal layer of the ohmic contact metal layer of the next layer or the metal layer of an interconnection structure is 1-3 microns;

5) And 3-4, manufacturing a plurality of dielectric layers and metal layers, stacking to form a plurality of interconnection structures, connecting two adjacent interconnection structures through the metal layers, forming an annular structure surrounding the HEMT device by the ion implantation region, the ohmic contact metal layer and the interconnection structure below the metal layer of the uppermost interconnection structure, and connecting the metal layer of the uppermost interconnection structure with the source electrode of the HEMT device.

Because the source electrode of the HEMT device is grounded, all layers in the protection structure are kept to have equal potential, and charges generated by ESD are grounded, so that the charges generated by the ESD are released, the protection structure of the HEMT device has an electrostatic protection function, and the yield of the device in the process is improved. The manufacturing method of the protective structure is not only suitable for HEMT devices, but also suitable for other GaN devices.

The protection structure of the embodiment of the application has an ESD protection structure, and the protection structure of the embodiment of the application is compared with the yield of the HEMT device process of the comparison example by taking the arrangement of the sealing ring at the periphery of the HEMT device and not arranging any ESD protection structure as the comparison example, and the results are shown in the following table:

	yield rate
		Examples	90%
Comparative example	60%

As can be seen by comparing with the comparative example, the protective structure of the embodiment of the application can effectively improve the yield of the HEMT device manufacturing process, does not occupy excessive area structurally, and can achieve a very good protective effect.

The above embodiments are only used for further illustrating the GaN device of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention falls within the scope of the technical solution of the present invention.

Claims

1. A semiconductor device, characterized in that: it comprises a protection structure, wherein the protection structure comprises an ion implantation region formed on a semiconductor epitaxial layer, and an ohmic contact metal layer stacked above the ion implantation region;

At least one metal layer is stacked on the ohmic contact metal layer;

From the top view, the ion implantation area surrounds the periphery of the semiconductor device area, the ion implantation area and the device area are separated by a passive area, the top metal layer is connected to the source of the semiconductor device, and the top metal layer is a non-closed loop structure.

2. The semiconductor device according to claim 1, wherein:

The ion implantation area is a ring structure; the metal layer on the top layer is connected to the source pad of the semiconductor device.

3. The semiconductor device according to claim 2, wherein:

The ion implantation area is a ring structure with a ring width of 20-50 microns.

4. The semiconductor device according to claim 1, wherein:

At least one of the metal layers is provided with a closed-loop opening, and the closed-loop opening communicates the inner side and the outer side of the annular structure.

5. The semiconductor device according to claim 1, wherein:

The ions implanted into the ion implantation area are N or He.

6. The semiconductor device according to claim 1, wherein:

The semiconductor device is a HEMT device; the top metal layer is a non-closed-loop annular structure.

7. The semiconductor device according to claim 1, wherein:

The top metal layer is two semi-ring structures spaced apart from each other.

8. The semiconductor device according to claim 7, wherein:

Also included is an external connection portion, which connects the metal layer of the top layer and the source pad of the semiconductor device.

9. The semiconductor device according to claim 2, wherein:

The width of the ohmic contact metal layer is 1-3 microns smaller than that of the ion implantation region.

10. The semiconductor device according to claim 1, wherein:

It also includes a first dielectric layer, which covers part of the ion implantation area and part of the ohmic contact metal layer. The first dielectric layer has a through hole, and the through hole is located above the ohmic contact metal layer.