CN120300003A - A chip packaging structure and preparation method for improving heat dissipation capability and warping - Google Patents
A chip packaging structure and preparation method for improving heat dissipation capability and warping Download PDFInfo
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Abstract
本发明公开一种提高散热能力和改善翘曲的芯片封装结构及制备方法，该方法包括以下步骤：在基板上制备重布线结构，在重布线结构上形成金属导电结构；在重布线结构上连接若干功能芯片；在至少一种功能芯片上设若干散热结构，再对所有功能芯片和散热结构进行封装，形成塑封体；对塑封体进行减薄，露出散热结构；去除基板，在重布线结构上形成导电结构，得到封装体；根据实际需求在封装体上贴装或不贴装载板。本发明将若干裸硅和散热膜堆叠在功能芯片上，能够改善翘曲、提高散热能力，在此基础上进行塑封，可减小塑封料用量；将若干种功能芯片通过覆晶工艺焊接到重布线结构上，可高效实现晶圆重构，能同时解决高密度扇出型重构晶圆的翘曲和散热问题。
The present invention discloses a chip packaging structure and preparation method for improving heat dissipation capability and warpage, the method comprising the following steps: preparing a rewiring structure on a substrate, forming a metal conductive structure on the rewiring structure; connecting a plurality of functional chips on the rewiring structure; providing a plurality of heat dissipation structures on at least one functional chip, and then encapsulating all functional chips and heat dissipation structures to form a plastic package; thinning the plastic package to expose the heat dissipation structure; removing the substrate, forming a conductive structure on the rewiring structure to obtain a package; mounting or not mounting a loading plate on the package according to actual needs. The present invention stacks a plurality of bare silicon and heat dissipation films on a functional chip, which can improve warpage and heat dissipation capability, and performs plastic encapsulation on this basis, which can reduce the amount of plastic encapsulation material; welding a plurality of functional chips to the rewiring structure through a flip chip process, which can efficiently realize wafer reconstruction, and can simultaneously solve the warpage and heat dissipation problems of high-density fan-out reconstructed wafers.
Description
Technical Field
The invention belongs to the technical field of chip packaging, and particularly relates to a chip packaging structure capable of improving heat dissipation capacity and warpage and a preparation method thereof.
Background
In recent years, artificial intelligence has achieved explosive development, and HBM (english full-scale High Bandwidth Memory, chinese full-scale high-bandwidth memory) market demand is increasing. The HBM Stack is laid above the silicon intermediate substrate side by side with CPU/GPU and the like through CoWoS (English full scale Chip on Wafer on Substrate) and other 2.5D packaging technologies, the logic die of the CPU/GPU and the like are connected with the silicon intermediate substrate in a reverse film packaging (FC) mode, communication is realized between the logic chips of the memory and the GPU and the like through RDL (English full scale Redistribution Layer, chinese full scale redistribution layer) technology, and interconnection and protection are formed for the chips through LMC (English full scale Liquid Molding Compound, chinese full scale liquid plastic package). However, the stacked height is far higher than that of the side-by-side CPU/GPU, the usage amount of the plastic package material is increased, and the warpage of the reconstituted wafer is obvious after the plastic package process due to the large difference of the thermal expansion coefficients of the plastic package material and silicon, so that the normal operation of the subsequent process is seriously affected. And a large amount of DRAMs (english full name Dynamic Random Access Memory) are stacked and packaged together with the GPU/CPU to generate a large amount of heat. Therefore, it is desirable to find a package structure and a packaging method that can solve both the warpage and heat dissipation problems of the high-density fan-out package reconstituted wafer.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention aims to provide a chip packaging structure capable of improving heat dissipation capacity and warpage and a preparation method thereof, and the chip packaging structure can simultaneously solve the problems of warpage and heat dissipation of a high-density fan-out type packaging reconstruction wafer.
In order to achieve the above purpose and achieve the above technical effects, the invention adopts the following technical scheme:
A preparation method of a chip packaging structure for improving heat dissipation capacity and warping comprises the following steps:
providing a substrate, preparing a re-wiring structure on the substrate, and forming a metal conductive structure on the re-wiring structure;
Connecting a plurality of different functional chips on the rewiring structure, wherein the number of each functional chip is a plurality of functional chips, and the functional chips are electrically connected with the metal conductive structure;
Arranging a plurality of groups of heat dissipation structures on at least one functional chip, and packaging all functional chips and the heat dissipation structures to form a plastic package body;
thinning the plastic package body to expose the heat dissipation structure;
removing the substrate, and forming a conductive structure on the rewiring structure to obtain a package;
And mounting or not mounting a loading board (PCB board, organic carrier board and the like) on the packaging body according to actual production requirements.
Further, the preparation method comprises the following steps:
step one, setting a temporary bonding layer on a substrate;
Preparing a re-wiring structure on a substrate, and forming a metal conductive structure on a metal bonding pad on the surface of the re-wiring structure;
connecting a plurality of different functional chips on the rewiring structure, wherein the number of each functional chip is a plurality, and the functional chips are electrically connected with the metal conductive structure;
Setting a plurality of groups of heat dissipation structures on at least one functional chip;
packaging all the functional chips and the heat dissipation structure to form a plastic package body;
Step six, thinning the plastic package body to expose the heat dissipation structure on the surface of the functional chip;
Step seven, removing the substrate;
Step eight, forming a conductive structure on one surface of the rewiring structure far away from the functional chip to obtain a package body;
and step nine, determining whether a PCB or an organic carrier is attached to the packaging body according to actual production requirements.
Further, in the second step, a re-wiring structure is prepared on the substrate, and the step of forming a metal conductive structure on the metal pad on the surface of the re-wiring structure includes:
Forming a first metal rewiring layer on the temporary bonding layer through the matching of a magnetron sputtering process, a photoetching process and an electroplating process, covering a first passivation layer on the first metal rewiring layer through a coating or film pressing process, and forming a conducting opening on the first passivation layer through the photoetching process; the metal rewiring layers are sequentially and alternately manufactured into other layers of metal rewiring layers and passivation layers according to the steps, each two adjacent metal rewiring layers are electrically connected, a metal conductive structure is formed on the metal rewiring layer on the uppermost layer, the subsequent electrical connection with a functional chip is facilitated, and the whole preparation of the rewiring structure is further completed;
because the metal circuits of the two metal rewiring layers positioned at the lowest layer and the uppermost layer are metal bonding pads, metal conductive structures are formed on the metal bonding pads at the uppermost layer, and the metal conductive structures are solder balls formed through a ball implantation process or metal bumps formed through an electroplating process.
Further, in the third step, two different functional chips, namely a functional chip I and a functional chip II, are connected on the rewiring structure, the functional chip I is provided with a plurality of functional chips, the functional chips II are provided with a plurality of functional chips and are stacked together from top to bottom sequentially, and the functional chip I and the functional chip II are respectively electrically connected with the metal conductive structure.
Further, in the fourth step, a group of heat dissipation structures are disposed on the functional chip I, and the heat dissipation structures include a heat dissipation film and bare silicon which are sequentially disposed from bottom to top.
Further, in the fourth step, two or more than two groups of heat dissipation structures are arranged on the functional chip I, the heat dissipation structures include heat dissipation films and bare silicon which are sequentially arranged from bottom to top, and the heat dissipation films and the bare silicon on the functional chip I are alternately arranged.
Further, the heat dissipation film comprises an upper adhesive layer, an intermediate layer and a lower adhesive layer which are sequentially arranged from top to bottom, wherein the upper adhesive layer and the lower adhesive layer have adhesiveness, and the intermediate layer is quartz glass, carbon nano tube or graphene.
In step nine, the conductive structure is a solder ball formed by a ball mounting process when the PCB is mounted on the package, and is a plated metal bump formed by a plating process when the carrier is mounted on the package.
The invention also discloses a chip packaging structure prepared by the preparation method of the chip packaging structure for improving the heat radiation capability and the warpage.
Further, the chip packaging structure comprises a rewiring structure, a plurality of different functional chips are connected to the rewiring structure, the number of each functional chip is a plurality of, the functional chips and the metal conducting structure form electric connection, a plurality of groups of heat dissipation structures are arranged on at least one functional chip, the heat dissipation structures comprise heat dissipation films and bare silicon which are sequentially arranged from bottom to top, one side, far away from the functional chips, of the rewiring structure forms a conducting structure, and a loading plate is attached or not attached to the conducting structure.
Compared with the prior art, the invention has the beneficial effects that:
The invention discloses a chip packaging structure capable of improving heat radiation capacity and improving warpage and a preparation method thereof, wherein a plurality of bare silicon and heat radiation films are stacked on a functional chip through DIE ATTACH technology, the heat radiation films and the bare silicon are sequentially stacked, the height of the functional chip can be increased, the warpage can be improved through increasing the silicon proportion, the heat radiation capacity can be improved through the stacked heat radiation films, plastic packaging is carried out on the basis, the consumption of plastic packaging materials can be obviously reduced, the preparation cost is reduced, the degree of warpage is controlled, the problems of increased plastic packaging material consumption, reduced silicon proportion and larger warpage caused by height difference among different functional chips in the prior art are solved, a re-wiring technology is carried out on a substrate, a plurality of functional chips are welded on the re-wiring structure through a flip-chip technology, so that wafer reconstruction can be realized, the whole structure is simple, the preparation technology is simple, the cost is low, the problem of warpage and heat radiation of a high-density packaging reconstruction wafer can be simultaneously solved, and the chip packaging structure is suitable for industrial popularization and use.
Drawings
FIG. 1 is a schematic diagram of a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a third embodiment of the present invention;
Fig. 4 is a schematic structural diagram of a functional chip I according to the present invention;
FIG. 5 is a schematic diagram of the functional chip II of the present invention;
FIG. 6 is a schematic diagram of a fourth step of embodiment 1;
FIG. 7 is a schematic diagram of a fifth step of embodiment 1;
FIG. 8 is a schematic structural diagram of step six of embodiment 1 of the present invention;
FIG. 9 is a schematic diagram of the seventh embodiment of the present invention;
FIG. 10 is a schematic diagram of the structure of step eight of embodiment 1 of the present invention;
FIG. 11 is a schematic structural diagram of step nine of embodiment 1 of the present invention;
FIG. 12 is a schematic diagram of a fourth step of embodiment 2;
FIG. 13 is a schematic diagram of a fifth step of embodiment 2;
Fig. 14 is a schematic structural diagram of step six of embodiment 2 of the present invention;
FIG. 15 is a schematic structural diagram of step seven of embodiment 2 of the present invention;
FIG. 16 is a schematic diagram showing the structure of step eight of embodiment 2 of the present invention;
fig. 17 is a schematic structural diagram of step nine of embodiment 2 of the present invention;
The semiconductor chip comprises 1-glass, a 2-temporary bonding layer, a 3-rewiring structure, a 4-metal conductive structure, a 5-functional chip I, a 501-microbump structure I, a 6-functional chip II, 601-through silicon vias, 602-metal bumps, 603-insulating materials, 7-heat dissipation films, 8-bare silicon, 9-plastic packages, 10-conductive structures and 11-PCBs.
Detailed Description
The present invention is described in detail below so that advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making clear and unambiguous the scope of the present invention.
The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
As shown in fig. 1-11, the invention discloses a method for preparing a chip packaging structure for improving heat dissipation capability and warpage, which comprises the following steps:
As shown in fig. 1, a temporary bonding layer 2 is formed by coating a polymer such as a temporary bonding glue on a substrate, and the polymer such as the temporary bonding glue is cured by heating, laser or the like, and glass 1 is selected as the substrate.
Step two, as shown in fig. 2, preparing a rerouting structure 3 comprising a plurality of metal rerouting layers on the glass 1 obtained in the step one, and forming a metal conductive structure 4 on a metal pad of the rerouting structure 3, wherein the specific steps are as follows:
Forming a first metal rewiring layer on the temporary bonding layer through the matching of a magnetron sputtering process, a photoetching process and an electroplating process, covering a first passivation layer on the first metal rewiring layer through a coating or film pressing process, forming a conducting opening on the first passivation layer through the photoetching process, wherein the conducting opening has the function of connecting a rear PCB (printed circuit board) through a conducting bump prepared through a conducting opening of the lowest layer after the glass 1 is removed later;
Since the metal lines of the two metal redistribution layers at the lowest layer and the uppermost layer are metal pads, the metal conductive structures 4 are formed on the metal pads at the uppermost layer, and the metal conductive structures 4 may be solder balls formed by a ball-implanting process, such as tin balls, or metal bumps formed by an electroplating process.
Step three, as shown in fig. 3-5, a plurality of different functional chips are connected to the redistribution structure 3, and each functional chip is a plurality of functional chips, so that the functional chips are electrically connected with the metal conductive structures 4.
In some embodiments, two different functional chips, i.e. functional chip I5 and functional chip II6, are soldered on the redistribution structure 3 by a flip-chip process, and the first micro bump structure 501 of the functional chip I5 and the metal bump 602 of the functional chip II6 are electrically connected to the metal conductive structure 4, respectively. The functional chips II6 are provided with a plurality of functional chips and are stacked sequentially from top to bottom, adjacent functional chips II6 are connected with each other through silicon through holes 601 and metal bumps 602, insulating materials 603 are arranged on the functional chips II6, the insulating materials 603 can be liquid plastic packaging materials filled through a MUF process, and also can be non-conductive films filled through a hot-pressing non-conductive film (TC NCF) hot-pressing bonding mode, and the functional chips are used for filling gaps among functional chip stacks to form HBM with a stable whole structure. Functional chip I5 may select a CPU/GPU and functional chip II6 may select a memory chip.
And step four, as shown in fig. 6, a group of heat dissipation structures are arranged on at least one functional chip, or at least two groups of heat dissipation structures are periodically arranged, and each group of heat dissipation structures comprises a heat dissipation film 7 and bare silicon 8 which are sequentially arranged from bottom to top. When the heat dissipation structure has at least two groups, the heat dissipation films 7 and the bare silicon 8 on the functional chip need to be alternately arranged, and the heat dissipation film 7 in the heat dissipation structure at the lowest side is adhered on the functional chip;
In some embodiments, a layer of adaptive heat dissipation film 7 is attached to each layer of bare silicon 8, each layer of heat dissipation film 7 is composed of three layers, an upper adhesive layer, a middle layer and a lower adhesive layer are sequentially arranged from top to bottom, the upper adhesive layer and the lower adhesive layer have adhesiveness, the upper adhesive layer is used for being connected with the bare silicon 8, the lower adhesive layer of the heat dissipation film 7 in the lowest heat dissipation structure is used for being connected with a functional chip, the lower adhesive layer of the rest heat dissipation film 7 is used for being connected with the adjacent bare silicon 8, the middle layer is made of materials such as quartz glass, carbon nano tubes and graphene, when the bare silicon 8 with the heat dissipation film 7 which is the same in size as the functional chip I5 after grinding and cutting is adhered to the surface of the functional chip I5 through DA (Die attach), a large amount of heat is generated when the device operates, the heat can be transferred onto the heat dissipation film 7 from the back surface of the functional chip I5, and the heat can be transferred onto the bare silicon 8. The heat dissipation film 7 and the bare silicon 8 are sequentially overlapped, so that the silicon ratio is increased, the use of plastic packaging materials is reduced, the purpose of reducing warping after plastic packaging is achieved, and the height of the bare silicon 8 can be set according to the stacking height of the DRAM stack.
Step five, as shown in fig. 7, packaging the functional chip and the heat dissipation structure to form a plastic package body 9;
In some embodiments, the functional chip I5, the functional chip II6, the heat dissipation film 7 and the bare silicon 8 are packaged by a plastic packaging MUF process to form a plastic package body 9, the plastic package body 9 protects the functional chip I3 and the functional chip II4 and supports the whole reconstruction wafer, and the warpage is controlled by stacking the bare silicon 8 and the heat dissipation film 7.
Step six, as shown in fig. 8, the plastic package body 9 is ground and thinned, so that the bare silicon 8 on the surface of the functional chip is exposed, and the heat dissipation effect is improved.
Step seven, as shown in fig. 9, the glass 1 is removed by adopting the processes of laser bonding, heat release, chemical release or mechanical release, and the like, the temporary bonding layer 2 is cleaned by using the liquid medicine, the passivation layer is coated again, one or more layers of rewiring metal layers are formed on the passivation layer, and an under bump metal pad is manufactured at the top end of the rewiring metal layer.
Step eight, as shown in fig. 10, a conductive structure 10 is formed on the under bump metal pad, and the conductive structure 10 is a solder ball formed by a ball-mounting process or a metal bump formed by an electroplating process, so as to obtain a package.
Step nine, as shown in fig. 11, a carrier board is attached to the bottom of the package according to actual requirements, wherein the carrier board adopts a PCB 11 or an organic carrier board, etc., if the package is directly attached to the PCB 11 in a subsequent process, the conductive structure 10 can select solder balls formed by a ball-implanting process, and if the package is attached to the carrier board in a subsequent process, the conductive structure 10 can select metal bumps formed by electroplating. The heat dissipation film 7 and the bare silicon 8 may be further stacked according to actual circumstances.
The invention also discloses a chip packaging structure for improving heat radiation capability and improving warpage, which is prepared by adopting the preparation method of the chip packaging structure for improving heat radiation capability and improving warpage, wherein the chip packaging structure comprises a rewiring structure 3, a plurality of functional chips are arranged on the rewiring structure 3, each functional chip is a plurality of functional chips, the functional chips are electrically connected with a metal conductive structure 4 of the rewiring structure 3, a group of heat radiation structures or at least two groups of heat radiation structures are arranged on at least one functional chip, each group of heat radiation structures comprises a heat radiation film 7 and bare silicon 8 which are sequentially arranged from bottom to top, the functional chips and the heat radiation structures are molded in a plastic package body 9, bare silicon 8 on the surface of the plastic package body 9 is exposed after grinding and thinning, a conductive structure 10 is formed on one side of the rewiring structure 3, which is far away from the functional chips, a PCB (printed circuit board) or an onboard board is arranged on one side of the rewiring structure 3, if the PCB 11 is pasted, the conductive structure 10 can be formed through a ball implantation process, and if the onboard board is pasted, the conductive structure 10 can be formed through a metal bump.
Example 1
As shown in fig. 1 to 11, a method for manufacturing a chip package structure for improving heat dissipation capability and improving warpage includes the steps of:
Step one, as shown in fig. 1, coating a conventional temporary bonding adhesive on glass 1 to form a temporary bonding layer 2, and curing the conventional temporary bonding adhesive by adopting a laser mode;
step two, as shown in fig. 2, preparing a re-wiring structure 3 comprising a plurality of metal re-wiring layers on the glass 1 obtained in the step one, and forming a metal conductive structure 4 on a metal pad of the re-wiring structure 3, wherein the specific steps are as follows:
The first metal rewiring layer is formed on the temporary bonding layer through the matching of a magnetron sputtering process, a photoetching process and an electroplating process, then a first passivation layer is covered on the first metal rewiring layer through a coating or film pressing process, a conducting opening is formed on the first passivation layer through the photoetching process, and the conventional mature technology is adopted, so that the method is omitted, the other metal rewiring layers and the passivation layer are sequentially and alternately manufactured according to the steps in a circulating manner, the metal rewiring layers are multiple, every two adjacent metal rewiring layers are electrically connected, a metal conductive structure 4 is formed on the metal rewiring layer on the uppermost layer, the subsequent electrical connection with the inverted functional chip (the functional chip I5 and the functional chip II 6) is facilitated, and the whole preparation of the rewiring structure 3 is further completed;
because the metal circuits of the two metal rewiring layers positioned at the lowest layer and the uppermost layer are metal bonding pads, a metal conductive structure 4 is formed on the metal bonding pad at the uppermost layer, and the metal conductive structure 4 is a tin ball formed through a ball implantation process;
Step three, as shown in fig. 3-5, two different functional chips, namely a functional chip I5 and a functional chip II6, are soldered on the re-wiring structure 3 by a flip-chip process, and the micro bump structure one 501 of the functional chip I5 and the metal bump 602 of the functional chip II6 are electrically connected with the metal conductive structure 4 respectively. The functional chips I5 are provided with one functional chip II6, the functional chips II6 are provided with a plurality of functional chips which are sequentially stacked from top to bottom, adjacent functional chips II6 are connected with the metal bumps 602 through the through silicon holes 601, the functional chips II6 are provided with insulating materials 603, and the insulating materials 603 are liquid plastic packaging materials filled through MUF technology and act as gaps between the functional chips II6, so that the HBM with the whole stable structure is formed;
Step four, as shown in fig. 6, a group of heat dissipation structures are arranged on the functional chip I5, each heat dissipation structure comprises a heat dissipation film 7 and bare silicon 8 which are sequentially arranged from bottom to top, each heat dissipation film 7 is composed of three layers, an upper adhesive layer, a middle layer and a lower adhesive layer are sequentially arranged from top to bottom, the upper adhesive layer and the lower adhesive layer have adhesiveness, and the middle layer is quartz glass;
Specifically, a layer of matched heat dissipation film 7 is attached to the bare silicon 8, the upper adhesive layer is used for being connected with the bare silicon 8, the lower adhesive layer of the heat dissipation film 7 is used for being connected with the functional chip I5, the bare silicon 8 which is the same as the functional chip I5 in size and is attached with the heat dissipation film 7 after being ground and cut and is matched with the functional chip I5 is adhered to the surface of the functional chip I5 through DA (Die attach), a large amount of heat is generated during operation of the device, the heat can be transferred to the heat dissipation film 7 from the back through the functional chip I5, and then the heat is transferred to the bare silicon 8. The heat dissipation film 7 and the bare silicon 8 are overlapped, so that the silicon occupation ratio is increased, the use of plastic packaging materials is reduced, the purpose of reducing warping after plastic packaging is achieved, and the height of the bare silicon 8 can be set according to the stacking height of the DRAM stack;
step five, as shown in fig. 7, packaging the functional chip I5, the functional chip II6, the heat dissipation film 7 and the bare silicon 8 by a plastic package MUF process to form a plastic package body 9, wherein the plastic package body 9 protects the functional chip I3 and the functional chip II4 and simultaneously supports the whole reconstruction wafer, and the warpage is controlled by stacking the bare silicon 8 and the heat dissipation film 7;
step six, as shown in fig. 8, the plastic package body 9 is ground and thinned to expose the bare silicon 8 on the surface of the functional chip, which is beneficial to improving the heat dissipation effect;
Step seven, as shown in fig. 9, removing the glass 1 by adopting a laser bonding process, cleaning the temporary bonding layer 2 by using a conventional cleaning liquid medicine, recoating a passivation layer, forming a layer of rewiring metal layer on the passivation layer, and manufacturing an under bump metal pad at the top end of the rewiring metal layer;
Step eight, as shown in fig. 10, forming a conductive structure 10 on the under bump metal pad, wherein the conductive structure 10 is a solder ball formed by a ball-implanting process, so as to obtain a package;
step nine, as shown in fig. 11, the package is directly attached to the PCB 11 in the subsequent process.
The chip packaging structure for improving heat radiation capability and improving warpage is prepared by adopting the preparation method of the chip packaging structure for improving heat radiation capability and improving warpage, the chip packaging structure comprises a rewiring structure 3, two different functional chips, namely a functional chip I5 and a functional chip II6, are arranged on the rewiring structure 3, the functional chip I5 is provided with one functional chip II6, the functional chips II6 are arranged in a plurality of mode and are sequentially stacked from top to bottom, adjacent functional chips II6 are connected through a through silicon hole 601 and a metal bump 602, an insulating material 603 is arranged on the functional chip II6, a micro bump structure one 501 of the functional chip I5 and a metal bump 602 of the functional chip II6 are electrically connected with a metal conductive structure 4 respectively, a group of heat radiation structures are arranged on the functional chip I5, the heat radiation structures comprise a heat radiation film 7 and bare silicon 8 which are sequentially arranged from bottom to top, the heat radiation film 7 is composed of a three-layer structure, an upper bonding layer, an intermediate layer and a lower bonding layer are sequentially arranged from top to bottom, the upper bonding layer and the lower bonding layer are provided with glass, the intermediate layer is bonded with one side, the upper bonding layer is far from the functional chip II6 is bonded with one side, the micro bump structure 501 and one side of the functional chip I5 is far from the functional chip is formed with a conductive ball 10, and the conductive ball 11 is formed by a conductive ball 11 through a conductive ball, and the conductive structure 10 is formed by a conductive ball 11.
Example 2
The difference between the present embodiment and embodiment 1 is that the heat dissipation structure of the present embodiment is provided with two groups.
As shown in fig. 1-5 and 12-17, a method for manufacturing a chip package structure for improving heat dissipation capability and warpage, comprising the steps of:
Step one, as shown in fig. 1, coating a conventional temporary bonding adhesive on glass 1 to form a temporary bonding layer 2, and curing the conventional temporary bonding adhesive by adopting a laser mode;
step two, as shown in fig. 2, preparing a re-wiring structure 3 comprising a plurality of metal re-wiring layers on the glass 1 obtained in the step one, and forming a metal conductive structure 4 on a metal pad of the re-wiring structure 3, wherein the specific steps are as follows:
The first metal rewiring layer is formed on the temporary bonding layer through the matching of a magnetron sputtering process, a photoetching process and an electroplating process, then a first passivation layer is covered on the first metal rewiring layer through a coating or film pressing process, a conducting opening is formed on the first passivation layer through the photoetching process, and the conventional mature technology is adopted, so that the method is omitted, the other metal rewiring layers and the passivation layer are sequentially and alternately manufactured according to the steps in a circulating manner, the metal rewiring layers are multiple, every two adjacent metal rewiring layers are electrically connected, a metal conductive structure 4 is formed on the metal rewiring layer on the uppermost layer, the subsequent electrical connection with the inverted functional chip (the functional chip I5 and the functional chip II 6) is facilitated, and the whole preparation of the rewiring structure 3 is further completed;
because the metal circuits of the two metal rewiring layers positioned at the lowest layer and the uppermost layer are metal bonding pads, a metal conductive structure 4 is formed on the metal bonding pad at the uppermost layer, and the metal conductive structure 4 is a tin ball formed through a ball implantation process;
Step three, as shown in fig. 3-5, two different functional chips, namely a functional chip I5 and a functional chip II6, are soldered on the re-wiring structure 3 by a flip-chip process, and the micro bump structure one 501 of the functional chip I5 and the metal bump 602 of the functional chip II6 are electrically connected with the metal conductive structure 4 respectively. The functional chips I5 are provided with one functional chip II6, the functional chips II6 are provided with a plurality of functional chips which are sequentially stacked from top to bottom, adjacent functional chips II6 are connected with the metal bumps 602 through the through silicon holes 601, the functional chips II6 are provided with insulating materials 603, and the insulating materials 603 are liquid plastic packaging materials filled through MUF technology and act as gaps between the functional chips II6, so that the HBM with the whole stable structure is formed;
As shown in fig. 12, two groups of heat dissipation structures are arranged on the functional chip I5, each group of heat dissipation structures comprises a heat dissipation film 7 and bare silicon 8 which are sequentially arranged from bottom to top, the heat dissipation films 7 and the bare silicon 8 on the functional chip I5 are alternately arranged, each heat dissipation film 7 consists of three layers, an upper adhesive layer, a middle layer and a lower adhesive layer are sequentially arranged from top to bottom, the upper adhesive layer and the lower adhesive layer have adhesiveness, and the middle layer is quartz glass;
Specifically, a layer of matched heat dissipation film 7 is attached to each layer of bare silicon 8, the upper adhesive layer is used for being connected with the bare silicon 8, the ground and cut bare silicon 8 which is the same as the functional chip I5 in size and is provided with the matched heat dissipation film 7 is attached to the surface of the functional chip I5 through DA (Die attach), a large amount of heat is generated during operation of the device, the heat can be transferred to the heat dissipation film 7 from the back through the functional chip I5, and then the heat is transferred to the bare silicon 8. The heat dissipation film 7 and the bare silicon 8 are overlapped, so that the silicon occupation ratio is increased, the use of plastic packaging materials is reduced, the purpose of reducing warping after plastic packaging is achieved, and the height of the bare silicon 8 can be set according to the stacking height of the DRAM stack;
Step five, as shown in fig. 13, packaging the functional chip I5, the functional chip II6, the heat dissipation film 7 and the bare silicon 8 by a plastic package MUF process to form a plastic package body 9, and supporting the whole reconstruction wafer while the plastic package body 9 protects the functional chip I3 and the functional chip II4, and controlling the warpage by stacking the bare silicon 8 and the heat dissipation film 7;
step six, as shown in fig. 14, the plastic package body 9 is ground and thinned to expose the bare silicon 8 on the surface of the functional chip, which is beneficial to improving the heat dissipation effect;
step seven, as shown in fig. 15, removing the glass 1 by adopting a laser bonding process, cleaning the temporary bonding layer 2 by using a conventional cleaning liquid medicine, recoating a passivation layer, forming a layer of rewiring metal layer on the passivation layer, and manufacturing an under bump metal pad at the top end of the rewiring metal layer;
Step eight, as shown in fig. 16, forming a conductive structure 10 on the under bump metal pad, wherein the conductive structure 10 is a solder ball formed by a ball-implanting process, so as to obtain a package;
step nine, as shown in fig. 17, the package is directly attached to the PCB 11 in the subsequent process.
The chip packaging structure for improving heat radiation capability and improving warpage is prepared by adopting the preparation method of the chip packaging structure for improving heat radiation capability and improving warpage, the chip packaging structure comprises a rerouting structure 3, two different functional chips, namely a functional chip I5 and a functional chip II6, are arranged on the rerouting structure 3, one functional chip I5 is arranged, the functional chips II6 are arranged, a plurality of functional chips II6 are sequentially stacked from top to bottom, adjacent functional chips II6 are connected through a through silicon hole 601 and a metal bump 602, an insulating material 603 is arranged on the functional chip II6, a first micro bump structure 501 of the functional chip I5 and a metal bump 602 of the functional chip II6 are respectively electrically connected with the metal conductive structure 4, two groups of heat radiation structures are periodically arranged on the functional chip I5, each group of heat radiation structures comprises a heat radiation film 7 and bare silicon 8 which are sequentially arranged from bottom to top, the heat dissipation film 7 and the bare silicon 8 are respectively provided with two layers, the heat dissipation film 7 and the bare silicon 8 on the functional chip I5 are alternately arranged, the lowest layer is the heat dissipation film 7, the uppermost layer is the bare silicon 8, the heat dissipation film 7 is composed of a three-layer structure, an upper adhesive layer, a middle layer and a lower adhesive layer are sequentially arranged from top to bottom, the upper adhesive layer and the lower adhesive layer have adhesiveness, the middle layer is quartz glass, the lower adhesive layer of the heat dissipation film 7 positioned at the lowest layer is adhered to the functional chip I5, the upper adhesive layer of the heat dissipation film 7 positioned at the lowest layer is adhered to one layer of the bare silicon 8, the other layer of the bare silicon 8 is connected with the upper adhesive layer of the other layer of the heat dissipation film 7, the functional chip I5, the functional chip II6, the heat dissipation film 7 and the bare silicon 8 are in a plastic package body 9, the plastic package body 9 exposes the bare silicon 8 at the uppermost layer after being ground and thinned, one side of the heavy wiring structure 3 far from the functional chip forms a conductive structure 10, the conductive structure 10 is a solder ball formed by a ball-mounting process, and the conductive structure 10 is provided with a PCB 11.
The procedure is as in example 1.
The process related to the invention is in the existing mature process category, and is not described herein in detail, and a person skilled in the art can completely operate the invention by means of conventional process means and obtain the beneficial effects of the invention.
Parts or structures of the present invention, which are not specifically described, may be existing technologies or existing products, and are not described herein.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related arts are included in the scope of the present invention.
Claims (10)
1. The preparation method of the chip packaging structure for improving the heat dissipation capacity and the warping is characterized by comprising the following steps of:
providing a substrate, preparing a re-wiring structure on the substrate, and forming a metal conductive structure on the re-wiring structure;
Connecting a plurality of different functional chips on the rewiring structure, wherein the number of each functional chip is a plurality of functional chips, and the functional chips are electrically connected with the metal conductive structure;
Arranging a plurality of groups of heat dissipation structures on at least one functional chip, and packaging all functional chips and the heat dissipation structures to form a plastic package body;
thinning the plastic package body to expose the heat dissipation structure;
removing the substrate, and forming a conductive structure on the rewiring structure to obtain a package;
and mounting or not mounting the loading plate on the packaging body according to actual production requirements.
2. The method of manufacturing a chip package structure for improving heat dissipation and warpage as set forth in claim 1, comprising the steps of:
step one, setting a temporary bonding layer on a substrate;
Preparing a re-wiring structure on a substrate, and forming a metal conductive structure on a metal bonding pad on the surface of the re-wiring structure;
connecting a plurality of different functional chips on the rewiring structure, wherein the number of each functional chip is a plurality, and the functional chips are electrically connected with the metal conductive structure;
Setting a plurality of groups of heat dissipation structures on at least one functional chip;
packaging all the functional chips and the heat dissipation structure to form a plastic package body;
Step six, thinning the plastic package body to expose the heat dissipation structure on the surface of the functional chip;
Step seven, removing the substrate;
Step eight, forming a conductive structure on one surface of the rewiring structure far away from the functional chip to obtain a package body;
and step nine, determining whether a PCB or an organic carrier is attached to the packaging body according to actual production requirements.
3. The method of manufacturing a chip package structure for improving heat dissipation and warpage as defined in claim 2, wherein in the second step, a re-wiring structure is formed on the substrate, and the step of forming a metal conductive structure on the metal pad on the surface of the re-wiring structure comprises:
Forming a first metal rewiring layer on the temporary bonding layer through the matching of a magnetron sputtering process, a photoetching process and an electroplating process, covering a first passivation layer on the first metal rewiring layer through a coating or film pressing process, and forming a conducting opening on the first passivation layer through the photoetching process; the metal rewiring layers are sequentially and alternately manufactured into other layers of metal rewiring layers and passivation layers according to the steps, each two adjacent metal rewiring layers are electrically connected, a metal conductive structure is formed on the metal rewiring layer on the uppermost layer, the subsequent electrical connection with a functional chip is facilitated, and the whole preparation of the rewiring structure is further completed;
because the metal circuits of the two metal rewiring layers positioned at the lowest layer and the uppermost layer are metal bonding pads, metal conductive structures are formed on the metal bonding pads at the uppermost layer, and the metal conductive structures are solder balls formed through a ball implantation process or metal bumps formed through an electroplating process.
4. The method for manufacturing a chip package structure for improving heat dissipation and warpage as defined in claim 2, wherein in the third step, two different functional chips, i.e. functional chip I and functional chip II, are connected to the redistribution structure, the number of functional chips I is plural, the number of functional chips II are stacked sequentially from top to bottom, and the functional chips I and II are electrically connected to the metal conductive structure, respectively.
5. The method for manufacturing a chip package structure for improving heat dissipation capability and warpage as claimed in claim 4, wherein in the fourth step, a group of heat dissipation structures are disposed on the functional chip I, and the heat dissipation structures include a heat dissipation film and bare silicon sequentially disposed from bottom to top.
6. The method for manufacturing a chip package structure for improving heat dissipation capability and warpage as claimed in claim 4, wherein in the fourth step, two or more groups of heat dissipation structures are provided on the functional chip I, the heat dissipation structures include heat dissipation films and bare silicon sequentially provided from bottom to top, and the heat dissipation films and bare silicon on the functional chip I are alternately arranged.
7. The method for manufacturing a chip package structure for improving heat dissipation capability and warpage as claimed in claim 5 or 6, wherein the heat dissipation film comprises an upper adhesive layer, an intermediate layer and a lower adhesive layer which are sequentially arranged from top to bottom, the upper adhesive layer and the lower adhesive layer have adhesiveness, and the intermediate layer is quartz glass, carbon nanotubes or graphene.
8. The method of claim 2, wherein in step nine, the conductive structures are solder balls formed by a ball mounting process when the PCB is mounted on the package, and plated metal bumps formed by a plating process when the carrier is mounted on the package.
9. A chip package structure prepared by the method for preparing a chip package structure for improving heat dissipation and improving warpage according to any one of claims 1 to 8.
10. The chip package structure for improving heat dissipation capability and improving warpage according to claim 9, comprising a rerouting structure, wherein a plurality of different functional chips are connected to the rerouting structure, each functional chip is a plurality of functional chips, the functional chips are electrically connected to a metal conductive structure, a plurality of groups of heat dissipation structures are arranged on at least one functional chip, each heat dissipation structure comprises a heat dissipation film and bare silicon which are sequentially arranged from bottom to top, a conductive structure is formed on one side of the rerouting structure far away from the functional chip, and a loading board is attached or not attached to the conductive structure.
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| CN202510454210.6A CN120300003A (en) | 2025-04-11 | 2025-04-11 | A chip packaging structure and preparation method for improving heat dissipation capability and warping |
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| CN202510454210.6A CN120300003A (en) | 2025-04-11 | 2025-04-11 | A chip packaging structure and preparation method for improving heat dissipation capability and warping |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111081649A (en) * | 2018-10-22 | 2020-04-28 | 三星电子株式会社 | Semiconductor packaging |
| CN221596429U (en) * | 2022-11-10 | 2024-08-23 | 台湾积体电路制造股份有限公司 | Package |
| CN221861640U (en) * | 2022-12-27 | 2024-10-18 | 台湾积体电路制造股份有限公司 | Semiconductor assembly |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111081649A (en) * | 2018-10-22 | 2020-04-28 | 三星电子株式会社 | Semiconductor packaging |
| CN221596429U (en) * | 2022-11-10 | 2024-08-23 | 台湾积体电路制造股份有限公司 | Package |
| CN221861640U (en) * | 2022-12-27 | 2024-10-18 | 台湾积体电路制造股份有限公司 | Semiconductor assembly |
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