CN120066203B - A data synchronization circuit and device - Google Patents
A data synchronization circuit and deviceInfo
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- CN120066203B CN120066203B CN202510151215.1A CN202510151215A CN120066203B CN 120066203 B CN120066203 B CN 120066203B CN 202510151215 A CN202510151215 A CN 202510151215A CN 120066203 B CN120066203 B CN 120066203B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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Abstract
The invention provides a data synchronization circuit and a data synchronization device, wherein the circuit comprises a signal input module, a signal modulation module, a demodulation module and a quick push-pull logic module, wherein the signal input module is used for acquiring input data and clock signals, the signal modulation module is used for modulating the input data based on clock signals to generate modulation signals, the quick push-pull logic module is used for carrying out quick push-pull based on the input data and the clock signals to acquire quick push-pull signals, the demodulation module comprises a Schmitt trigger, the demodulation module is used for carrying out preliminary demodulation on the modulation signals to acquire preliminary demodulation signals, then carrying out push-pull based on the quick push-pull signals to acquire push-pull modulation signals, and the Schmitt trigger is used for filtering the push-pull modulation signals and outputting terminal demodulation signals. The invention provides a data synchronization circuit and a data synchronization device, which can reduce signal delay and pulse width distortion, ensure the stability and reliability of a sequential logic circuit and reduce the problems of data errors and circuit misoperation.
Description
Technical Field
The present invention relates to the field of digital information transmission, and in particular, to a data synchronization circuit and apparatus.
Background
In today's electronic circuit technology, and in particular sequential logic circuits, data typically only changes when a clock edge arrives. In the synchronous logic circuit, all clock signals of the internal control circuit are from the same reference clock source, and the data is changed only when the unified clock edge is triggered. Whereas dynamic changes of data in asynchronous logic circuits may be driven by different clock sources, the phase relationship of the input data and clock is completely independent. When the clock edge comes, the input data can just change, so that the output of the asynchronous logic circuit generates an unstable state, and the stability and the reliability of the circuit are affected.
In addition to paying attention to the correctness of the output logic level, two indexes are also paid more attention. One is the delay of the output signal compared to the input signal. Such as the time difference between the rising edge of the output signal and the rising edge of the input signal. The other is pulse width distortion, i.e., the difference between the output signal pulse width and the input signal pulse width, which can also be defined as the difference between the rising edge delay time and the falling edge delay time. In the prior art, in order to avoid an unstable state when data is transmitted in different clock domains, a conventional asynchronous data synchronization method and a twice synchronization-twice sampling method are often adopted to reduce the probability of generating the unstable state. And during the subsampling method, there is a delay of approximately 2 clock cycles in the worst case. The maximum pulse width distortion is approximately 1 clock cycle. For the part fields with extremely high time sensitivity requirements, such as high-speed signal processing, real-time communication, precise measurement and the like, the processing mode can cause delay and pulse width distortion, influence the stability and reliability of a sequential logic circuit, and cause the problems of data errors, circuit misoperation and the like.
Disclosure of Invention
The invention aims to provide a data synchronization circuit and a data synchronization device, which are used for solving the technical problems, reducing signal delay and pulse width distortion, guaranteeing the stability and reliability of a sequential logic circuit, and reducing the problems of data errors, circuit misoperation and the like.
In order to solve the technical problems, the invention provides a data synchronization circuit, which comprises a signal input module, a signal modulation module, a demodulation module and a quick push-pull logic module, wherein:
The signal input module is used for acquiring input data and clock signals;
the signal modulation module is used for modulating the input data based on the clock signal to generate a modulation signal;
The quick push-pull logic module is used for carrying out quick push-pull based on the input data and the clock signal to obtain a quick push-pull signal;
The demodulation module comprises a Schmitt trigger;
The demodulation module is used for carrying out preliminary demodulation on the modulation signals to obtain preliminary demodulation signals, then pushing and pulling the preliminary demodulation signals based on the rapid push-pull signals to obtain push-pull modulation signals, and the Schmitt trigger is used for filtering the push-pull modulation signals and outputting terminal demodulation signals.
The quick push-pull logic module can avoid the condition that the primary demodulation signal shows that the first falling edge is quick and the last rising edge is slow, further prevent the terminal demodulation signal processed by the Schmitt trigger from having the problems of smaller rising edge delay and larger falling edge delay, effectively reduce the delay of the terminal demodulation signal, inhibit the pulse width distortion phenomenon, thereby realizing the accurate synchronization of data, ensuring the stability and the reliability of a time sequence logic circuit and reducing the occurrence of data errors and circuit misoperation.
Further, the signal modulation module comprises a first inverter and a first nor gate;
the first inverter is used for converting the input data into logic state inversion data and transmitting the logic state inversion data to the first NOR gate;
the first NOR gate is used for performing NOR operation on the logic state inversion data based on the clock signal and generating a modulation signal.
In the scheme, the first NOR gate executes NOR operation, wherein when input data is low level, a modulation signal modulated by the first NOR gate is in a low level state, and when the input data is high level, the modulation signal modulated by the first NOR gate is in inverse phase of a clock signal.
Further, the demodulation module comprises a narrowing pulse module and a filtering module;
The narrowing pulse module is used for carrying out preliminary demodulation and narrowing pulse on the modulated signal to obtain a preliminary demodulation signal, and transmitting the preliminary demodulation signal to the filtering module;
The Schmitt trigger is arranged in the filtering module;
The filtering module is used for pushing and pulling the preliminary demodulation signal based on the rapid push-pull signal and outputting a terminal demodulation signal through the Schmitt trigger.
In the scheme, the narrowing pulse module can perform pulse width compression processing on the modulation signal to obtain a preliminary demodulation signal with 2 times of clock frequency, and the filtering module can enable the waveform of the signal to be smoother. The irregular signal waveform can be more regular, the signal jitter is reduced, and the signal stability is improved.
Further, the narrowed pulse module comprises a delay and a second nor gate;
The delayer is used for carrying out signal delay on the modulation signal, obtaining a delayed modulation signal and transmitting the delayed modulation signal to the second NOR gate;
the second nor gate is configured to perform a nor operation on the modulated signal and the delayed modulated signal, generate a preliminary demodulation signal, and transmit the preliminary demodulation signal to the filtering module.
In the scheme, the delayer works cooperatively with the modulation signal, the second NOR gate performs NOR operation on the modulation signal and the delayed modulation signal to realize pulse width compression processing and obtain a preliminary demodulation signal with 2 times of clock frequency, and the delayer has a signal time sequence adjusting function, and realizes accurate regulation and control on each signal time sequence in the circuit by performing delay processing on the modulation signal and changing time correlation of the signal.
Further, the filtering module comprises a first NMOS tube, a second PMOS tube, a current limiting resistor, a voltage stabilizing capacitor and a second inverter;
The first NMOS tube and the second PMOS tube are used for carrying out asymmetric charge and discharge on a preliminary demodulation signal, acquiring a push-pull pre-signal, transmitting the push-pull pre-signal to a quick push-pull logic module, pushing and pulling the push-pull pre-signal by the quick push-pull logic module, acquiring a push-pull modulation signal and transmitting the push-pull modulation signal to a Schmidt trigger;
The first access end of the current limiting resistor is connected with the source electrode of the second PMOS tube, the second access end of the current limiting resistor is connected with the drain electrode of the first NMOS tube and the input end of the Schmitt trigger, and the current limiting resistor is used for limiting the charging current of the voltage stabilizing capacitor;
The first access end of the voltage stabilizing capacitor is connected with the second access end of the current limiting resistor and the input end of the Schmitt trigger, the second access end of the voltage stabilizing capacitor is connected with the ground, and the voltage stabilizing capacitor is used for stabilizing the push-pull signal;
The second inverter is used for carrying out logic state inversion on the push-pull modulation signal filtered by the Schmitt trigger so as to output a terminal demodulation signal.
In the scheme, the asymmetric charge and discharge changes the characteristics of the signal before push-pull by controlling the charge and discharge speed and the path of the voltage stabilizing capacitor, thereby playing the roles of adjusting the signal waveform, reducing the pulse width distortion and realizing the accurate synchronization of data.
Further, the asymmetric charge-discharge mode has two modes of slow charge, fast discharge and fast charge, slow discharge;
The slow charge and fast discharge mode specifically comprises that in a charging stage, the gate-source voltage of the first PMOS tube is larger than the starting voltage of the first PMOS tube, the first PMOS tube is in a relatively cut-off state, the power supply current slowly charges the voltage stabilizing capacitor through the current limiting resistor to enable the voltage of the voltage stabilizing capacitor to slowly rise, in a discharging stage, the gate-source voltage of the first NMOS tube is larger than the starting voltage of the first NMOS tube, the first NMOS tube is rapidly conducted to enable charges stored on the voltage stabilizing capacitor to be rapidly released through the first NMOS tube, the voltage of the voltage stabilizing capacitor is rapidly reduced, and a push-pull signal of slow charge and fast discharge is obtained;
The fast charging and slow discharging mode specifically comprises the steps that in a charging stage, the gate-source voltage of the first PMOS tube is smaller than the starting voltage of the first PMOS tube, the first PMOS tube is rapidly conducted, the power supply current rapidly flows to the voltage stabilizing capacitor, the voltage of the voltage stabilizing capacitor rapidly rises, in a discharging stage, the gate-source voltage of the first NMOS tube is smaller than the starting voltage of the first NMOS tube, the first NMOS tube is in a relatively cut-off state, the voltage stabilizing capacitor discharges through the current limiting resistor, the discharging current is smaller, the voltage of the voltage stabilizing capacitor slowly drops, and the push-pull signal of fast charging and slow discharging is obtained.
In the scheme, the slow charge and fast discharge enable the signal before push-pull to have the characteristics of slow rising edge and fast falling edge. If the processing is not added, the rising edge delay is small and the falling edge delay is large after the push-pull signal passes through the Schmitt trigger, so that the pulse width of the terminal demodulation signal is larger than that of the input data, the situation can be improved by slow charge and fast discharge, the pulse width distortion is reduced, the accuracy of data transmission is ensured, and the fast charge and slow discharge enable the push-pull signal to have the characteristics of fast rising edge and slow falling edge. If the processing is not added, the rising edge delay is large and the falling edge delay is small after the push-pull signal passes through the Schmitt trigger, so that the pulse width of the terminal demodulation signal is larger than the pulse width of input data;
further, the quick push-pull logic module comprises an AND gate and a first PMOS tube;
The AND gate is used for performing AND operation on the clock signal and the input data to obtain a preliminary push-pull signal, and transmitting the preliminary push-pull signal to the first PMOS tube;
The drain electrode of the first PMOS tube is connected with the input end of the Schmitt trigger, the grid electrode of the first PMOS tube is connected with the output end of the AND gate, the source electrode of the first PMOS tube is connected with the power supply, and the first PMOS tube is used for rapidly pushing and pulling the potential of the signal before pushing and pulling to obtain a push-pull modulation signal and transmitting the push-pull modulation signal to the Schmitt trigger.
In the scheme, after the rapid push-pull module is introduced to rapidly push-pull the push-pull signal, the problem of pulse width distortion caused by asymmetric charge and discharge can be solved, and the excessive distortion of pulse width is avoided.
Further, the quick push-pull has two modes of quick pull-up and quick pull-down;
the first PMOS tube is used for pulling up the potential of a signal before push-pull to the power supply voltage, obtaining a push-pull modulation signal for pull-up, and transmitting the push-pull modulation signal to the Schmitt trigger;
the fast pull-down mode is specifically that the first PMOS tube is used for pulling down the potential of a signal before push-pull to the ground potential, obtaining a pull-down push-pull modulation signal and transmitting the push-pull modulation signal to the Schmitt trigger.
In the above scheme, if the second PMOS transistor and the current limiting resistor are only relied on to charge the voltage stabilizing capacitor in the slow charge and fast discharge process, the rising edge of the push-pull modulation signal will be very slow. When the first PMOS tube is used for pulling up the push-pull modulation signal in a rapid pull-up mode, when the gate-source voltage of the first PMOS tube is smaller than the starting voltage of the first PMOS tube, the first PMOS tube is conducted, the first PMOS tube can rapidly pull up the potential of the signal before push-pull to the power voltage, the push-pull modulation signal which is pulled up is obtained, the problem of pulse width distortion caused by slow rising edge of the push-pull modulation signal is avoided, the problem that the falling edge of the signal before push-pull is not rapid enough exists in the process of rapid charging and slow discharging, rapid pull-down can ensure that the signal rapidly drops to a low level, adverse effects of pulse width distortion caused by slow falling of the signal before push-pull are avoided, and accuracy of data transmission and stability of signal processing are ensured.
The invention provides a data synchronization device, which comprises a shell, wherein the shell is internally provided with the data synchronization circuit, the shell is provided with a data input interface, a data output interface and a power interface, the data input interface is electrically connected with a signal input module, the data output interface is electrically connected with a demodulation module, and the power interface is electrically connected with a quick push-pull logic module.
The data synchronization device provided by the scheme is simple in structure, in practical application, the data input interface is only required to be connected with the signal input module, the data output interface is connected with the demodulation module and is used for powering on the quick push-pull logic module through the power interface, so that data synchronization can be stably and reliably completed, delay of a terminal demodulation signal is effectively reduced, pulse width distortion phenomenon is restrained, accurate synchronization of data is realized, stability and reliability of a sequential logic circuit are guaranteed, and data errors and circuit misoperation problems are reduced.
Drawings
FIG. 1 is a diagram of a data synchronization circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a data synchronization circuit according to an embodiment of the present invention;
FIG. 3 is a signal waveform diagram of a data synchronization circuit according to an embodiment of the present invention;
fig. 4 is a signal waveform diagram of a data synchronization circuit of a fast push-pull module according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present embodiment provides a data synchronization circuit, and the architecture thereof specifically referring to fig. 1 includes:
the signal input module is used for acquiring input data and clock signals;
the signal modulation module is used for modulating the input data based on the clock signal and generating a modulation signal;
The fast push-pull logic module is used for carrying out fast push-pull based on the input data and the clock signal to obtain a fast push-pull signal;
The demodulation module comprises a Schmitt trigger, and is used for carrying out preliminary demodulation on the modulation signal to obtain a preliminary demodulation signal, pushing and pulling the preliminary demodulation signal based on the rapid push-pull signal to obtain a push-pull modulation signal, and the Schmitt trigger is used for filtering the push-pull modulation signal and outputting a terminal demodulation signal.
The data synchronization circuit provided by the embodiment provides a new data synchronization mode to provide smaller delay and data pulse width distortion, adopts the input data and clock signals to be input into the quick push-pull logic module together to generate a quick push-pull signal so as to quickly push-pull the modulated signal, and adopts the quick push-pull logic module to avoid the condition that the initial demodulated signal shows that the first falling edge is quick and the last rising edge is slow, thereby preventing the problems of smaller rising edge delay and larger falling edge delay of the terminal demodulated signal processed by the Schmitt trigger, effectively reducing the delay of the terminal demodulated signal, inhibiting the pulse width distortion phenomenon, realizing the accurate synchronization of data, ensuring the stability and the reliability of the sequential logic circuit and reducing the occurrence of data errors and circuit misoperation problems.
Referring to fig. 2, a circuit structure diagram of a data synchronization circuit provided in this embodiment is shown, where the signal modulation module includes a first inverter and a first nor gate;
the first inverter is used for converting the input data into logic state inversion data and transmitting the logic state inversion data to the first NOR gate;
the first NOR gate is used for performing NOR operation on the logic state inversion data based on the clock signal and generating a modulation signal.
In this embodiment, the clock is used to perform OOK modulation on the input data, where OOK modulation may be implemented by a nor gate or an and gate; in this embodiment, a nor gate is used, where the nor gate performs nor operation, when input data is low level, a modulated signal modulated by the first nor gate is in a low level state, and when input data is high level, the modulated signal modulated by the first nor gate is an inversion of a clock signal, so that a problem of data synchronization is solved, and the nor gate can effectively reduce delay, so that the circuit can detect the level of the input data once every half clock signal period.
Further, the demodulation module comprises a narrowing pulse module and a filtering module;
the pulse narrowing module is used for primarily demodulating the modulated signal and narrowing the pulse to obtain a primarily demodulated signal, and transmitting the primarily demodulated signal to the filtering module;
The Schmitt trigger is arranged in the filtering module;
And the filtering module is used for pushing and pulling the preliminary demodulation signal based on the rapid push-pull signal and outputting a terminal demodulation signal through the Schmitt trigger.
In this embodiment, the narrowing pulse module may perform pulse width compression processing on the modulated signal to obtain a preliminary demodulation signal with 2 times of clock frequency, and the filtering module may make the waveform of the signal smoother. The method can change irregular signal waveforms into more regular, lower charging waveforms are filtered, signal jitter is reduced, square wave signal output is obtained, signal stability is improved, demodulation signals of the demodulated terminal only change when clock signals are low level, and therefore unstable state errors cannot occur when the terminal demodulation signals are collected on rising edges of the clock signals.
Further, the narrowed pulse module comprises a delay and a second nor gate;
The delayer is used for carrying out signal delay on the modulation signal, obtaining a delayed modulation signal and transmitting the delayed modulation signal to the second NOR gate;
the second nor gate is configured to perform a nor operation on the modulated signal and the delayed modulated signal, generate a preliminary demodulation signal, and transmit the preliminary demodulation signal to the filtering module.
In the embodiment, the delayer is cooperated with the modulation signal, the second NOR gate performs NOR operation on the modulation signal and the delayed modulation signal to realize pulse width compression processing and obtain a preliminary demodulation signal of narrow pulse with 2 times of clock frequency, and the delayer is provided with a signal time sequence adjusting function, and the time correlation of the signals is changed by performing delay processing on the modulation signal to realize accurate regulation and control on each signal time sequence in the circuit.
Further, the filtering module comprises a first NMOS tube, a second PMOS tube, a current limiting resistor, a voltage stabilizing capacitor and a second inverter;
The first NMOS tube and the second PMOS tube are used for carrying out asymmetric charge and discharge on a preliminary demodulation signal, acquiring a push-pull pre-signal, transmitting the push-pull pre-signal to a quick push-pull logic module, pushing and pulling the push-pull pre-signal by the quick push-pull logic module, acquiring a push-pull modulation signal and transmitting the push-pull modulation signal to a Schmidt trigger;
The first access end of the current limiting resistor is connected with the source electrode of the second PMOS tube, the second access end of the current limiting resistor is connected with the drain electrode of the first NMOS tube and the input end of the Schmitt trigger, and the current limiting resistor is used for limiting the charging current of the voltage stabilizing capacitor;
The first access end of the voltage stabilizing capacitor is connected with the second access end of the current limiting resistor and the input end of the Schmitt trigger, the second access end of the voltage stabilizing capacitor is connected with the ground, and the voltage stabilizing capacitor is used for stabilizing the push-pull signal;
The second inverter is used for carrying out logic state inversion on the push-pull modulation signal filtered by the Schmitt trigger so as to output a terminal demodulation signal.
In this embodiment, the first NMOS transistor and the second PMOS transistor form an inverter, and perform asymmetric charging and discharging, and the asymmetric charging and discharging changes the characteristics of the signal before push-pull by controlling the charging and discharging speed and path of the voltage stabilizing capacitor, so as to play roles in adjusting the signal waveform, reducing pulse width distortion, and realizing accurate synchronization of data.
Further, the asymmetric charge-discharge mode has two modes of slow charge, fast discharge and fast charge, slow discharge;
The slow charge and fast discharge mode specifically comprises that in a charging stage, the gate-source voltage of the first PMOS tube is larger than the starting voltage of the first PMOS tube, the first PMOS tube is in a relatively cut-off state, the power supply current slowly charges the voltage stabilizing capacitor through the current limiting resistor to enable the voltage of the voltage stabilizing capacitor to slowly rise, in a discharging stage, the gate-source voltage of the first NMOS tube is larger than the starting voltage of the first NMOS tube, the first NMOS tube is rapidly conducted to enable charges stored on the voltage stabilizing capacitor to be rapidly released through the first NMOS tube, the voltage of the voltage stabilizing capacitor is rapidly reduced, and a push-pull signal of slow charge and fast discharge is obtained;
The fast charging and slow discharging mode specifically comprises the steps that in a charging stage, the gate-source voltage of the first PMOS tube is smaller than the starting voltage of the first PMOS tube, the first PMOS tube is rapidly conducted, the power supply current rapidly flows to the voltage stabilizing capacitor, the voltage of the voltage stabilizing capacitor rapidly rises, in a discharging stage, the gate-source voltage of the first NMOS tube is smaller than the starting voltage of the first NMOS tube, the first NMOS tube is in a relatively cut-off state, the voltage stabilizing capacitor discharges through the current limiting resistor, the discharging current is smaller, the voltage of the voltage stabilizing capacitor slowly drops, and the push-pull signal of fast charging and slow discharging is obtained.
In this embodiment, the slow charge and fast discharge makes the pre-push signal exhibit the characteristics of slow rising edge and fast falling edge. If the processing is not added, the rising edge delay is small and the falling edge delay is large after the push-pull signal passes through the Schmitt trigger, so that the pulse width of the terminal demodulation signal is larger than that of the input data, the situation can be improved by slow charge and fast discharge, the pulse width distortion is reduced, the accuracy of data transmission is ensured, and the fast charge and slow discharge enable the push-pull signal to have the characteristics of fast rising edge and slow falling edge. If the processing is not added, the rising edge delay is large and the falling edge delay is small after the push-pull signal passes through the Schmitt trigger, so that the pulse width of the terminal demodulation signal is larger than the pulse width of input data;
further, the quick push-pull logic module comprises an AND gate and a first PMOS tube;
The AND gate is used for performing AND operation on the clock signal and the input data to obtain a preliminary push-pull signal, and transmitting the preliminary push-pull signal to the first PMOS tube;
The drain electrode of the first PMOS tube is connected with the input end of the Schmitt trigger, the grid electrode of the first PMOS tube is connected with the output end of the AND gate, the source electrode of the first PMOS tube is connected with the power supply, and the first PMOS tube is used for rapidly pushing and pulling the potential of the signal before pushing and pulling to obtain a push-pull modulation signal and transmitting the push-pull modulation signal to the Schmitt trigger.
In this embodiment, since the and gate is used to perform and operation on the clock signal and the input data, if the input data has become low level at this time, the preliminary push-pull signal will change to low level along with the falling edge of the clock signal when the clock signal changes to low level from high level, after the preliminary push-pull signal changes to low level, the first PMOS transistor will become conductive, at this time, the push-pull modulation signal is pulled up to high level, if the logic module is not pushed up quickly, the push-pull modulation signal of the logic module is not pushed up quickly, the rising edge delay is small, the falling speed is fast, the pulse width of the terminal demodulation signal after passing through the schmitt trigger will be greater than the pulse width of the input data, resulting in increased pulse width distortion, and after the fast push-pull module is introduced to push-pull the signal quickly, the problem of pulse width distortion generated due to asymmetric charge and discharge can be improved, and the excessive distortion of pulse width is avoided.
Further, the quick push-pull has two modes of quick pull-up and quick pull-down;
the first PMOS tube is used for pulling up the potential of a signal before push-pull to the power supply voltage, obtaining a push-pull modulation signal for pull-up, and transmitting the push-pull modulation signal to the Schmitt trigger;
the fast pull-down mode is specifically that the first PMOS tube is used for pulling down the potential of a signal before push-pull to the ground potential, obtaining a pull-down push-pull modulation signal and transmitting the push-pull modulation signal to the Schmitt trigger.
In this embodiment, in the slow charge and fast discharge process, if the second PMOS transistor and the current limiting resistor are only used to charge the voltage stabilizing capacitor, the rising edge of the push-pull modulation signal will be slow. When the first PMOS tube is used for pulling up the push-pull modulation signal in a rapid pull-up mode, when the gate-source voltage of the first PMOS tube is smaller than the starting voltage of the first PMOS tube, the first PMOS tube is conducted, the first PMOS tube can rapidly pull up the potential of the signal before push-pull to the power voltage at the moment, the push-pull modulation signal which is pulled up is obtained, the problem of pulse width distortion caused by slow rising edge of the signal before push-pull is avoided, the problem that the falling edge of the signal before push-pull is not rapid enough exists in the process of rapid charging and slow discharging, the signal before push-pull can be pulled down to be rapidly lowered to a low level by rapid pull, adverse effects of pulse width distortion caused by slow falling of the signal before push-pull are avoided, accuracy of data transmission and stability of signal processing are guaranteed, and after rapid push-pull, the terminal demodulation signal is lowered to 0.5 cycle delay from 2 cycle delay.
Referring to fig. 3, a signal waveform diagram of a data synchronization circuit provided in this embodiment is generated by a fast pull-up method in fast push-pull, in which data_in is input data, clk is a clock signal, a is a modulated signal, b is a preliminary demodulation signal, c is a preliminary push-pull signal, d is a push-pull modulation signal, data_out is a terminal demodulation signal, fig. 4 is a signal waveform diagram of an unsprung fast push-pull logic module, in which data_in is input data, clk is a clock signal, a is a modulated signal, b is a preliminary demodulation signal, c is a preliminary push-pull signal, d is a push-pull modulation signal, and data_out is a terminal demodulation signal, fig. 4 and fig. 3 are compared, only the last edge signal of the push-pull modulation signal and the terminal demodulation signal is found to be different, and after the fast pull-up method in fast push-pull, the maximum delay and pulse width distortion of the terminal demodulation signal data_out are both 1/2 clock cycles, thereby achieving the purposes of effectively reducing delay of the terminal demodulation signal and suppressing pulse width distortion.
Further, the embodiment provides a data synchronization device, which comprises a shell, wherein the shell is internally provided with the data synchronization circuit, the shell is provided with a data input interface, a data output interface and a power interface, the data input interface is electrically connected with the signal input module, the data output interface is electrically connected with the demodulation module, and the power interface is electrically connected with the quick push-pull logic module.
The data synchronization device provided in the embodiment has a simple structure, and in practical application, the data synchronization device is only connected with the signal input module through the data input interface, the data output interface is connected with the demodulation module and powers on the quick push-pull logic module through the power interface, so that the data synchronization can be stably and reliably completed, the delay of a terminal demodulation signal is effectively reduced, the pulse width distortion phenomenon is restrained, the accurate synchronization of data is realized, the stability and the reliability of a sequential logic circuit are ensured, and the occurrence of data errors and circuit misoperation problems is reduced.
The embodiment can be applied to a transmission scene of a motor PWM driving signal in an isolation chip, and because the PWM signal is closely related to dead time which directly affects energy loss and efficiency in a motor driving process, and meanwhile, pulse width distortion plays a key role in motor control accuracy, so that delay of the PWM signal in the transmission process is reduced, the pulse width distortion phenomenon is reduced, and the method is important for optimizing motor driving performance, improving the overall energy efficiency of a motor system and realizing accurate motor control. The data synchronization circuit effectively solves the problems of signal delay and pulse width distortion, improves the control precision of the motor, reduces the energy loss, provides reliable guarantee for efficient and stable operation of the motor, and has wide application prospect and remarkable practical value.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (6)
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5172397A (en) * | 1991-03-05 | 1992-12-15 | National Semiconductor Corporation | Single channel serial data receiver |
| CN102707766A (en) * | 2011-03-18 | 2012-10-03 | 瑞昱半导体股份有限公司 | Signal synchronization device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5172397A (en) * | 1991-03-05 | 1992-12-15 | National Semiconductor Corporation | Single channel serial data receiver |
| CN102707766A (en) * | 2011-03-18 | 2012-10-03 | 瑞昱半导体股份有限公司 | Signal synchronization device |
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