CN216819829U - High-speed sampling circuit and SerDes receiver and chip including the high-speed sampling circuit - Google Patents

Abstract

The high-speed sampling circuit and the SerDes receiver and chip including the high-speed sampling circuit include a series of MOS tubes. The utility model allocates sampling and decision operations to two stages of clock low level and high level respectively, which reduces the need for Circuit response speed requirements. At the same time, by designing a precharge circuit, the influence of parasitic capacitance is offset, and the output response speed is improved. Compared with the traditional StrongArm structure, the utility model has the advantage of small output load capacitance.

Description

High-speed sampling circuit and SerDes receiver and chip including the high-speed sampling circuit

technical field

The utility model relates to the technical field of sampling circuits, in particular to a high-speed sampling circuit, a SerDes receiver and a chip including the high-speed sampling circuit.

Background technique

The high-speed serial interface (Serializer-Deserializer, SerDes) is one of the core devices of the data center, which supports the high-speed data transmission requirements of 5G communication, autonomous driving, telemedicine and other big data application scenarios. The receiver is located at the receiving end of the SerDes, and is used to convert the received high-speed serial signal into a low-speed parallel signal, which is then handed over to the subsequent part for digital processing. The sampling circuit is an important component of the SerDes receiver, which is used to sample and quantize the received signal. With the continuous improvement of the data transmission rate, the time margin of the sampling circuit is getting smaller and smaller. How to improve the response speed and realize fast sampling and quantization is the key problem that needs to be solved in the high-speed SerDes receiver.

The existing sampling circuit is generally based on the StrongArm structure. As shown in Figure 1, the MOS transistor M0 provides tail current under the control of the clock signal CLK. /M8 is a pull-up MOS tube. The working principle of this circuit is: when the clock signal CLK is at a low level, M7/M8 is turned on, M0 is turned off, and the output terminals Vop/Von are both pulled up to VDD, which is the reset stage; when CLK is at a high level , M0 is turned on, and M7/M8 is turned off. Assuming Vip>Vin, then the current flowing through M1 is greater than the current flowing through M2, the voltage at the Von terminal will drop faster than the Vop terminal, and Vop-Von is the amplified Vip-Vin, which is the sampling stage; with the voltage at the Von terminal When the voltage drops, M6 is gradually turned on. Once M6 is turned on, the inverter composed of M6 and M4 will make the Vop terminal voltage drop and be pulled up quickly, and the inverter composed of M5 and M3 will continue to pull down the Von terminal voltage. , this time is the regeneration stage; finally Vop is pulled up to VDD, Von is pulled down to the ground, this time is the judgment stage. Similarly, if Vip<Vin, Vop will be pulled down to ground eventually, and Von will be pulled up to VDD. It can be seen that when Vip>Vin is input, Vop>Von is output, and when Vip<Vin, Vop<Von is output, which realizes the correct level judgment.

Obviously, in one clock cycle, the StrongArm structure is only in the working state for half of the time, plus the influence of parasitic capacitance, the circuit must complete sampling, regeneration and judgment in much less than half of the clock cycle. At high data rates, tight timing margins will be faced.

Utility model content

Aiming at the above problems existing in the prior art, the present invention provides a high-speed sampling circuit, a SerDes receiver and a chip including the high-speed sampling circuit, with the purpose of relieving the tight timing margin of the sampling circuit.

For achieving the above object, the technical scheme adopted by the present utility model is:

On the one hand, the utility model provides a high-speed sampling circuit, comprising:

A tail current circuit for providing tail current;

The input circuit includes MOS transistors M1 and M2. The MOS transistors M1 and M2 form an input pair. The source of the MOS transistor M1 is connected to the source of the MOS transistor M2. The gate of the MOS transistor M1 is connected to the input Vip terminal. The gate is connected to the input Vin;

The isolation circuit includes MOS transistors M3 and M4, MOS transistors M3 and M4 are used as isolation transistors, the source of MOS transistor M3 is connected to the drain of MOS transistor M1, the source of MOS transistor M4 is connected to the drain of MOS transistor M2, and the MOS transistor M3 The gate of the MOS tube M4 is connected to the gate of the MOS tube M4, the drain of the MOS tube M3 is connected to the drain of the MOS tube M5, the drain of the MOS tube M4 is connected to the drain of the MOS tube M6, and the gate of the MOS tube M5 is connected to the drain of the MOS tube M6. The gate, the source of the MOS transistor M5 and the source of the MOS transistor M6 are connected to the VDD terminal;

Latch circuit, MOS transistors M7, M8, M9, M10, M11 form a latch, the source of MOS transistor M7 and the source of MOS transistor M9 are connected to the VDD terminal, the gate of MOS transistor M7 is connected to the gate of MOS transistor M8 The gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, the drain of the MOS transistor M7 is connected to the drain of the MOS transistor M8, the drain of the MOS transistor M9 is connected to the drain of the MOS transistor M10, and the source of the MOS transistor M8 , The source of the MOS transistor M10 is connected to the drain of the MOS transistor M11, the gate of the MOS transistor M11 is connected to the clock signal CLK, and the source of the MOS transistor M11 is grounded;

The drain of the MOS transistor M5, the drain of the MOS transistor M7 and the gate of the MOS transistor M9 are commonly connected to the output Von terminal, and the drain of the MOS transistor M6, the gate of the MOS transistor M7 and the drain of the MOS transistor M9 are commonly connected to the output Vop end.

The utility model allocates sampling and decision operations to two stages of clock low level and high level respectively. When the clock signal CLK is low level, the MOS tubes M7 to M11 in the latch stop working, and the MOS tubes M3 and M4 , M5, M6 are turned on, and the output signal Vop-Von is the amplified Vip-Vin, which is in the sampling stage at this time; when the clock signal CLK is at a high level, the MOS transistors M0, M1, M2, M3, M4, M5, M6 All are cut off, and the latch composed of M7, M8, M9, M10 and M11 uses positive feedback to latch and output the sampled value just before the end of the sampling phase, which is the judgment phase.

As a preferred solution of the present invention, it also includes a pre-charging circuit. The pre-charging circuit includes a MOS transistor M12, a MOS transistor M13 and two parasitic capacitors Cx. The source of the MOS transistor M12 is connected to the VDD terminal, and the source of the MOS transistor M13 is connected to VDD. terminal, the gate of the MOS transistor M12 is connected to the gate of the MOS transistor M1 as the input Vip terminal, the gate of the MOS transistor M13 is connected to the gate of the MOS transistor M2 as the input Vin terminal, and the drain of the MOS transistor M12 is connected to the MOS transistor M1 The drain of the MOS transistor M13 is connected to the drain of the MOS transistor M2, and one end of the first parasitic capacitance is connected to the X point between the source of the MOS transistor M3 and the drain of the MOS transistor M1. The other end of the capacitor is grounded, one end of the second parasitic capacitor is connected to point X between the source of the MOS transistor M4 and the drain of the MOS transistor M2, and the other end of the second parasitic capacitor is grounded.

On the other hand, the present invention provides a SerDes receiver, which includes a sampling circuit, and the sampling circuit is any one of the above-mentioned high-speed sampling circuits.

On the other hand, the present invention provides a chip including any of the above high-speed sampling circuits.

With respect to the prior art, the present utility model has the following beneficial technical effects:

1. Compared with the traditional StrongArm architecture, the present utility model has the advantage of alleviating the timing margin, which is embodied in: (1) The sampling and decision operations are respectively allocated to the clock low level and high level to complete in two stages, which reduces the need for the circuit. Response speed requirements; (2) By adding two precharge tubes, MOS tube M12 and MOS tube M13, to offset the influence of parasitic capacitance and improve the output response speed.

2. Compared with the traditional StrongArm structure, the utility model has the advantages of small output load capacitance, which is embodied in: since the MOS tube M12 and the MOS tube M1 form a CMOS inverter, and the MOS tube M13 and the MOS tube M2 form a CMOS inverter , the signal at node X is close to full swing. The MOS tube M3 and the MOS tube M4 are used as isolation tubes, and isolation can be achieved by using a small size, while reducing the requirement of circuit gain. The MOS transistor M5 and the MOS transistor M6 can also be small in size, thereby reducing the load capacitance of the output terminal and extending the bandwidth.

Description of drawings

The present utility model will be described in further detail below with reference to the accompanying drawings and specific embodiments.

Fig. 1 is a schematic diagram of the traditional StrongArm structure sampling circuit structure;

2 is a schematic diagram of a circuit structure of an embodiment of the present invention;

Fig. 3 is the sequence diagram of the embodiment shown in Fig. 2;

The purpose realization, functional characteristics and advantages of the present utility model will be further described with reference to the accompanying drawings in conjunction with the embodiments.

Detailed ways

The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, but not all of them. Example. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

It should be noted that the descriptions such as “first” and “second” in the present invention are only used for description purposes, and should not be interpreted as indicating or implying their relative importance or implying the number of indicated technical features. . Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that the technical solutions The combination does not exist and is not within the protection scope required by the present invention.

An embodiment of the present utility model provides a novel high-speed sampling circuit, which aims to relieve the tight timing margin of the sampling circuit. Its circuit structure is shown in Figure 2. For the input pair of tubes, the MOS tube M3 and the MOS tube M4 are isolation tubes, the MOS tubes M7-M11 form a latch, and the MOS tube M12 and the MOS tube M13 are pre-charging tubes.

The tail current circuit is used to provide tail current. The tail current circuit includes a MOS transistor M0, the drain of the MOS transistor M0 is connected to the source of the MOS transistor M1 and the source of the MOS transistor M2, the gate of the MOS transistor M0 is connected to Vb, and the source of the MOS transistor M0 is grounded, where Vb is a set bias voltage.

The input circuit includes MOS transistors M1 and M2. The MOS transistors M1 and M2 form an input pair. The source of the MOS transistor M1 is connected to the source of the MOS transistor M2. The gate of the MOS transistor M1 is connected to the input Vip terminal. The gate is connected to the input Vin;

The isolation circuit includes MOS transistors M3 and M4, MOS transistors M3 and M4 are used as isolation transistors, the source of MOS transistor M3 is connected to the drain of MOS transistor M1, the source of MOS transistor M4 is connected to the drain of MOS transistor M2, and the MOS transistor M3 The gate of the MOS tube M4 is connected to the gate of the MOS tube M4, the drain of the MOS tube M3 is connected to the drain of the MOS tube M5, the drain of the MOS tube M4 is connected to the drain of the MOS tube M6, and the gate of the MOS tube M5 is connected to the drain of the MOS tube M6. The gate, the source of the MOS transistor M5 and the source of the MOS transistor M6 are connected to the VDD terminal;

Latch circuit, MOS transistors M7, M8, M9, M10, M11 form a latch, the source of MOS transistor M7 and the source of MOS transistor M9 are connected to the VDD terminal, the gate of MOS transistor M7 is connected to the gate of MOS transistor M8 The gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, the drain of the MOS transistor M7 is connected to the drain of the MOS transistor M8, the drain of the MOS transistor M9 is connected to the drain of the MOS transistor M10, and the source of the MOS transistor M8 , The source of the MOS transistor M10 is connected to the drain of the MOS transistor M11, the gate of the MOS transistor M11 is connected to the clock signal CLK, and the source of the MOS transistor M11 is grounded.

The drain of the MOS transistor M5, the drain of the MOS transistor M7 and the gate of the MOS transistor M9 are commonly connected to the output Von terminal, and the drain of the MOS transistor M6, the gate of the MOS transistor M7 and the drain of the MOS transistor M9 are commonly connected to the output Vop end.

Precharge circuit, the precharge circuit includes MOS transistor M12, MOS transistor M13 and two parasitic capacitors Cx, the source of MOS transistor M12 is connected to the VDD terminal, the source of the MOS transistor M13 is connected to the VDD terminal, and the gate of the MOS transistor M12 is used as an input The Vip terminal is connected to the gate of the MOS transistor M1, the gate of the MOS transistor M13 is connected to the gate of the MOS transistor M2 as the input Vin, the drain of the MOS transistor M12 is connected to the drain of the MOS transistor M1, and the drain of the MOS transistor M13 Connected to the drain of the MOS transistor M2, one end of the first parasitic capacitance is connected to the X point between the source of the MOS transistor M3 and the drain of the MOS transistor M1, the other end of the first parasitic capacitance is grounded, and the second parasitic capacitance One end of the second parasitic capacitor is connected to the X point between the source electrode of the MOS transistor M4 and the drain electrode of the MOS transistor M2, and the other end of the second parasitic capacitor is grounded.

The working principle of the circuit is as follows: the sampling and judgment operations are respectively allocated to the clock low level and high level to complete. When the clock signal CLK is low level, the MOS tubes M7~M11 in the latch stop working, and the MOS transistors M7~M11 stop working. The tubes M3, M4, M5, and M6 are turned on, and the output signal Vop-Von is the amplified Vip-Vin, which is in the sampling stage; when the clock signal CLK is at a high level, the MOS tubes M0, M1, M2, M3, M4 , M5, M6 are all cut off, the latch composed of M7, M8, M9, M10 and M11 uses positive feedback to latch and output the sampled value just before the end of the sampling stage, which is the judgment stage. It can be found that, unlike the traditional StrongArm structure, which completes the sampling and decision operations in the same half cycle, this circuit has completed the sampling and amplification operations before CLK becomes high, and within half a cycle when CLK is low Only the decision operation needs to be completed, which relieves the tight timing margin.

By adding two precharge tubes, MOS tube M12 and MOS tube M13, to offset the influence of the parasitic capacitance Cx at node X, speed up the level transition at point X when the input signal changes, and improve the output response speed. The specific principle is: after the SerDes receiver works stably, under the action of the clock and data recovery circuit (Clock and Data Recovery, CDR), the transition edge of the clock signal is aligned with the midpoint of the data symbol, as shown in Figure 3. Taking the half-rate sampling architecture as an example (that is, the sampling clock period is equal to 2 unit symbol lengths), ideally, when the input signal changes, the sampling phase has a settling time of 1/4 cycle. However, due to the parasitic capacitance at node X, its charging and discharging process will slow down the transition speed at point X (for example, when the input signal Vip changes from a low level to a high level, the parasitic capacitance Cx needs to be discharged; Vip changes from a high level When it is a low level, the parasitic capacitance Cx needs to be charged), which in turn affects the level transition of the output terminal and prolongs the sampling setup time. Since the MOS transistor M12 and the MOS transistor M1 form a CMOS inverter, and the MOS transistor M13 and the MOS transistor M2 form a CMOS inverter, when the input signal changes, the charging and discharging speed of the parasitic capacitance Cx is accelerated, thereby reducing the sampling setup time. Impact.

In another embodiment of the present invention, a SerDes receiver is provided, which includes a sampling circuit, and the sampling circuit is the high-speed sampling circuit described in the above embodiments.

In another embodiment of the present invention, a chip is provided, including the high-speed sampling circuit described in the above embodiments.

Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that these are only examples, and various changes or modifications can be made to the embodiments without departing from the principles and essence of the present invention. The protection scope of the present invention is limited only by the appended claims.

Claims (6)

1. high-speed sampling circuit, is characterized in that, comprises: A tail current circuit for providing tail current; The input circuit includes MOS transistors M1 and M2. The MOS transistors M1 and M2 form an input pair. The source of the MOS transistor M1 is connected to the source of the MOS transistor M2. The gate of the MOS transistor M1 is connected to the input Vip terminal. The gate is connected to the input Vin; The isolation circuit includes MOS transistors M3 and M4, MOS transistors M3 and M4 are used as isolation transistors, the source of MOS transistor M3 is connected to the drain of MOS transistor M1, the source of MOS transistor M4 is connected to the drain of MOS transistor M2, and the MOS transistor M3 The gate of the MOS tube M4 is connected to the gate of the MOS tube M4, the drain of the MOS tube M3 is connected to the drain of the MOS tube M5, the drain of the MOS tube M4 is connected to the drain of the MOS tube M6, and the gate of the MOS tube M5 is connected to the drain of the MOS tube M6. The gate, the source of the MOS transistor M5 and the source of the MOS transistor M6 are connected to the VDD terminal; Latch circuit, MOS transistors M7, M8, M9, M10, M11 form a latch, the source of MOS transistor M7 and the source of MOS transistor M9 are connected to the VDD terminal, and the gate of MOS transistor M7 is connected to the gate of MOS transistor M8 The gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, the drain of the MOS transistor M7 is connected to the drain of the MOS transistor M8, the drain of the MOS transistor M9 is connected to the drain of the MOS transistor M10, and the source of the MOS transistor M8 , the source of the MOS transistor M10 is connected to the drain of the MOS transistor M11, the gate of the MOS transistor M11 is connected to the clock signal CLK, and the source of the MOS transistor M11 is grounded; The drain of the MOS transistor M5, the drain of the MOS transistor M7 and the gate of the MOS transistor M9 are commonly connected to the output Von terminal, and the drain of the MOS transistor M6, the gate of the MOS transistor M7 and the drain of the MOS transistor M9 are commonly connected to the output Vop end. 2. The high-speed sampling circuit according to claim 1, wherein the tail current circuit comprises a MOS transistor M0, the drain of the MOS transistor M0 is connected to the source of the MOS transistor M1, the source of the MOS transistor M2, and the The gate is connected to Vb, and the source of the MOS transistor M0 is connected to the ground. 3. The high-speed sampling circuit according to claim 2, wherein when the clock signal CLK is at a low level, the MOS tubes M7-M11 in the latch stop working, and the MOS tubes M3, M4, M5, and M6 are turned on, The output signal Vop-Von is the amplified Vip-Vin, which is in the sampling stage at this time; when the clock signal CLK is at a high level, the MOS transistors M0, M1, M2, M3, M4, M5, and M6 are all turned off, and M7, M8, The latch composed of M9, M10 and M11 uses positive feedback to latch and output the sampled value just before the end of the sampling phase, which is the decision phase. 4. The high-speed sampling circuit according to claim 2, further comprising a pre-charging circuit, the pre-charging circuit comprises a MOS transistor M12, a MOS transistor M13 and two parasitic capacitors Cx, and the source of the MOS transistor M12 is connected to the VDD terminal , the source of the MOS transistor M13 is connected to the VDD terminal, the gate of the MOS transistor M12 is connected to the gate of the MOS transistor M1 as the input Vip terminal, and the gate of the MOS transistor M13 is connected to the gate of the MOS transistor M2 as the input Vin terminal. The drain of the transistor M12 is connected to the drain of the MOS transistor M1, the drain of the MOS transistor M13 is connected to the drain of the MOS transistor M2, and one end of the first parasitic capacitance is connected between the source of the MOS transistor M3 and the drain of the MOS transistor M1. At point X in between, the other end of the first parasitic capacitor is grounded, one end of the second parasitic capacitor is connected to the X point between the source of the MOS transistor M4 and the drain of the MOS transistor M2, and the other end of the second parasitic capacitor ground. 5 . A SerDes receiver, characterized by comprising a sampling circuit, the sampling circuit being the high-speed sampling circuit according to any one of claims 1 to 4 . 6. A chip, characterized by comprising the high-speed sampling circuit according to any one of claims 1 to 4.

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