CN120012442B - A system-level random verification method and system for a universal MCU verification platform - Google Patents
A system-level random verification method and system for a universal MCU verification platformInfo
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Abstract
本发明提供一种通用MCU验证平台的系统级随机验证方法及系统，涉及仿真验证技术领域，包括：在硬件环境中基于随机变量和硬件约束条件生成随机激励存储至被验证设备中；被验证设备的MCU调取存储的随机激励并添加软件约束条件，随后将软件约束后的随机激励用作于随机仿真得到仿真结果；硬件环境读取软件约束后的随机激励产生期望结果，在比较期望结果和仿真结果不一致时输出警示信息完成随机验证。有益效果是可以模拟出各种可能的时序关系，从而确保验证过程能够覆盖到更多的场景和情况，提高验证的全面性。从而大大增强了随机化的能力；可以兼容现有的任一MCU验证平台，不会对现有验证环境造成影响，只是对现有验证环境功能的扩展。
The present invention provides a system-level random verification method and system for a universal MCU verification platform, which relates to the field of simulation verification technology, including: generating random excitations based on random variables and hardware constraints in a hardware environment and storing them in a verified device; the MCU of the verified device retrieves the stored random excitations and adds software constraints, and then uses the random excitations after software constraints for random simulation to obtain simulation results; the hardware environment reads the random excitations after software constraints to produce expected results, and outputs a warning message to complete random verification when the expected results are inconsistent with the simulation results. The beneficial effect is that various possible timing relationships can be simulated, thereby ensuring that the verification process can cover more scenarios and situations, and improving the comprehensiveness of the verification. This greatly enhances the ability of randomization; it is compatible with any existing MCU verification platform, will not affect the existing verification environment, and is only an extension of the functions of the existing verification environment.
Description
Technical Field
The invention relates to the technical field of simulation verification, in particular to a system-level random verification method and system of a universal MCU verification platform.
Background
A Micro Controller Unit (MCU) is an integrated circuit integrated with a Central Processing Unit (CPU), a memory and other peripheral devices, and is widely used in various fields such as industrial control, medical equipment, automotive electronics, etc. In order to ensure the reliability and stability of the system, simulation verification technology plays a crucial role. In the simulation verification process of the MCU, a random verification method based on System Verilog is often adopted for module-level verification, and System-level verification focuses on directional verification, and the main purpose is to check the accuracy of the connection relationship between systems.
MCUs are typically designed as systems that contain multiple clock domains. Taking a clock system of 32-bit MCU as an example, it may include five clocks, i.e. an external high-speed clock HSE, an internal high-speed clock HRC, an internal low-speed clock LRC, an external low-speed clock LSE and a phase-locked loop clock PLL, so as to adapt to the working requirements under normal functions and low-power modes. These clocks are not only used for different modules and modes, but also allow the user to divide and switch the system clock at any time the MCU is running, so that the actual operation timing of the MCU becomes very complex. In addition, the modules of the MCU integrate various communication protocols, which create more complex timing problems with respect to uncertainties in data transmission (e.g., data length, transmission timing, and clock rate, etc.). When the verification personnel face the verification difficulties of cross clock domains, clock phases, clock frequency division and the like caused by complex time sequences and the verification points of a plurality of deterministic functions of each MCU module, the comprehensive consideration in system level verification is difficult, and the effective verification is difficult to be carried out through the directional test cases.
At present, the random verification method is mainly realized through a System Verilog language in a simulation environment. System Verilog, a hardware description language, supports behavioral level, register Transfer Level (RTL) and gate level descriptions, and is widely used in the design and verification of digital circuits. In System Verilog, random test vectors can be generated by defining a random environment and testing is performed by read and write operations with MCU registers. While existing random verification methods improve verification efficiency and coverage to some extent, some challenges and limitations remain. Although the current MCU verification method can randomize the working scene of the modules to a certain extent, the randomization capability is still insufficient when the time sequence interaction among the modules or the verification of the complex use scene are processed.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a system-level random verification method of a universal MCU verification platform, which comprises the steps of S1, S2, wherein random excitation is generated and stored in verified equipment based on random variables and hardware constraint conditions in a hardware environment, MCU of the verified equipment invokes the stored random excitation and adds software constraint conditions, then the random excitation after software constraint is used for random simulation to obtain a simulation result, S3, the hardware environment reads the random excitation after software constraint to generate an expected result, and warning information is output to complete random verification when the expected result is compared with the simulation result.
Preferably, the step S1 comprises the step S11 of generating initial random excitation according to the random variable in the hardware environment, the step S12 of limiting the range of the initial random excitation according to the hardware constraint condition in the hardware environment and/or obtaining the random excitation by numerical elimination completion constraint and storing the random excitation to the verified device.
Preferably, after executing the step S1, a stimulus monitoring process is further included, including that the hardware environment monitors the random stimulus stored in the verified device, and when the random stimulus is invoked, the step S1 is executed again to regenerate the random stimulus for storing in the verified device.
Preferably, the verified device is provided with a storage space, the random excitation is stored in the storage space, and the method further comprises an excitation rewriting process after the step S1 is executed, wherein the hardware environment monitors the storage space, and when the data in the storage space is lost, the generated random excitation is rewritten in the storage space.
Preferably, each simulation result is associated with a piece of log information, the time in the hardware environment is used as the random variable, and when the simulation result is obtained each time, the corresponding random variable is recorded in the associated log information.
Preferably, the random simulation process is that the MCU is configured according to the random excitation, and after the configuration is finished, a pre-written function is executed in the MCU to obtain a corresponding simulation result.
Preferably, the MCU needs at least two random excitations for configuration, in the step S1, the hardware environment further obtains external excitations after generating the random excitations, the random excitations and the external excitations are stored in the MCU, and in the random simulation process, the MCU is configured according to the random excitations and the external excitations.
The invention further provides a system-level random verification system of the universal MCU verification platform, the system-level random verification system comprises a stimulus generation environment and verified equipment, a hardware environment in the stimulus generation environment comprises a random stimulus generation module, a first monitoring module, a desired generation module and a second monitoring module, wherein the random stimulus generation module is used for generating the random stimulus according to the random variable and the hardware constraint condition and storing the random stimulus in a storage space of the verified equipment, the first monitoring module is used for monitoring the configuration of an MCU of the verified equipment in a random simulation process and monitoring the random stimulus in the storage space, the desired generation module is connected with the first monitoring module and used for receiving the configuration sent by the first monitoring module and generating the corresponding desired result, the second monitoring module is used for monitoring the simulation result generated by the MCU in a random simulation mode, the scoring board module is connected with the second monitoring module and used for comparing the simulation result with the desired result and outputting warning information when the simulation result is inconsistent with the desired result, the running environment in the stimulus generation environment is configured in the verified equipment, the first monitoring module is used for receiving the configuration of the MCU in the random simulation process, the first monitoring module is connected with the software constraint module, and the software is used for calling the software constraint and is added in the storage space to the MCU to store the random constraint software.
Preferably, the hardware environment further comprises an external excitation module, which is connected with the random excitation generating module and the first monitoring module and is used for acquiring external excitation when the MCU needs at least two random excitation for configuration, restraining the external excitation by the random excitation and sending the restrained external excitation to the MCU.
Preferably, the first monitoring module further comprises a re-random unit for driving the random stimulus generation module to regenerate the random stimulus stored in the storage space when the random stimulus is called, and a re-write unit for monitoring the storage space and re-writing the generated random stimulus storage into the storage space when the storage space data is lost.
The technical scheme has the following advantages or beneficial effects:
1. By generating random stimuli based on random variables and hardware constraints in a hardware environment, various complex MCU operating scenarios can be more flexibly simulated. Various possible time sequence relations can be simulated, so that the verification process can cover more scenes and conditions, and the comprehensiveness of verification is improved. Thereby greatly enhancing the randomization capability.
2. The MCU verification platform can be compatible with any existing MCU verification platform, cannot influence the existing verification environment, and only expands the functions of the existing verification environment.
Drawings
FIG. 1 is a flow chart of a system level random verification method of a universal MCU verification platform in a preferred embodiment of the invention;
FIG. 2 is a flow chart of step S1 in the preferred embodiment of the invention;
FIG. 3 is a schematic diagram of a system level random verification system of a general MCU verification platform according to a preferred embodiment of the present invention.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples. The present invention is not limited to the embodiment, and other embodiments may fall within the scope of the present invention as long as they conform to the gist of the present invention.
In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a system level random verification method of a general-purpose MCU verification platform is now provided, as shown in fig. 1, including a step S1 of generating random excitation based on random variables and hardware constraint conditions in a hardware environment and storing the random excitation in a verified device, a step S2 of the MCU of the verified device retrieving the stored random excitation and adding software constraint conditions, and then using the random excitation after the software constraint as a simulation result for random simulation, and a step S3 of reading the random excitation after the software constraint by the hardware environment to generate a desired result, and outputting warning information to complete random verification when comparing the desired result with the simulation result is inconsistent.
Specifically, in this embodiment, in the random verification of the MCU, the random excitation refers to a random test vector or data packet generated by the simulation environment and used for testing the MCU function and performance. These random excitations are intended to simulate the various conditions that an MCU may encounter in practical applications to verify the performance and stability of the MCU in different scenarios.
In particular, the random stimulus may comprise various types of stimulus signals, such as a clock signal, a reset signal, a register configuration signal, a data input signal, and the like. These excitation signals are generated in a random manner in the simulation environment and act on the input end of the MCU according to a certain time sequence and logic relation. By observing and analyzing the output response of the MCU after receiving these random excitations, the verifier can evaluate the functional correctness, performance stability and ability to handle complex timing of the MCU.
In the random verification process, the generation of random stimulus is one of the key steps. To ensure the integrity and validity of the verification, the random stimulus needs to cover various conditions that the MCU may encounter, including normal operation, abnormal operation, boundary conditions, etc. Meanwhile, the generation of random excitation also needs to consider the characteristics and application scenes of the MCU so as to ensure that the generated excitation signals meet the actual working requirements of the MCU.
The random verification method in the embodiment can simulate various complex MCU working scenes more flexibly by generating random excitation based on random variables and hardware constraint conditions in a hardware environment. The random excitation not only considers the constraint of the hardware level, but also can carry out further customization and constraint on the software level, thereby greatly enhancing the randomization capability.
By introducing random excitation, various possible time sequence relations can be simulated, so that the verification process can cover more scenes and conditions, and the comprehensiveness of verification is improved.
For complex use scenarios, the actual use situation can be more accurately simulated by combining random excitation of hardware and software layers. This helps to find potential problems and defects, improving the reliability and stability of the MCU.
The MCU verification platform can be compatible with any existing MCU verification platform, cannot influence the existing verification environment, and only expands the functions of the existing verification environment. Meanwhile, the original verification case cannot be influenced, the case cannot be increased, and the workload of verification personnel cannot be increased. Meanwhile, a simple method is provided for verification points of protocol classes, time sequences and the like which need a large number of verification cases.
Further, in the preferred embodiment of the present invention, the random stimulus is generated by step S1, as shown in FIG. 2, step S1 includes step S11 of generating an initial random stimulus according to a random variable in a hardware environment, step S12 of performing range limitation on the initial random stimulus according to a hardware constraint condition in the hardware environment, and or performing constraint on numerical elimination to obtain a random stimulus and store the random stimulus in a verified device.
Specifically, in this embodiment, the clock source is selected as a random variable for example:
step S11 generating an initial random stimulus (clock source based selection)
And core logic for encoding the clock configuration parameters in the random number to generate the original 32-bit numerical value.
1. Definition random variable field (32 bit structure)
Clock source selection (4 bit)
0X0 HRC (64 MHz inside)
0X1 HSE (external 8 MHz)
0X2 LSE (internal 30 KHZ)
0X3 LRC (external 32.768 KHZ)
0X4 PLL (phase locked loop output)
Other values of HRC
PLL frequency multiplication coefficient (4 bits):
AHB division factor (4 bits):
Random values 0x0 (not divided), 0x1 (divided by 2), 0x2 (divided by 4), 0x3 (divided by 8)
2. Generating an initial random number (example)
A 32-bit value is generated using a simulated environment random engine (seed=0x5a3d):
0x42A30000 (binary 0100 0010 1010 0011 0000 0000 0000 0000)
Parsing field:
Clock source selection 0100 (bits 31-28→0x4, corresponding to PLL)
PLL frequency multiplication coefficient 0010 (bits 27-24→value 0x2, frequency multiplication x 2)
AHB frequency division coefficient 1010 (bit 23-20→value 0xA, illegal)
Reserved bit of all 0
Step S12, apply hardware constraint correction
Only the illegal field is corrected, and the legal random value is reserved.
1. Clock source selection constraints
If the clock source field value (0 x0/0x1/0x 4) indicates a fast clock, the clock is normally divided. If the clock source field value (0 x2/0x 3) indicates a slow clock, the clock source field value may be selected to not divide, limit the size of the divide, or be replaced with other clocks according to actual requirements.
2. PLL frequency multiplication coefficient constraint
If the frequency multiplication coefficient <0x3→is set to the minimum value of 0x3 (×3)
If the multiplication factor >0xC→is set to the maximum value 0xC (×12)
In this example, the frequency multiplication factor is 0x2 (×2), and the correction is 0x3 (×3).
3. AHB frequency division coefficient constraint
Only 0x0/0x1/0x2/0x3 is allowed, other values are corrected by priority:
If the value is >0x3→taking the maximum legal value of 0x3 (frequency division by 8)
In this example, the division factor is 0xA (decimal 10), and is corrected to 0x3 (8 division).
4. Recoding legal values
Corrected field:
clock source selection 0100 (PLL)
PLL frequency multiplication coefficient 0011 (×3)
AHB frequency division coefficient 0011 (8 frequency division)
Reserved bit unchanged
Final legal incentive value:
0x43330000 (binary 0100 0011 0011 0011 0000 0000 0000 0000)
The random stimulus after the hardware constraint is stored in the memory space of the verified device, and this memory space is usually referred to as the memory space inside the MCU.
In a preferred embodiment of the present invention, after executing the step S1, a stimulus monitoring procedure is further included, including that the hardware environment monitors the random stimulus stored in the verified device, and when the random stimulus is invoked, the step S1 is executed again to regenerate the random stimulus for storing in the verified device.
Specifically, in this embodiment, when the random stimulus in the verified device is invoked, the hardware environment can regenerate the random stimulus and store it to the verified device. This ensures a real-time update of the random stimulus, consistent with the current state of the device being verified, thereby improving the accuracy of the verification.
By regenerating when the random stimulus is invoked, changes in the state of the verified device that may occur during the simulation process can be countered. This enhances the robustness of the verification, making the verification process more reflective of the complexity of the actual use case.
In some complex scenarios, the state of the verified device may change due to a variety of factors. Step S13 allows regeneration each time a random stimulus is invoked, so that these complex scenarios can be simulated, ensuring the integrity and reliability of the verification.
In a preferred embodiment of the invention, for system level verification of an MCU, a verified device (MCU) has a memory space, the random stimulus is stored in the memory space and is fetched when in use, and the method further comprises a stimulus rewriting process after the step S1 is executed, wherein the hardware environment monitors the memory space, and the generated random stimulus memory is rewritten into the memory space when the data of the memory space is lost.
Specifically, in this embodiment, the state of the data in the storage space is also monitored in real time, and when the data in the random access memory module is lost due to power failure or a low power consumption mode in the simulation, the random access memory module needs to be written again in time. The integrity of the data in the storage space can be ensured.
This is critical to the accuracy and reliability of the verification process, as any loss of data may result in a deviation or failure of the verification result.
It can be ensured that the verification process can continue seamlessly after the device has been restored to normal. This avoids interrupting the verification flow due to data loss, improving the continuity and efficiency of verification.
In the preferred embodiment of the invention, each simulation result is associated with a piece of log information, the time in the hardware environment is used as a random variable, and when each simulation result is obtained, the corresponding random variable is recorded in the associated log information.
Specifically, the script in the verification environment is required to support the transmission of the random seed (namely, the random variable in the step S1) to the verification environment before the establishment of the random excitation generation environment, generally, the set time is the transmitted random seed, because the time in the simulation environment is always changed, different random seeds can be ensured each time, meanwhile, seed information is added when log information of a simulation result is saved, when the verification case in the random environment is completed, regression test is performed, and the log information and the random seed can save complete regression information, so that the problem is solved conveniently.
In a preferred embodiment of the invention, the random simulation process is that the MCU is configured according to random excitation, and after the configuration is completed, a pre-written function is executed in the MCU to obtain a corresponding simulation result.
Specifically, the random stimulus generation environment is divided into a hardware environment and a software environment, the software environment is configured in the MCU of the device to be verified, and the software environment is essentially a function program for reading the random stimulus. When the program knows the random excitation, the corresponding configuration can be performed.
In the preferred embodiment of the invention, the MCU needs at least two random excitation to be configured, in the step S1, the hardware environment further acquires external excitation after generating the random excitation, the random excitation and the external excitation are stored in the MCU, and the MCU is configured according to the random excitation and the external excitation in the random simulation process.
Specifically, in some cases, the MCU needs at least two random excitations to perform configuration, at this time, simulation verification cannot be performed only by means of one random excitation generated by a hardware environment, at this time, an external excitation is needed, and the external excitation is matched with the random excitation. The external stimulus is used as an input signal to drive the device under test (Device Under Test, DUT for short) into the desired operating state. This is the starting point for simulation verification, and by applying appropriate stimulus signals, the logic and circuitry within the DUT can be triggered to begin operation and produce a corresponding output.
The external stimulus may be designed to cover a variety of possible test scenarios, including normal operation, boundary conditions, abnormal situations, and the like. This ensures that the integrity of the simulation verification is ensured, covering as much of the DUT's potential behavior as possible, thereby increasing the confidence of the verification.
The invention further provides a random verification system of the universal MCU verification platform, which is applied to the random verification method, as shown in fig. 3, and comprises an excitation generation environment ENV and a verified device DUT, wherein the hardware environment in the excitation generation environment comprises a random excitation generation module, a first monitoring module, an expected generation module, a score board module and a second monitoring module, wherein the random excitation generation module is used for generating random excitation according to random variables and hardware constraint conditions and storing the random excitation in a storage space of the verified device, the first monitoring module is used for monitoring the configuration of an MCU of the verified device in a random simulation process and monitoring the random excitation in the storage space, the expected generation module is connected with the first monitoring module and is used for receiving the configuration sent by the first monitoring module and generating a corresponding expected result, the second monitoring module is used for monitoring the simulation result generated by the MCU random simulation, the score board module is connected with the expected generation module and the second monitoring module and is used for comparing the simulation result and the expected result, and outputting warning information to complete the random verification when the simulation result and the expected result are inconsistent, and the running environment in the excitation generation environment is configured in the MCU of the verified device.
In a preferred embodiment of the present invention, as shown in fig. 3, the hardware environment further includes an external excitation module, connected to the random excitation generating module and the first monitoring module, configured to obtain external excitation when the MCU needs at least two random excitations for configuration, and to constrain the external excitation by the random excitation, and send the constrained external excitation to the MCU.
Preferably, the first monitoring module further comprises a re-random unit for driving the random stimulus generation module to regenerate the random stimulus stored in the storage space when the random stimulus is invoked, and a re-write unit for monitoring the storage space and re-writing the generated random stimulus storage into the storage space when the storage space data is lost.
Specifically, in this embodiment, a specific structure diagram of the random excitation generating environment is shown in fig. 3, and the building can be performed according to the structure shown in fig. 3 when the environment is built.
Firstly, constructing a rand config module (random excitation generation module), wherein the construction of the module is to generate random numbers based on random variables according to actual random requirements, and set constraints. In simple applications, the configuration is not complex, and when the constraint to be paid next is a random result of this time, special attention is required in building. The rand config module is also driven by the first monitoring module, and a new random stimulus needs to be generated every time the signal is driven.
The inspirt module (external excitation module) controls the external excitation of the MCU, and its constraint is usually derived from the random result of the rand config module, and the inspirt module generates external excitation for the MCU according to the result of the rand config module. When the random result of the rand config module changes, the actuation controlled by the inspirt module will also change.
The monitor1 module (first monitoring module) is mainly used for monitoring random excitation inside the MCU and monitoring a configuration process, and when the random excitation is used, the random config module is driven to carry out random operation again. In addition, it is also necessary to monitor the state of the memory bank (i.e., memory space), which is the place for storing random stimuli, and it is necessary to select it according to the actual use context.
When the chip simulates low power consumption or power failure, data in the memory bank may be destroyed, and when destroyed, an instruction needs to be sent to enable the rand config module to put the data into the memory bank module again.
The REFERENCE MODEL module (expected generation module) is a built accompanying model, and is mainly used for receiving the configuration transmitted by the monitor1 module, generating expected results and transmitting the expected results to the scoreboard module.
The monitor2 module (second monitoring module) is used for monitoring design behaviors, when the configuration is changed, the MCU can generate different behaviors, the monitor2 module can monitor the behaviors, and the recorded simulation result is transmitted to the scoreboard module.
The scoreboard module (score board module) is used for receiving the expected result from the REFERENCE MODEL module and the simulation result of the monitor2 module in real time, comparing the results, and printing out warning information when the expected result conflicts with the actual simulation result.
The role of the reconstraint module (reconstraction module) is to reconstract again, which is needed when building a general-purpose environment, for example when GPIO (GPIO is an input-output interface between a chip and an external device, available for simple state-reading and control switches) or PADCFG module (PADCFG module is typically used for configuration and management of GPIO ports) invokes a random environment in which there is an incentive for an MCU. However, GPIO or PADCFG simulation may not be desirable to stimulate the MCU, and the effect of the restint module is to restrict the random environment from stimulating the MCU. Of course, the role of the restint module is not limited to this, and it should be noted that the constraint of the restint module is only declared once, and is valid in the whole simulation process.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations herein, which should be included in the scope of the present invention.
Claims (9)
1. A system level random verification method for a universal MCU verification platform, comprising:
Step S1, generating random excitation based on random variables and hardware constraint conditions in a hardware environment and storing the random excitation into verified equipment;
step S2, the MCU of the verified equipment invokes the stored random excitation and adds software constraint conditions, and then the random excitation after the software constraint is used as a random simulation to obtain a simulation result;
S3, the hardware environment reads the random excitation after the software constraint to generate an expected result, and when the expected result is compared with the simulation result, warning information is output to complete random verification;
the step S1 includes:
step S11, generating initial random excitation according to the random variable in the hardware environment;
And step S12, limiting the range of the initial random stimulus according to the hardware constraint condition in the hardware environment, and/or performing numerical elimination to complete constraint to obtain the random stimulus and store the random stimulus to the verified device.
2. A random verification method according to claim 1, further comprising an incentive monitoring procedure after performing said step S1, comprising:
The hardware environment monitors the random stimulus stored in the verified device, and when the random stimulus is called, the step S1 is executed again to regenerate the random stimulus to be stored in the verified device.
3. A random verification method according to claim 1, wherein a storage space is provided in the verified device, the random stimulus being stored in the storage space, and further comprising a stimulus rewrite process after performing the step S1, comprising:
And the hardware environment monitors the storage space, and when the data in the storage space is lost, the generated random excitation storage is written into the storage space again.
4. The random verification method according to claim 1, wherein each simulation result is associated with a piece of log information, and time in the hardware environment is taken as the random variable;
and recording the corresponding random variable in the associated log information when the simulation result is obtained each time.
5. The random verification method according to claim 1, wherein the random simulation process in step S2 is configured for the MCU according to the random excitation, and after the configuration is completed, a pre-written function is executed in the MCU to obtain a corresponding simulation result.
6. The random verification method according to claim 5, wherein the MCU is configured with at least two random stimuli, wherein in the step S1, the hardware environment further acquires external stimuli after generating the random stimuli, the random stimuli and the external stimuli are stored in the verified device, and wherein in the random simulation process the MCU is configured according to the random stimuli and the external stimuli.
7. A system level random verification system of a universal MCU verification platform, characterized by applying a random verification method according to any of claims 1-6, comprising a stimulus generating environment and a verified device;
The hardware environment in the stimulus generation environment includes:
a random stimulus generation module for generating the random stimulus according to the random variable and the hardware constraint condition, and storing the random stimulus in a storage space of the verified device;
The first monitoring module is used for monitoring the configuration of the MCU of the verified equipment in a random simulation process and monitoring the random excitation in the storage space;
The expected generation module is connected with the first monitoring module and is used for receiving the configuration sent by the first monitoring module and generating the corresponding expected result;
The second monitoring module is used for monitoring a simulation result generated by the MCU random simulation;
The score board module is connected with the expected generation module and the second monitoring module and is used for comparing the simulation result with the expected result and outputting warning information when the simulation result is inconsistent with the expected result so as to complete random verification;
The operation environment in the stimulus generation environment is configured in the MCU of the verified device, and comprises:
and the software constraint module is connected with the storage space and is used for calling the random excitation in the storage space and adding software constraint, and the MCU is configured according to the random excitation after the software constraint.
8. A random verification system according to claim 7, wherein said hardware environment further comprises
The external excitation module is connected with the random excitation generation module and the first monitoring module and is used for acquiring external excitation when the MCU needs at least two random excitation to be configured, restraining the external excitation by the random excitation and sending the restrained external excitation to the MCU.
9. The random access verification system of claim 7, wherein the first monitoring module further comprises:
A re-random unit for driving the random stimulus generation module to regenerate the random stimulus stored in the memory space when the random stimulus is invoked, and
And the re-writing unit is used for monitoring the storage space, and re-writing the generated random excitation storage into the storage space when the data in the storage space is lost.
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