CN105205249B - A kind of SOC debugging verification systems and its software-hardware synergism method - Google Patents

Abstract

The invention discloses a SOC (System On Chip) debugging verification system, which includes a SOC chip and a verification platform, the SOC chip includes a processor, a memory, and a software test case stored in the memory, and the verification platform includes a hardware test case. On the basis of the existing technology, a debugging module is added to the SOC chip to be verified, and the software access address of the debugging module is allocated to an address segment that is not used in the system, and the register array and hardware in the debugging module are read and written through software test cases The test case writes and reads the register array in the debugging module to realize the interactive communication between the software test case and the hardware test case to complete the verification of the SOC chip. The invention also proposes a software and hardware coordination method of the SOC debugging verification system. Through the invention, the software test case and the hardware test case can communicate with each other during the debugging and verification process of the SOC chip, thereby reducing the number of simulation times and improving efficiency.

Description

A SOC debugging and verification system and its software and hardware coordination method

technical field

The invention relates to the field of integrated circuit verification and testing, in particular to a method for stimulating interaction between software and hardware in SOC system verification and an SOC debugging and verification system for realizing the method.

Background technique

With the rapid development of the integrated circuit industry, more and more chips are designed as SOC (System On Chip) chips. With the increasing scale of SOC chips, the verification of SOC chips is becoming more and more difficult. The SOC debugging and verification system generally uses electronic design automation (Electronic Design Automation, EDA) tools to simulate and verify the SOC chip to ensure the correctness of the SOC chip design. SOC system verification incentives (test cases) are generally divided into two parts: software incentives (software test cases) and hardware incentives (hardware test cases). Software incentives are coded by C, C++ and other software languages, compiled by a compiler to generate executable files, stored in the memory of the SOC chip, and then the central processing unit (Central Processor Unit, CPU) of the SOC chip reads instructions from the memory and Execute to complete the function designed by the SOC chip. Hardware incentives are coded by hardware description languages such as Verilog, VHDL, and SystemVerilog or hardware verification languages. They are located in the system verification platform and are used to build the application environment of the SOC chip or directly modify the internal hardware signals of the SOC chip design to make the SOC chip meet the desired working conditions. The software stimulus and hardware stimulus work together to realize the system verification of the SOC chip in a certain application environment to complete a certain functional operation.

However, the existing software incentives and hardware incentives have the following problems in the process of coordination:

1. Increase the number of simulation debugging: Since neither the software stimulus nor the hardware stimulus knows the status of the other, it takes multiple debugging to determine the scenario where both are satisfied.

2. Increase the simulation running time: In order to ensure that the software incentives or hardware incentives are fully prepared, delays that exceed actual requirements will be added to the incentives.

3. Few functional points are covered by a single simulation: Both software and hardware incentives do not know whether the other party has finished running. One simulation can only cover part of the functions in a certain application environment. To cover more functions, re-simulation verification is required.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention proposes a SOC debugging and verification system, which is mainly used in the process of using EDA tools to simulate and verify SOC chips. It includes a SOC chip and a verification platform. The SOC chip includes a processor, a memory, and a software test case stored in the memory. The verification platform includes a hardware test case. A debugging module is also set in the SOC chip. The software test case and the hardware test case complete the verification of the SOC chip through the interactive communication of the debugging module during the running process.

The present invention also proposes a software-hardware coordination method of the above-mentioned SOC debugging and verification system, comprising the following steps:

Step 1: The software test case drives the processor of the SOC chip to write A to the register in the debugging module through the system bus of the SOC chip. After this step is executed successfully, the value of the register in the debugging module is equal to A;

Step 2: The hardware test case monitors the value of the register, and judges whether the value of the register is equal to A, if it is not equal to A, then continue monitoring, if it is equal to A, then continue to step 3;

Step 3: The hardware test case determines that the software test case is currently ready, and the hardware test case begins to construct the hardware application environment or working conditions for the next operation of the SOC chip;

Step 4: After the current hardware application environment or working conditions of the hardware test case are constructed, modify the value of the register to B;

Step 5: The software test case drives the processor to monitor the value of the register in the debugging module through the system bus, and judges whether the register value is equal to B, if not equal to B, then continue monitoring, if it is equal to B, then continue to step 6;

Step 6: The software test case determines that the hardware test case is ready for the current hardware application environment or working conditions, and the software test case starts the next operation;

Step 7: Repeat steps 1 to 6 until the software test cases and hardware test cases cooperate with each other to complete all the debugging and verification work.

The values A and B in the above steps 1-6 are arbitrary values. The current A and B values can be the same as or different from the A and B values in the previous cycle. The registers where the current A and B values are stored are the same as those in the previous cycle. The registers where the values of A and B exist may be the same or different.

This application adds a debugging module to the SOC chip that can be accessed simultaneously by the software stimulus and the hardware stimulus, so that the software stimulus and the hardware stimulus can communicate with each other in the collaborative process, thereby reducing the number of times of SOC system verification simulation debugging and shortening the time. The simulation running time increases the function points covered by a single simulation, which helps to improve the verification efficiency of the SOC system, and does not increase the scale of the SOC chip design, and does not affect the design function of the SOC chip at all.

Description of drawings

Fig. 1 is a structural representation of the present invention;

Fig. 2 is the structural representation of debugging module of the present invention;

Fig. 3 is a flow chart of software and hardware cooperation in the present invention.

Detailed ways

The working process of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

As shown in Figure 1, the SOC debugging and verification system proposed by an embodiment of the present invention includes a SOC chip 101 and a verification platform 106. The SOC chip includes a processor 103 and a memory 104, and the memory 104 stores software test cases, also called software incentives. 105. The software incentive 105 is coded by software languages such as C and C++, and compiled by a compiler to generate an executable file. The processor 103 can read instructions from the memory 104 and execute them to drive the SOC chip 101 to realize the designed functions.

The verification platform 106 is made up of a hardware stimulus 107 (also called a hardware test case) and a monitor 108. The verification platform 106 is built by the hardware description language Verilog or VHDL or the hardware verification language SystemVerilog. In the verification platform 106, all signals or The register is a fully visible specific signal or unit to the hardware stimulus 107 and the monitor 108, so the hardware stimulus 107 can directly monitor or modify the internal signal or register value of the SOC chip 101, and the monitor 108 can directly monitor the internal signal of the SOC chip 101 or register value. The hardware stimulus 107 constructs the application environment or working conditions of the SOC chip 101 by modifying the values of signals or registers inside the SOC chip 101 . The monitor 108 judges whether the SOC chip 101 is working correctly by checking whether the internal signals or register values of the SOC chip 101 meet expectations.

The SOC chip 101 is the object to be verified. In order to realize the mutual collaboration and mutual communication interaction of the software and hardware test cases proposed by the present invention, in the system verification stage, a debugging module 102 is added to the SOC chip 101, and the software access address of the debugging module 102 It is allocated to an address area not used in the SOC chip 101 system. The debugging module 102 is only used in the system verification stage, and does not exist in actual chip products. The software test case and the hardware test case complete the verification of the SOC chip through the interactive communication of the debugging module during the running process.

As shown in FIG. 2 , the debugging module 201 is a submodule of the SOC chip 101 and is integrated on the system bus of the SOC chip 101 . The debugging module 201 is composed of a bus interface 202 , a bus access analysis unit 203 and a register array 204 . The bus interface 202 adopts the system bus interface of the SOC chip 101 , and the bus access analysis unit 203 converts the access timing of the bus interface 202 into the access timing of the register array 204 . There is at least one register in the register array in the debugging module, and any number of registers can be set as required, and generally about 10 registers are needed to complete the debugging verification of the SOC chip.

The software stimulus 105 drives the processor 103 to read and write the register array in the debugging module 102 through the system bus of the SOC chip 101, and the hardware stimulus 107 in the verification platform 106 can read and write the register array in the debugging module 102. The registers of the software stimulus 105 and the hardware stimulus 107 can be jointly accessed, and the registers in the debugging module 102 can be used to realize the interactive communication between the software stimulus 105 and the hardware stimulus 107.

As shown in Figure 3, the present invention also proposes the collaborative method of the software and hardware of SOC debug verification system, and it mainly is the interactive collaboration between hardware test case and software test case to complete the debug verification of SOC chip, comprises the following steps:

Step 1: The software test case drives the processor of the SOC chip to write A into the register 0 in the debugging module through the system bus of the SOC chip. After this step is executed successfully, the value of the register 0 in the debugging module is equal to A;

Step 2: The hardware test case monitors the value of register 0, and judges whether the value of register 0 is equal to A, if it is not equal to A, then continue monitoring, if it is equal to A, then continue to step 3;

Step 3: The hardware test case determines that the software test case is currently ready, and the hardware test case begins to construct the hardware application environment or working conditions for the next operation of the SOC chip;

Step 4: After the current hardware application environment or working conditions of the hardware test case are constructed, modify the value of register 0 to B;

Step 5: The software test case drives the processor to monitor the value of register 0 in the debugging module through the system bus, and judge whether the value of register 0 is equal to B, if it is not equal to B, then continue monitoring, if it is equal to B, then continue to step 6;

Step 6: The software test case determines that the hardware test case is ready for the current hardware application environment or working conditions, and the software test case starts the next operation;

Step 7: Determine whether the debugging and verification of the SOC chip is completed, and if so, end; otherwise, loop steps 1 to 6 until the software test case and the hardware test case cooperate to complete all the debugging and verification work.

The values A and B in the above steps 1-6 are arbitrary values. The current A and B values can be the same as or different from the A and B values in the previous cycle. The registers where the current A and B values are stored are the same as those in the previous cycle. The registers where the values of A and B exist may be the same or different. The above steps 1 to 6 are just a flow of information interaction between the software stimulus 105 and the hardware stimulus 107 based on a specific register in the debugging module 102. If there are more information to be exchanged between the software stimulus 105 and the hardware stimulus 107, It can be realized by using other registers in the debugging module 102, and the process of using other registers for interaction is the same as when using register 0, and the verifier can implement the step 7 in the Repeat step 1 to step 6.

It should be understood that the above descriptions for specific embodiments are relatively detailed, and should not be considered as limiting the scope of the patent protection of the present invention, and the scope of protection of the patent protection of the present invention should be determined by the appended claims.

Claims (6)

1. a kind of SOC debugging verification systems, including SOC chip and verification platform, the SOC chip include processor, memory, The software test case being stored in memory, the verification platform include hardware testing use-case, which is characterized in that the SOC A debugging module is also provided in chip, the software test case and hardware testing use-case pass through debugging in the process of running Module interacts communication to complete the verification to SOC chip；

The debugging module includes the bus interface being connected with the system bus of SOC chip, the bus being connect with bus interface Access resolution unit, for the register array of software test case and hardware testing use-case read and write access；

In verification, the processor of software test case driving SOC chip is by the system bus of SOC chip to debugging mould A value is written in register in the block, when the value of hardware testing use-case control register is correct, then hardware testing use-case starts The hardware adaptations environment or operating condition that SOC chip operates in next step are built, the value of register is revised as separately after the completion of structure One value, then judge whether the value in register is correct by software test case, if correctly, then continuing next round test case Verification, until all debugging verify work finish.

2. SOC debugging verification systems as described in claim 1, which is characterized in that the register in the register array Number is at least one.

3. SOC debugging verification systems as described in claim 1, which is characterized in that the software test case is by debugging mould Softward interview address after block mapping is written and read access to debugging module.

4. SOC debugging verification systems as claimed in claim 3, which is characterized in that the software after the debugging module mapping is visited Ask not used address in the system that address is SOC chip.

5. SOC debugging verification systems as described in claim 1, which is characterized in that the verification platform further includes for checking Whether signal or register value inside SOC chip match preset value to judge monitor that whether SOC chip correctly works.

6. the software-hardware synergism method of the SOC debugging verification systems as described in claim 1 to 5 any one claim, It is characterized in that, includes the following steps：

Step 1：The processor of software test case driving SOC chip is by the system bus of SOC chip into debugging module A is written in register, after which runs succeeded, the value of the register in debugging module is equal to A；

Step 2：The value of hardware testing use-case control register, judges whether the value of the register is equal to A, if being not equal to A, Continue to monitor, if being equal to A, continues step 3；

Step 3：Hardware testing use-case determines that software test case is currently ready, and hardware testing use-case starts to build SOC cores The hardware adaptations environment or operating condition of under piece single stepping；

Step 4：After the completion of the current hardware adaptations environment of hardware testing use-case or operating condition structure, the value of register is changed For B；

Step 5：Software test case drives processor to judge to post by the value of the register in system bus monitoring debugging module Whether storage value is equal to B, if being not equal to B, continues to monitor, if being equal to B, continues step 6；

Step 6：Software test case determines that hardware testing use-case is already prepared to current hardware adaptations environment or operating condition, Software test case starts the operation of next step；

Step 7：Circulation step 1 to 6, until the debugging that software test case and hardware testing use-case mutually cooperate with completion all is tested Demonstrate,prove work；

Value A, B in above-mentioned steps 1-6 is arbitrary value, and current A, B value and A, B value in cyclic process before can be identical or not Together, the register of current A, B value storage may be the same or different with the register present in A, B value in cyclic process before.