CN1255963C - Demodulation timing generation circuit and demodulation device - Google Patents

Abstract

A demodulation timing generating circuit capable of correctly generating a timing for demodulating a received signal with high accuracy even under various reception conditions, and a demodulating apparatus using the demodulation timing generating circuit, wherein a synchronous training signal (burst signal) added to the head of the received signal (packet) is used, the burst detector (109) and an amplification gain controller (111) perform AGC control and frequency offset correction, a detection window period for cross-correlation detection is provided, a peak value of the cross-correlation in the detection window is detected by the timing controller (110), and data corresponding to the peak position is loaded into the counter (11003) for counting the OFDM symbol interval. By this design, it is possible to set an optimum FFT timing regardless of one channel state.

Description

Demodulation timing generation circuit and demodulation device

technical field

The present invention relates to a demodulation timing generation circuit and a demodulation device for a receiver of a wireless communication system, and more particularly to a demodulation device for receiving signals modulated by, for example, an Orthogonal Frequency Division Multiplexing (OFDM) modulation method and including burst pulses. A demodulation timing generating circuit and a demodulation device of a wireless communication system such as a burst signal including a preamble signal at the head of a packet signal modulated here.

Background technique

The OFDM modulation method is a modulation method that performs Fourier inverse transform on signal symbols transmitted by 2n basic modulation (QPSK, 16ASAM, etc.) to form 2 ⁿ subcarriers that are orthogonal to each other on the frequency axis.

In a wireless communication system employing such an OFDM modulation system, a transmitter serial-to-parallel converts transmission data, and performs Inverse Fast Fourier Transform (IFFT) on the converted data to collectively modulate the plurality of subcarriers that are orthogonal to each other.

On the transmitting side, a burst signal called a preamble serving as a synchronization training signal is added to the head of a modulated signal having a frame structure subjected to such IFFT processing, and the modulated signal is transmitted.

Subsequently, on the receiving side, processes such as automatic gain control (AGC), frequency offset correction, and FFT (Fast Fourier Transform) timing generation are performed using the preamble signal, thereby performing FFT operations based on the generated FFT timing.

Note that in a receiver of a wireless communication system, since the received signal level needs to be adjusted within the dynamic range of the A/D converter, the receiver is equipped with an AGC circuit as a function for adjusting the received signal level to the A/D converter. /D converter within the dynamic range of the circuit.

The AGC circuit synchronizes a timing to within one period of the burst signal while controlling the amplification gain in accordance with the reception level of the burst signal.

Also, in a receiver of a wireless communication system employing the OFDM demodulation method, it is necessary to optimize timing for performing FFT processing on one received symbol.

This is because the offset of the FFT timing will cause inter-symbol interference (ISI) or symbol rotation, thus causing deterioration of reception performance.

This FFT timing is set by using the above-described burst signal (training signal) called a preamble, which is appended to the head of the transmission data.

In the past, using autocorrelation or cross-correlation circuits, the FFT timing was set according to the point at which the correlation result exceeded the threshold of the preamble.

Note that this autocorrelation is used to find the correlation between repetitive signals included in the preamble section.

Cross-correlation, on the other hand, is used to obtain the correlation between a pre-known data sequence and an input data sequence.

In general, this autocorrelation is not affected much by reflections and fading, but has the weakness of exhibiting a correlation between even-numbered data and noise rather than preambles.

On the other hand, cross-correlation does not detect the correlation of noise and irrelevant data, but the peak value of the correlation tends to become small when there is a large shift in the received frequency and when the received wave is changed due to reflection and fading.

In this way, since auto-correlation and cross-correlation are affected by factors such as channel reflection, S/N, etc., there is a disadvantage in the above-described method of using this threshold to generate FFT timing that it must be set under various transmission conditions Low thresholds that can be shared and difficult to detect precise timing.

Also, among wireless LAN systems that use 5 GHz latest standardization, Time Division Multiple Access (TDMA) is employed in Wireless 1394 and HiperLAN/2.

In this TDMA wireless communication system, frame synchronization is the most basic option, but it has the following problems:

(1) In wireless communication, due to the influence of the channel state such as occurrence of the above-mentioned attenuation, it is not possible to always detect the synchronization of each frame.

(2) In the above-mentioned 5GHz system, in order to realize the low cost of the system, the high-precision crystal oscillator TCXO with temperature compensation is not used, but a crystal is used. For this reason, the reference frequency offset between the base station and the mobile station becomes 40 ppm at the maximum. This means there is a frequency shift of 4 clock cycles in 100000 clock cycles. Depending on the frame period, frame synchronization will easily be lost if this offset is not corrected well.

(3) If frame synchronization is lost, more than usual number of frames will need to acquire other synchronizations. During this period, the transfer of large amounts of data will be interrupted.

In the best systems, retransmission of data will be achieved, however if it is desired to guarantee a certain level of QoS (Quality of Service) this will be a fatal problem.

(4) In the Wireless 1394 system, due to the connection through the Wireless 1394, synchronization with a system with a large offset (100ppm) is required, and a frame synchronization system with good compliance is required.

Reference Document 1 (JP-A-2001-156743) discloses a communication system and a receiving device that transmit OFDM modulated signals using a plurality of types of synchronization signals to improve synchronization detection accuracy and optimize demodulation timing. In the transmission signal, a frame synchronization signal is arranged for each frame, a packet synchronization signal is arranged for each time slot in a reserved area, and a packet synchronization signal is arranged for each transmission block in an unreserved area. The receiving device detects the frame synchronization signal with a frame synchronization detection circuit to maintain frame synchronization, and the packet synchronization detection circuit roughly adjusts the demodulation timing according to the count value of the frame counter, detects the packet synchronization signal located in each time slot, and controls the demodulation timing with high precision Since the demodulation timing is controlled based on the detected packet synchronization signal in the non-reserved area, it is possible to optimize the demodulation timing and reduce the error rate of demodulated data.

Comparative Document 2 (JP-A-10-98438) discloses the following burst signal receiving device, which can improve the reliability and stability of burst signal detection after channel switching. When the control unit controls the frequency selection unit to switch the reception frequency (channel), based on the output level of the amplification unit detected by the reception power detection unit, the gain correction data for correcting the current gain of the gain control unit is obtained, so that Make said level the optimum wait level. When the detection signal of the burst signal is not input from the burst signal detection unit, the gain correction data is input to the gain control unit. The gain control unit corrects the gain currently supplied to the amplifying unit based on the gain correction data so that the output level of the gain unit becomes the optimum waiting level.

Contents of the invention

A first object of the present invention is to provide a demodulation timing generating circuit capable of correctly generating timing for demodulating a received signal with high precision even under various reception conditions, and a device using the demodulation timing generating circuit Demodulation device.

A second object of the present invention is to provide a highly adaptable and stable demodulation timing generation circuit capable of stably and continuously maintaining the established frame synchronization and avoiding data transmission/reception under conditions in which the channel state is unstable interrupt, and a demodulation device using the demodulation timing generation circuit.

The present invention provides a demodulation timing generating circuit for generating a timing signal for initiating demodulation of a received signal having a frame synchronization signal added to a header portion of a data symbol, a burst portion of which is used as a synchronization training signal, the circuit comprising: a burst detector for performing a correlation operation in the burst portion of the frame synchronization signal; a peak detection circuit for performing a peak correlation power by the burst detection unit detect, detect a peak in a detection window centered around an expected timing and exceed a detection threshold, and output a signal indicative of an offset between the expected timing and the peak detection position; a frame period counter for counting by a reference clock a frame period whose counter uses the set count as an operation period, generates window timing for instructing the detection window of the peak detection circuit based on the operation period, and instructs output of the timing signal at timing according to expected timing based on the set count an average value circuit for averaging a deviation between a result of peak detection of frame synchronization of the peak detection circuit and an expected timing of synchronization detection of the frame period counter, and outputting the average result as a correction value; and a correction value A setting circuit for setting a period of correction of the correction value of the average value circuit as a count value to the frame period counter.

The present invention also provides a demodulation apparatus for generating a timing signal for initiating demodulation of a received signal having a frame synchronization signal added to a header portion of a data symbol, the burst portion of which is used as a synchronization training signal, the demodulation device includes: a burst detector for performing correlation operations in the burst part of the frame synchronization signal; a peak detection circuit for performing correlation power by the burst detection unit Peak detection for detecting peaks only in a detection window centered around the expected timing and exceeding the detection threshold, and outputting a signal indicating the offset between the expected timing and the peak detection position; frame period counter for passing The reference clock counts the frame period, the counter of which uses the set count as an operation period, generates window timing for instructing the detection window of the peak detection circuit according to the operation period, and instructs the peak detection circuit at timing according to an expected timing counted based on the setting. an output of a timing signal; an average value circuit for averaging a deviation between a result of peak detection of frame synchronization of the peak detection circuit and an expected timing of synchronization detection of the frame period counter, and outputting the average result as a correction value a correction value setting circuit for setting a period corrected by the correction value of the average value circuit as a count value to the frame period counter; and a demodulation unit for performing Fourier transform on the received signal, and performing Fourier transform on the received signal according to the The received signal is demodulated when the received timing signal is commanded by the frame period counter output.

In order to achieve the above objects, according to a first aspect of the present invention, there is provided a demodulation timing generation circuit for generating a timing signal for starting demodulation of a received signal having a synchronization training signal added to a header portion of a data symbol. The burst portion of the signal, comprising: a burst detector, configured to perform a correlation operation in the burst portion of the received signal; a peak position detection unit, configured to set a detection window according to the correlation operation result and detect a peak value of the correlation power and a position of the peak value in a cycle of the detection window; and an output unit for outputting the timing signal at a predetermined time after the peak position detected by the peak position detection unit.

Also, in the first aspect of the present invention, the window width for detecting the peak of the correlation result is variable, and is set to a width according to reception conditions.

The peak position detection unit sets a lower limit of the correlation value to be detected, and when the correlation value is smaller than the lower limit, it is not considered that a peak has been detected.

Also, in the first aspect of the present invention, the burst detector performs a cross-correlation operation, and the peak position detection unit detects a peak value of cross-correlation power and the peak position.

In addition, in the first aspect of the present invention, the burst detector performs an autocorrelation operation and a cross-correlation operation, and the peak position detection unit sets a detection window according to the autocorrelation operation result and detects the peak value of the cross-correlation power and at the The position of this peak within the period of the detection window.

In a second aspect of the present invention, there is provided a demodulation timing generation circuit for generating a timing signal for initiating demodulation of a received signal having a burst serving as a synchronization training signal added to a header portion of a data symbol A pulse part, the circuit comprising: a burst detector for performing a correlation operation in the burst part of the received signal; a peak position detection unit for setting a detection window and detecting a correlation power according to the correlation operation result and the position of the peak value in the period of the detection window; a counter for counting symbol parts, and if the preset timing data value is counted, then output a timing signal; and a position timing conversion unit for converting and in the Timing data corresponding to the peak position detected by the peak position detection unit is preset to the counter.

Also, in the second aspect of the present invention, the position timing conversion unit generates timing data based on the relative relationship between the trailing edge of the detection window and the peak position, and presets the timing data to the counter.

Also, in the second aspect of the present invention, the peak position detection unit performs peak detection by comparing the previous output maximum value with the magnitude of the current correlation input, and stores the window timing in which the maximum value is obtained, so that finally The peak position is located at the end of the detection window.

Also, in the second aspect of the present invention, the counter periodically counts one symbol once preset and outputs the timing signal at a constant timing per symbol.

Also, in the second aspect of the present invention, the counter is a down counter; and the position timing switching unit changes the load data value of the counter after the counter has counted down to 0.

Also, in the second aspect of the present invention, the window width for detecting the peak of the correlation result is variable, and is set to a width according to reception conditions.

Also, in the second aspect of the present invention, the peak position detecting unit is set to a lower limit of the correlation value to be detected, and when the correlation value is smaller than the lower limit, the peak is not considered to have been detected.

Also, in the second aspect of the present invention, the burst detection unit performs a cross-correlation operation, and the peak position detection unit detects a peak value of cross-correlation power and a position of the peak value.

In addition, in the second aspect of the present invention, the burst detection unit performs an autocorrelation operation and a cross-correlation operation, and the peak position detection unit sets a detection window according to the autocorrelation operation result, and detects the peak value and the cross-correlation power of the cross-correlation power. The position of the peak within the detection window period.

In a third aspect of the present invention, there is provided a demodulation timing generating circuit for generating a timing signal for starting demodulation of a received signal having at least a preamble signal and following the A burst portion of a reference signal of a preamble, the circuit comprising: a burst detector for performing an autocorrelation operation on a preamble portion of a first half of the burst portion of the received signal, and performing an autocorrelation operation on a subsequent The reference signal part of the half part performs a cross-correlation operation; the peak position detection unit is used to set a detection window according to the autocorrelation operation result and detect the peak value of the cross-correlation power and the position of the peak value in the period of the detection window; and output A unit for outputting a timing signal at a predetermined time after the peak position detected by the peak position detection unit.

Also, in the third aspect of the present invention, the window width for detecting the peak value of the cross-correlation result is variable, and is set to a width according to reception conditions.

Also, in the third aspect of the present invention, the peak position detecting unit is set to a lower limit of the correlation value to be detected, and when the correlation value is smaller than the lower limit, the peak is not considered to have been detected.

In a fourth aspect of the present invention, there is provided a demodulation timing generating circuit for generating a timing signal for starting demodulation of a received signal having at least a preamble signal and following the A burst portion of a reference signal of a preamble, the circuit comprising: a burst detector for performing an autocorrelation operation on a preamble portion of a first half of the burst portion of the received signal, and performing an autocorrelation operation on a subsequent The reference signal part of the half part performs a cross-correlation operation; the peak position detection unit is used to set a detection window according to the autocorrelation operation result and detect the peak value of the cross-correlation power and the position of the peak value in the period of the detection window; the counter, for counting the symbol portion, and outputting a timing signal if a preset timing data value is counted; and a position timing converting unit for presetting timing data corresponding to the peak position detected by the peak position detecting unit to the counter.

Also, in the fourth aspect of the present invention, the position timing conversion unit generates timing data based on the relative relationship between the rear edge of the detection window and the peak position, and presets the timing data to the counter.

Also, in the fourth aspect of the present invention, the peak position detection unit performs peak detection by comparing the previous output maximum value with the magnitude of the current correlation input, and stores the timing of the detection window in which the maximum value is obtained, so that Finally, the peak position is located at the end of the detection window.

Also, in the fourth aspect of the present invention, the counter periodically counts one symbol once preset and outputs the timing signal at a constant timing per symbol.

Also, in the fourth aspect of the present invention, the counter is a down counter, and the position timing switching unit changes the load data value of the counter after the counter has counted down to 0.

Also, in the fourth aspect of the present invention, the window width for detecting the peak value of the cross-correlation result is variable, and is set to a width according to reception conditions.

Also, in the fourth aspect of the present invention, the peak position detecting unit is set to a lower limit of the cross-correlation value to be detected, and when the correlation value is smaller than the lower limit, the peak is not considered to have been detected.

In a fifth aspect of the present invention, there is provided a demodulation timing generating circuit for generating a timing signal for starting demodulation of a received signal having a frame synchronization signal added to a header portion of a data symbol, wherein the burst Sending pulse part is used as synchronous training signal, and this circuit comprises: burst pulse detector, is used for carrying out the relevant operation in this burst pulse part of this frame synchronous signal; Peak detection circuit, is used for detecting by this burst pulse The unit performs peak detection of the correlated power, detects a peak in a detection window centered around an expected timing and exceeds a detection threshold, and outputs a signal indicative of the offset between this expected timing and the peak detection position; a frame period counter, For counting the frame period by the reference clock, its counter uses the set count as the operation period, generates the window timing for instructing the detection window of the peak detection circuit according to the operation period, and the timing according to the expected timing counted based on the setting to instruct the output of the timing signal; an average value circuit for averaging the deviation between the peak detection result of the frame synchronization of the peak detection circuit and the expected timing of the synchronization detection of the frame period counter, and outputting the average result as a correction value; and a correction value setting circuit for setting a period of correction of the correction value of the averaging circuit as a count value to the frame period counter.

Moreover, in the fifth aspect of the present invention, when the peak detection circuit performs peak detection in the detection window and when its peak value does not exceed the detection threshold, it is judged that the correlation is not detected and the signal indicating the shift is not output. to the averaging circuit.

In addition, in the fifth aspect of the present invention, when the first frame synchronization is captured, the peak detection circuit detects the relevant peak in the state in which the detection window is always opened, and considers that the peak value first exceeds the threshold value. Sync detected.

In addition, in the fifth aspect of the present invention, the circuit further includes: a synchronization judging circuit for judging whether synchronization is detected when receiving the output signal of the peak detection circuit, and in a case where synchronization is detected, by the peak detection The output signal of the circuit sets the count value of the expected timing of synchronous detection of the frame period counter.

In addition, in the fifth aspect of the present invention, the average value circuit includes an integrating circuit, using the determined range of the upper bits (integer part) in the output as the first correction value, which is accumulated by the accumulating circuit and subtracted by each frame. The lower bit (fraction part) including the sign obtained by the upper bit, adds a second correction value to the first correction value corresponding to the transfer period, and outputs the result as a correction value to the correction value setting circuit.

Preferably the burst detector performs a cross-correlation operation on the reference signal portion of the second half of the burst portion of the received signal.

In a sixth aspect of the present invention, there is provided demodulation means for demodulating a received signal having a burst portion serving as a synchronization training signal added to a header portion of a data symbol, the demodulation means Including: a burst detector for performing a correlation operation in the burst part of the received signal; a peak position detection unit for setting a detection window according to the correlation operation result and detecting the peak value of the correlation power and the a position of a peak value in a cycle of the detection window; an output unit for outputting a timing signal at a predetermined time after the peak position detected by the peak position detection unit; and a demodulation unit for performing Fourier transform on the received signal, to demodulate the received signal upon receiving the output timing signal from the output unit.

In a seventh aspect of the present invention, there is provided demodulation means for demodulating a received signal having a burst portion serving as a synchronization training signal added to a header portion of a data symbol, the demodulation means Including: a burst detector for performing a correlation operation in the burst part of the received signal; a peak position detection unit for setting a detection window according to the correlation operation result and detecting the peak value of the correlation power and the the position of the peak value in the period of the detection window; the counter for counting the symbol part, and if counting the preset timing data value, then outputting the timing signal; the position timing conversion unit for converting the peak value detected by the peak position detection unit Timing data corresponding to the position is preset to the counter; and a demodulation unit for performing Fourier transform on the received signal to demodulate the received signal when receiving the outputted timing signal from the counter.

In an eighth aspect of the present invention, there is provided demodulation means for demodulating a received signal having at least a preamble signal and a reference signal following the preamble signal added to a head portion of a data symbol. A burst part, the demodulation device comprising: a burst detector for performing an autocorrelation operation on the preamble part of the first half of the burst part of the received signal, and performing an autocorrelation operation on the reference signal of the second half of the burst part Partially perform cross-correlation operation; peak position detection unit is used to set detection window according to the autocorrelation operation result and detects the peak value of the cross-correlation power and the position of the peak value in the period of the detection window; output unit is used for distance The peak position detecting unit outputs a timing signal at a predetermined time after the peak position detected; and a demodulation unit for performing Fourier transform on the received signal so as to demodulate the received signal when receiving the outputted timing signal from the output unit. Signal.

In a ninth aspect of the present invention, there is provided demodulation means for demodulating a received signal having a signal including at least a preamble signal and a reference signal following the preamble signal added to a head portion of a data symbol. A burst part, the demodulation device comprising: a burst detector for performing an autocorrelation operation on the preamble part of the first half of the burst part of the received signal, and performing an autocorrelation operation on the reference signal of the second half of the burst part A cross-correlation operation is partially performed; a peak position detection unit is used to set a detection window according to the autocorrelation operation result and detect the peak value of the cross-correlation power and the position of the peak value in the period of the detection window; a counter is used to count the symbol part , and if the preset timing data value is counted, a timing signal is output; a position timing conversion unit for presetting timing data corresponding to the peak position detected by the peak position detection unit to the counter; and a demodulation unit , for performing a Fourier transform on the received signal and demodulating the received signal upon receiving the output timing signal from the counter.

Also, in the present invention, the apparatus further includes an automatic gain control amplifier for amplifying the level of the input reception signal with a gain according to the gain control signal, and outputting the result to the burst detector and the demodulation unit The burst detector performs the burst detection according to the correlation operation of the amplified received signal, and outputs a burst synchronous detection signal; and the device also includes an amplification gain controller for converting the gain control signal output to the automatic gain control amplifier to perform amplification with a gain according to a received signal power value upon receiving the burst synchronous detection signal of the burst detection unit.

Also, in the present invention, the reception signal is modulated according to the OFDM method.

In a tenth aspect of the present invention, there is provided demodulation means for generating a timing signal for initiating demodulation of a received signal having a frame synchronization signal added to a head portion of a data symbol, wherein the burst Partly used as a synchronous training signal, the demodulation device includes: a burst detector for performing a correlation operation in the burst portion of the frame synchronization signal; a peak detection circuit for detecting by the burst The unit performs peak detection of the correlation power, detects a peak only in a detection window centered around the expected timing and exceeds a detection threshold, and outputs a signal indicating the offset between the expected timing and the peak detection position; frame period a counter for counting the frame period by a reference clock, the counter of which uses the set count as an operation period, generates window timing for instructing the detection window of the peak detection circuit according to the operation period, and generates an expected timing according to the count based on the setting timing to instruct the output of the timing signal; an average value circuit for averaging the deviation between the peak detection result of the frame synchronization of the peak detection circuit and the expected timing of the synchronization detection of the frame period counter, and outputting the an average result as a correction value; a correction value setting circuit for setting a period corrected by the correction value of the average value circuit as a count value to the frame period counter; and a demodulation unit for performing Fourier transform on the received signal, And the reception signal is demodulated upon reception of a timing signal according to an instruction output from the frame period counter.

According to the present invention, the gain control signal is output from the amplification gain controller to the automatic gain control amplifier, thereby setting the amplification gain of the automatic gain control amplifier to a predetermined gain.

In this condition, enters the input wait state for the received signal.

Under this condition, the reception signal is first input into the automatic gain control amplifier.

Then, the burst detector detects a burst signal of one period set by the communication system. First, the preamble is detected based on an autocorrelation operation, a burst sync detection signal indicating that the detection is performed is generated, and the signal is output to the amplification gain controller.

The amplification gain controller receives the burst synchronous detection signal of the burst detector, calculates a gain according to the received signal power value, and sets the gain control signal to the calculated value.

The gain control signal is provided to the automatic gain control amplifier. The automatic gain control amplifier receives the gain control signal and sets the gain to the calculated second gain.

For example, the automatic gain control amplifier amplifies the preamble and reference portions of the received signal with a gain corresponding to the level of the received signal.

The burst detector calculates the correlation (autocorrelation and cross-correlation) of the amplified received signal. At this time, the cross-correlation is obtained through the second half of the burst signal.

Also, a burst detector generates a detection window, performs peak detection of the peak position detector based on the autocorrelation result, and sets it in the peak position detector.

Subsequently, the cross-correlation power of the cross-correlation result is provided to a peak position detector.

The peak position detector finds the maximum value of the cross-correlation power value of the cross-correlation result within the detection window, and the position at the time.

Note that all that can be obtained at the end of the window is peak information indicating where the peak is located in the window.

Subsequently, the position timing conversion unit converts the position information obtained by the peak position detector into timing on the time axis, and presets data enabling a counter to count one symbol, so as to generate (output) in accordance with the converted data. Optimized timing signals in this counter.

The once-preset counter continues to periodically count the period of one symbol and outputs the timing signal at a constant timing of each symbol.

Subsequently, the FFT timing signal is output to the demodulator when, for example, the preset data is counted down.

Synchronously with the timing signal, a demodulator performs a fast Fourier transform on the signal to demodulate the OFDM signal.

Moreover, according to the present invention, for example, when frame synchronization detection is obtained by cross-correlation using a synchronization scheme, the result of peak detection of the correlation value is ignored when the correlation value is smaller than a fixed level, and if the correlation value is larger than the constant level If it is flat, the timing and the average value at the same time are used to directly reset the timing of the frame period counter, thereby correcting the frame period counter.

Synchronization with high adaptability and stability can thus be obtained.

Description of drawings

FIG. 1 is a structural block diagram of a first embodiment of a burst synchronous demodulation device using an FFT timing generation circuit according to the present invention.

FIG. 2 is a diagram showing a burst signal portion including a typical preamble of the IEEE802.11a system.

Fig. 3 shows a schematic diagram of a burst signal portion including a typical preamble representing a BRAN system.

Fig. 4 shows a schematic diagram of a burst signal portion including a typical preamble of a Wireless 1394 system.

FIG. 5 is a schematic diagram of a signal form in which a reference signal REF is inserted into one or more constant-period data signal portions in the Wireless 1394 system.

Figure 6 is a schematic diagram of the frame structure in the Wireless 1394 system.

7A and 7B are diagrams illustrating period extension in which a guard interval repeating the last part of data in an OFDM data symbol is added in front of a data part.

8A to 8D are diagrams regarding examples of timing of loading data into FFT.

FIG. 9 is a circuit diagram of a specific structure of the automatic gain control amplifying unit in FIG. 1 .

FIG. 10 is a schematic diagram of an example of a gain control characteristic of the gain control amplifier of FIG. 9 .

FIG. 11 is a schematic diagram of output characteristics of a received signal power monitor for an input level of a received signal.

FIG. 12 is a circuit diagram of an example of a specific configuration of the received signal processing unit in FIG. 1 .

FIG. 13 is a schematic diagram illustrating the structure of the OFDM demodulator of FIG. 1 .

FIG. 14 is a circuit diagram of an example of a specific structure of the burst detector and timing controller of FIG. 1 .

FIG. 15 is a circuit diagram of a structural example of the autocorrelation circuit of FIG. 14 .

FIG. 16 is a circuit diagram of a structural example of the cross-correlation circuit of FIG. 14 .

17A to 17D are diagrams showing the relationship between the cross-correlation peak position and the data loaded into the counter.

18A to 18D are diagrams showing the operation timing of the timer counter (symbol counter).

19A to 19G are timing charts showing the time from the autocorrelation processing of the burst detector to the output of the synchronous detection signals xpulse and ypulse.

20A to 20G are timing charts showing the time from the cross-correlation processing of the burst detection to the output of the synchronous detection signal cpulse and the FFT timing signal TFFT.

Fig. 21 is a flow chart explaining the first stage of the gain control operation in the amplification gain controller unit according to the present invention.

Fig. 22 is a flow chart explaining the second stage of the gain control operation in the amplification gain controller according to the present invention.

Fig. 23 is a flow chart explaining the third stage of the gain control operation in the amplification gain controller according to the present invention.

FIG. 24 is a circuit diagram of an example of a specific configuration of the amplification gain controller of FIG. 1 .

25A to 25H are timing charts illustrating the operation of the amplification gain controller of FIG. 24 .

FIG. 26 is a structural block diagram of a second embodiment of a burst synchronous demodulation device to which the FFT timing generating circuit according to the present invention is applied.

27 is a circuit diagram of a specific structural example of the burst detector and timing control unit of FIG. 26 according to the second embodiment of the present invention.

Fig. 28 is a block diagram of a structural example of the frame synchronization circuit of Fig. 27 .

FIG. 29 is a circuit diagram of a configuration example of the average value circuit of FIG. 28 .

FIG. 30 is a circuit diagram of a structural example of the numerically controlled oscillator (NCO) of FIG. 29 .

31A and 31B are schematic diagrams of accumulation states of low bits of the numerically controlled oscillator (NCO) of FIG. 29 .

FIG. 32 is a schematic diagram showing a state of overflow detection of the numerically controlled oscillator of FIG. 30 .

33A to 33D are timing charts of examples of operation timing of frame synchronization according to the second embodiment of the present invention.

34A to 34D are timing charts showing examples of timing of frame synchronization operations according to the second embodiment of the present invention.

35A to 35D are timing charts of one example of operation timing at the time of initial capture of frame synchronization according to the second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will then be given of preferred embodiments of the present invention with reference to the accompanying drawings.

first embodiment

1 is a block diagram showing the structure of a first embodiment of a burst synchronous demodulation apparatus to which an FFT timing generating circuit according to the present invention is applied.

As shown in Figure 1, the main components that burst pulse synchronous demodulation device 10 comprises are: automatic gain control amplifier (AGCAMP) 101, received signal power monitor (POW) 102, analog/digital (A/D) converter ( ADC) 103, digital/analog (D/A) converter (DAC) 104, A/D converter (ADC) 105, received signal processing unit (RXPRC) 106, OFDM demodulator (DEMOD) 107, delay unit ( DLY) 108, Burst Detector (BDT) 109, Timing Controller (TMG) 110 and Amplification Gain Controller (AGCTL) 111.

The automatic gain control system of the burst pulse synchronous communication system adopted in the present embodiment, transmission (reception) signal, and FFT timing optimization overview will be described in order below, and the burst pulse synchronous demodulation device 10 of Fig. 1 The specific configuration and the function of each component.

First, an automatic gain control system of a burst synchronous demodulator of a 5 GHz band wireless LAN system will be described.

In order to realize excellent communication performance over a wide frequency band, the OFDM modulation method has been adopted in the wireless LAN system of the 5 GHz frequency band.

The OFDM modulation method is strong in anti-abnormal echo and multipath, but on the contrary, it is weak in anti-circuit nonlinearity.

For this reason, when the A/D converter or the like is distorted, it causes a significant drop in the quality of the received signal.

For this reason, in wireless LAN systems in the 5GHz band, on the one hand, introducing timing synchronization in this option requires inserting a 10 to 20 microsecond burst signal called a "preamble" into a The head of the modulated signal, and it is necessary to perform level acquisition on the voltage amplitude of the signal input to the A/D converter 103 within the range of the signal tolerance without distortion.

In addition, several microseconds of the latter half of the preamble include a reference signal for monitoring the frequency characteristics of the channel and correcting the data signal (actual communication data) following the preamble. In the reference signal and the data signal, fluctuations in the level of the digital signal output from the A/D conversion 103 are not allowed. It is necessary to keep the gain of the automatic gain control amplifier 101 constant.

Therefore, in a wireless LAN system in the 5GHz band, a high-speed, high-performance automatic gain amplification method is required to perform level acquisition within the tolerance range of the signal without distortion within 10 microseconds.

In this embodiment, as described later, in order to realize high-speed and high-performance level acquisition in the preamble section, level acquisition in three steps is performed.

As a wireless LAN system in the 5GHz band, there are the following three typical systems:

(1) IEEE 802.11a,

(2) BRAN, and

(3)Wireless 1394.

Figure 2 shows a typical preamble of an IEEE 802.11a system; Figure 3 shows a typical preamble of a BRAN system; and Figure 4 shows a typical preamble of a Wireless 1394 system.

In the preamble in each system shown in Fig. 2 to Fig. 4, A16, B16, etc. represent pattern recognition and burst pulse period, and IA16 represents a pattern in phase opposite to A16.

Also, C64 represents a reference signal, and C16 and C32 represent guard interval portions.

In IEEE 802.11a, pattern B16 is repeated 10 times. In contrast, in BRAN the first 5 cycles are different (A16, IA16, A16, IA16, IA16).

Also, in Wireless 1394, all 10 cycles are different modes. Specifically, they change frame modes A16, IA16, A16, IA16, A16, A16, IA16, A16, IA16, IA16.

In addition, in the Wireless 1394 system, the isochronous transmission mode is supported, so continuous signals such as video signals can be transmitted.

However, when communicating a data signal spread over a long period, the transmission characteristic changes from the transmission characteristic when receiving the reference signal in the preamble signal at the head of the reception signal under a multipath environment, and the reception performance stops deterioration.

For this reason, as shown in FIG. 5, a data signal portion of a constant period or longer has the reference signal REF inserted therein. Therefore, the transmission characteristic is measured again for each reference signal, and the reception performance is prevented from deteriorating.

In addition, FIG. 6 is a schematic diagram of the frame structure in the Wireless 1394 system.

According to the base station or central station (hub station), the Wireless 1394 system defines 4 milliseconds as 1 frame. Many TDMA systems use this frame structure when utilizing the Wireless 1394 system. As shown in Figure 6, the frame is divided into regions for use.

Specifically, a frame as shown in Figure 6 is divided into the following areas from the head of the frame: FSP (Frame Start Packet); SRP (Cyclic Report Packet); SSP (Station Synchronization Packet); IPC (Isochronous Packet Field); APC (Asynchronous Packet Field); and Gap.

A preamble is placed in the frame start packet FSP of the header.

Such a burst signal requires optimization of reception level (AGC), correction of reception frequency offset, and synchronization detection in a short time.

In the present invention, as described later, at the start of reception (start of burst detection), the gain level of the automatic gain control amplifier 101 is maximized and enters a standby state. When it detects a signal, it measures the magnitude of the constant period of the input signal (received signal power), and adjusts the gain level of the preceding automatic gain control amplifier 101 according to the result.

Subsequently, the reception frequency offset is detected and corrected. This frequency offset is detected using autocorrelation. The use of autocorrelation detection is based on the fact that the output of one correlator corresponds to a phase rotation in one repetition period.

Synchronization detection is performed by using autocorrelation or cross-correlation. FFT timing for OFDM data symbols is determined from this detected synchronization timing.

With the OFDM data symbol SYBL, as shown in Figs. 7A and 7B, a period extension method is used to append a guard interval GI in front of the data part for repeating the last part of the data. This will keep the inter-symbol interference caused by multipath etc. to a minimum.

In this example, a guard interval of 0.4 µs is added to the data portion of 3.2 µs, thereby changing the length of one symbol to 3.6 µs.

8A to 8D are diagrams showing timing examples of loading data into the FFT for this case.

The example of FIG. 8B shows a situation where the timing of loading data into the FFT is too early. In this instance, when there is a delayed wave caused by one multipath, the data of the previous symbol covers (superimposes) the FFT range, so deterioration caused by intersymbol interference may occur.

On the other hand, the example of FIG. 8C shows a case where the timing of loading data into the FFT is too slow. If, as in this example, the later part of the symbol is set to fit into the FFT, if due to some effect the FFT timing shifts to the later part, this again results in degradation due to intersymbol interference.

Therefore, the timing of the normal setting is shown in Fig. 8D.

As can be understood from the above, in a receiver of a wireless communication system using OFDM, it is important to optimally set this FFT timing.

The setting method of the FFT timing according to the present invention will be outlined below.

For AGC and frequency offset correction, first half of the preamble is detected. Among them, a detection window for obtaining the cross-correlation of the second half is generated.

For example, the result of autocorrelation detection of the first half of the preamble can be used to set the window. This window is set to have a sufficient interval because autocorrelation detection cannot acquire sufficient synchronization timing.

Perform a peak search of the cross-correlation output in this window. A peak search is performed by comparing the maximum output so far with the magnitude of this current input.

By storing the timing of the window from which the maximum value is obtained, a peak position is determined at the end of the window.

Since the cross-correlation peak is obtained when the input signal matches the expected value signal on the time axis, the FFT timing generated on this basis enables optimal operation.

In this method, however, only peak information indicating where the peak is located within the window can be obtained at the end of the window.

Therefore, the peak information is converted into a timing on the time axis by, for example, the following method.

First prepare a counter for counting one symbol. When this counter reaches a certain value, it will generate an FFT timing signal TFFT.

Since the relationship between the peak position of the cross-correlation and the optimal FFT timing is known in advance, if the relative relationship between the back end (edge) of the detection window and the peak position is known, then it is possible to , optimizing the value of the counter that presets the symbol.

The once-preset counter continues to periodically count the period of one symbol and at a constant timing of each symbol, continuously outputs the FFT timing.

In the above method, when a burst signal portion called a preamble including 10 to 20 µs is inserted in the head of the modulated signal at an optimized FFT timing, the demodulation means for demodulating the received signal The components have the following structures and functions:

The automatic gain control amplifier 101 automatically controls the gain of the reception signal RS received with an antenna not shown in accordance with the level of the gain control signal Vagc provided by the amplification gain controller 111 through the DAC 110, and outputs the result to A/ The D converter 103 serves as a signal RX having a desired level. Note that the automatic gain control amplifier 101 is controlled between the case of automatic gain controlled by the gain control signal Vagc from the amplification gain controller 211 and the case of fixing the control gain.

FIG. 9 is a circuit diagram showing a specific configuration of the automatic gain control amplifier 101 .

The automatic gain control amplifier 101 shown in FIG. 9 includes a gain control amplifier (GCA) 1011, a local oscillator 1012, a multiplier 1013, an amplifier 1014, and a bandpass filter (BPF) 1015 with a bandwidth of several tens of MHz.

Among these components, the local oscillator 1012 and the multiplier 1013 constitute a frequency conversion circuit. For example, the local oscillator 1012 outputs a signal e(j2πf _cw t) having a carrier frequency f _cw to the multiplier 1013 . Note that () represents the power of e.

In the automatic gain control amplifier 101 of Fig. 9, the gain control amplifier 1011 amplifies the received signal (IF input signal) RS according to the gain determined by the gain control signal Vagc, and the frequency conversion formed by the local oscillator 1012 and the multiplier 1013 The circuit converts the frequency of the amplified signal, and then the BPF 1015 band-limits to obtain an output signal (IF output) RX.

In addition, FIG. 10 shows the gain control characteristics of the gain control amplifier 1011 of FIG. 9 .

In FIG. 10, the abscissa represents the gain control signal Vagc, and the ordinate represents the gain.

In this example, as shown in FIG. 10 , the gain control amplifier 1011 linearly changes the gain from 0 to 80 dB within the range of the gain control signal Vagc from 0 V to 1 V.

That is, in this example, the range of the control gain is 80dB.

As shown in Figure 9, the received signal power monitor (POW) 102 comprises the peak detection circuit (Peak Det) 1021 as peak detection circuit, measures the peak voltage of received signal RS, carries out value according to the level of the received signal of input, The received signal is converted into a field strength signal RSSI of a voltage signal, and the signal is output to the A/D converter 105 .

Among them, in order to deal with sudden signal changes, the monitor does not detect the average value, but detects the peak value. It should be noted that at the beginning of the burst detection, it gives a reset signal to reset the peak detection circuit (Peak Det) 1021 so that the maximum peak value can be monitored thereafter.

FIG. 11 shows the output characteristics of the received signal power monitor 102 with respect to the input level of the received signal.

In FIG. 11, the abscissa indicates the input level, and the ordinate indicates the voltage of the field intensity signal RRSI.

In this example, as shown in FIG. 11 , within the range of the input level from -70dBv to -20dBv, the voltage of the field strength signal RRSI varies linearly from 0V to 2V.

A/D converter 103 converts analog reception signal RX output from automatic gain control amplifier 101 into a digital signal and outputs it as digital reception signal RXD to reception signal processing unit 106 .

The D/A converter 104 converts the gain control signal Vagc generated at the automatic gain controller 111 from a digital signal to an analog signal, and outputs it to the automatic gain control amplifier 101 .

The A/D converter 105 converts the field intensity signal RSSI output from the received signal power monitor 102 from an analog signal to a digital signal, and outputs it to the amplification gain controller 111 .

The received signal processing unit 106 converts the digital received signal RXD into baseband signals bb_re (real part) and bb_im (imaginary part), converts the sampling frequency of the baseband signal to a low frequency (down-sampling), according to the signal from the burst detector 109 The error detection frequency Δf is complex multiplied to correct the frequency offset, generating a signal S106 (sy_re and sy_im), and outputting this signal to the OFDM demodulator 107, delay unit 108, burst detector 109 and amplification gain controller (AGCTL) 111.

FIG. 12 shows an example circuit diagram of a specific structure of the reception signal processing unit 106 of FIG. 1 .

As shown in FIG. 12 , reception signal processing unit 106 includes baseband conversion circuit 1016 , digital low-pass filters (LPF) 1062 and 1063 , down conversion circuits 1064 and 1065 , and frequency offset correction circuit 1066 .

The baseband conversion circuit 1061 includes a local oscillator 10611 , and multipliers 10612 and 10613 .

The baseband conversion circuit 1061 multiplies the received signal RXD(if) by the carrier frequency _fcw in the multipliers 10612 and 10613, thereby converting the input received signal RXD(if) into baseband signals bb_re and bb_im shown in formula (1) , and provide the result to LPF 1062 and 1063.

bb_re=if×cos(2πf _cw t)

bb_im＝if×sin(2πf _cw t) …(1)

The LPFs 1062 and 1063 have, for example, a linear phase FIR (Finite Impulse Response) transverse type circuit structure.

(n-1) delay devices 1re-1 to 1re-n-1 connected in cascade with the input line of the baseband signal bb_re and constituting the shift register are used to transfer the input baseband signal bb_re and the delay unit 1re-1 to n multipliers 2re-1 to 2re-n for multiplying the output signal of 1re-n-1 by filter coefficients h(0) to h(n-1), and n multipliers 2re-1 to 2re The output signals of -n are added and the adder 3re that outputs the result to the down conversion circuit 1064 constitutes the LPF 1062.

(n-1) delay devices 1im-1 to 1im-n-1 that are connected in cascade with the input line of the baseband signal im_re and constitute a shift register, are used to transfer the input baseband signal bb_im and the delay units 1im-1 to n multipliers 2im-1 to 2im-n for multiplying the output signal of 1im-n-1 with filter coefficients h(0) to h(n-1), and n multipliers 2im-1 to 2im The output signals of -n are added and the result is output to the adder 3im of the down conversion circuit 1065 to constitute the LPF 1063.

The LPFs 1062 and 1063 and the down conversion circuits 1064 and 1065 convert the sampling frequency of the baseband signals bb_re and bb_im into signals dc_re, dc_im of, for example, 100 MHz to 25 MHz.

At this time, the LPFs 1062 and 1063 limit the bandwidth of the baseband signals bb_re and bb_im, and prevent confusion with adjacent carriers.

Also, the clock is thinned out at the timing of the down-sampling by the down-conversion circuits 1064 and 1065 in accordance with the reception of the supplied signal En.

The frequency offset correction circuit 1066 is composed of a local oscillator 10661 , multipliers 10662 to 10665 , and adders 10666 , 10667 .

The frequency offset correction circuit 1066 reflects the error detection frequency Δf given from the burst detector 109 in the oscillation output of the local oscillator 10661, and performs complex multiplication of this oscillation output and the signal dc_re in the multipliers 10662 and 10663, Complex multiplication of the oscillating output and signal dc_im at multipliers 10663 and 10664, adding the outputs of multiplier 10662 and multiplier 10663 at adder 10666, and combining the outputs of multiplier 10664 and multiplier 10665 at adder 10667 , thereby generating the signals sy_re and sy_im shown in the following formulas (2) and (3), and outputting them to the OFDM demodulator 107, the delay unit 108, the burst detector 109 and the amplification gain controller 111 .

sy_re=dc_re×cos(2πf _cw t)

+dc_im×sin(2πf _cw t) (2)

sy_im＝dc_im×cos(2πf _cw t)

-dc_re×sin(2πf _cw t) (3)

By performing fast Fourier transform in the FFT processing unit 1071 synchronously with the FFT timing signal TFFT provided from the timing control unit 110, the OFDM demodulator 107 processes the output signal S106 of the received signal processing unit 106, as shown in FIG. 1 and FIG. As shown in 13, the signals sy_re and sy_im demodulate the OFDM signal and output the result to the subsequent processing circuit.

The delay unit 108 delays the output signal S106 of the received signal processing unit 106, that is, delays the signals sy_re and sy_im according to the size of the burst cycle for burst detection, and outputs the result as a signal S108 to the burst detector 109.

Note that the burst detection of the IEEE 802.11a system utilizes the delay of the delay unit 108 of 16 clock cycles to detect a burst of 16 clock cycles.

The burst pulse detection of the BRAN system utilizes the delay of the delay unit 108 of 32 clock cycles to detect the first half of the burst pulse with a size of 5 cycles. By delaying the delay unit 108 for 16 clock cycles, the second half of the 5 cycle burst can be detected, but two delays with different delays may be required.

The burst pulse detection of the Wireless 1394 system can carry out the delay of the delay unit 108 of 32 clock cycles, so that detect the burst pulse of the 5 cycle size of the first half, and also can detect the 5 cycle size of the second half with the same delay of burst pulses.

The burst detection unit 109 searches for the correlation between the signal S106 (sy_re and sy_im) from the received signal processing unit 106 and the delay signal S108 from the delay unit 108, and detects the burst signal whose period is determined by the communication system, Detecting parameters relevant to the data packet and frame structure, and generating first and second synchronous detection signals S109W (xpulse and ypulse) synchronously with the timing signal TMNG (X, Y, C) generated by the timing controller 110, as a synchronous timing window signal, and output the signal to the amplification gain controller 111 .

Also, the burst detector 109 outputs the synchronous timing window signal S109C for detecting the peak value of the cross-correlation result to the timing controller 110 .

Also, the burst detector 109 calculates the error frequency from the phase difference between the real part and the imaginary part of the received signal based on the result of the correlation to generate the error detection frequency Δf, and outputs it to the received signal processing unit 106 .

The timing controller 110 outputs the timing signal TMNG (X, Y) triggered by the trigger signal rxwndw to the burst detector 109 for generating first and second synchronous detection signals S109W (xpulse and ypulse) from the burst detector 109 ).

And, the timing controller 110 monitors the peak timing according to the cross-correlation result from the burst detector 109, outputs a third synchronous detection signal S210 (cpulse) to the amplification gain controller 111 at a predetermined time after this peak timing, And output the FFT timing signal TFFT to the OFDM demodulator 107 .

FIG. 14 shows an example circuit diagram of the specific structures of the burst detector 109 and the timing controller 110 of FIG. 1 .

The burst detector 109 includes an autocorrelation circuit 10901, a cross-correlation circuit 10902, a coefficient table 10903, delay units 10904 and 10905 for setting the delay amount to 32 clock cycles, and a delay unit 10906 for setting the delay amount to 48 clock cycles to 10908, moving average circuit 10909 to 10913, absolute value calculation circuit 10914 to 10916, threshold value circuit 10917, comparison circuit 10918, timing window X circuit 10919, timing window Y circuit 10920, detection window circuit 10921, frequency error detection circuit 10922 and Latch circuit 10923.

Also, the timing control unit 110 has a peak position search (detection) circuit (PPS) 11001 , a position/timing conversion circuit 11002 (PTTC), and a timing counter 11003 .

Signals sy_re and sy_im supplied from the received signal processing circuit 106 are input to an autocorrelation circuit 10901 , a cross-correlation circuit 10902 , and an absolute value calculation circuit 10914 .

Moreover, the signal sy_re is delayed by exactly 16 clock cycles in the delay unit 108re, and then input to the autocorrelation circuit 10901. Similarly, the signal sy_im is delayed by exactly 16 clock cycles in the delay unit 108im, and then input to the autocorrelation circuit 10901.

FIG. 15 is a circuit diagram showing a structural example of the autocorrelation circuit.

As shown in FIG. 15 , an autocorrelation circuit 10901 is formed of multipliers 11 to 14 and adders 15 and 16 .

The autocorrelation circuit 10901 exploits the fact that the X and Y parts of the first half of the preamble added to the head of the received signal are a function of the frequency of 16 clock periods, for the input signals sy_re and sy_im and 16 clock periods The outputs sy_re ^* and sy_im ^* of the delay elements 108re and 108im of , perform conjugate complex multiplication to obtain the autocorrelation outputs acre and acim, and output the autocorrelation outputs acre and acim to the delay elements 10904 to 10907 and the moving average Circuits 10909 to 10912.

Specifically, the input signal sy_re and the delayed signal sy_re ^* are complex multiplied in the multiplier 11, the input signal sy_re and the delayed signal sy_im ^* are complex multiplied in the multiplier 12, and the input signal sy_im and the delayed signal sy_re ^* are multiplied in the multiplier 13 performs complex multiplication, the input signal sy_im and the delayed signal sy_jm ^* perform complex multiplication in the multiplier 14, and the output of the multiplier 11 and the output of the multiplier 14 are added in the adder 15, thereby obtaining the autocorrelation output signal acre, And the output of the multiplier 12 and the output of the multiplier 13 are added in the adder 16 to obtain the autocorrelation output signal acim.

As shown in FIG. 16, the cross-correlation circuit 10902 has: (m-1) delay units 21re-1 to 21re-m-1 connected in cascade to the input line of the signal sy_re and constituting a shift register; m multipliers 22re -1 to 22re-m for multiplying the coefficients set in the coefficient table 10903 with the input signal sy_re and the output signals of the delay units 21re-1 to 21re-m-1; and the adder 23re for multiplying the m The output signals of the multipliers 22re-1 are added and output 22re-m, and a cross-correlation output signal cc_re is output to the absolute value calculation circuit 10916.

Also, as shown in FIG. 16, the cross-correlation circuit 10902 has: (m-1) delay units 21im-1 to 21im-m-1 connected in cascade to the input line of the signal sy_im and constituting a shift register; m The multipliers 22im-1 to 22im-m multiply the coefficients set in the coefficient table 10903 by the input signal sy_im and the delay units 21im-1 to 21im-m-1; and the adder 23im for adding m multiplications 22im-1 to 22im-m and outputs the cross-correlation output signal cc_im to the absolute value calculation circuit 10916.

The cross-correlation circuit 10902 sequentially writes the input signals sy_re and sy_im into the shift register, and multiplies these tap values by the value of the coefficient table 10903 in the multipliers 22re-1 to 22re-m and 22im-1 to 22im-m , and obtain the cross-correlation output signals cc_re and cc_im.

Note that the number of taps of the shift register in this embodiment is set to 32, for example, and the coefficient table stores data values of 32 clock cycles before the second half of the preamble C64.

The output signal acre of the autocorrelation circuit 10901 is directly input to the moving average circuit 10911 , and is delayed by an amount of 48 clock cycles by the delay unit 10906 , averaged (integrated), and input to the absolute value calculation circuit 10915 .

Similarly, the output signal acim of the autocorrelation circuit 10901 is directly input to the moving average circuit 10912 , and is delayed by an amount of 48 clock cycles by the delay unit 10907 , averaged (integrated), and input to the absolute value calculation circuit 10915 .

Then, the real part re and the imaginary part im are squared at the absolute value calculation circuit 10915 to calculate the absolute value (re ² +im ² ) and thereby obtain the autocorrelation power ACP, which is then output to the comparison circuit 10918 .

Also, the output signal acre of the autocorrelation circuit 10901 is directly input to the moving average circuit 10909, and is delayed by an amount of 32 clock cycles by the delay unit 10904, averaged (integrated), and input to the frequency error detection circuit 10922.

Similarly, the output signal acim of the autocorrelation circuit 10901 is directly input to the moving average circuit 10910 , and delayed by an amount of 32 clock cycles by the delay unit 10905 , averaged (integrated), and input to the frequency error detection circuit 10922 .

The output signals cc_re and cc_im of the cross-correlation circuit 10902 are squared in the absolute value calculation circuit 10916 for the real part re and the imaginary part im to calculate the absolute value (re ² +im ² ), and thus obtain the cross-correlation power CCP, which then outputs to the peak position search circuit 11001 of the timing controller 110.

Also, the input signals sy_re and sy_im are squared in the absolute value calculation circuit 10914 for the real part re and the imaginary part im to calculate the absolute value (re ² +im ² ). The absolute value is directly input to the moving average circuit 10913 and delayed by the delay unit 10908 for 48 clock cycles, averaged (integrated), and output to the threshold circuit 10917 .

Threshold circuit 10917 defines a threshold value th_ac of autocorrelation and supplies a signal to comparison circuit 10918 based on this threshold value.

The comparison circuit 10918 compares the autocorrelation power ACP with the autocorrelation threshold th_ac, and outputs the comparison result to the timing window X circuit 10919 , the timing window Y circuit 10920 and the detection window circuit 10921 .

Thus, the timing window X circuit 10919 multiplies the timing window by the comparison result of the comparison circuit 10918 , and outputs the first synchronous detection signal xpulse to the amplification gain controller 111 .

Then, the timing window Y circuit 10920 multiplies the timing window by the comparison result of the comparison circuit 10918 , and outputs the second synchronous detection signal ypulse to the amplification gain controller 111 .

The detection window circuit 10921 generates a detection window DW for peak search by the peak position search circuit 11001 of the timing controller 110, and sets the detection window DW to the peak position search circuit 11001 as a signal S109C.

In this embodiment, cross-correlation detection is performed in the first half of the C area in the second half of the preamble.

The logic value of the peak detection position is set at the 48th sample from the head of the C area. The detection window is set according to the time when the autocorrelation result of the second half of the Y zone exceeds the determined threshold.

Since thresholds are used, the reliability of this reference is not highly dependent on reception conditions and the like.

Therefore, the detection window in this embodiment is set within a range of about 10 clock cycles before and after the point of the reference predetermined sampling number. It is possible to change this range.

The peak position search circuit 11001 searches for the maximum value of the cross-correlation power value CCP of the cross-correlation result in the detection window DW and the position of the maximum value at this time.

As explained above, the peak search is performed by comparing the maximum output so far with the magnitude of the current input.

The peak position is determined at the end of the detection window DW by storing the timing of the detection window DW giving the maximum value.

Since the peak of the cross-correlation can be obtained when the input signal and an expected value signal match on the time axis, generating the FFT timing on that basis will achieve optimal operation.

The interval from peak position to optimized FFT timing is 32 samples (clock periods).

However, all that can be obtained at the end of the window is peak information indicating where the peak is located in the detection window DW.

Therefore, the position/timing conversion circuit (PTTC) 11002 converts the peak information obtained by the peak position search circuit 11001 into timing on the time axis by the following procedure, and presets data to the timing counter 11003 based on the converted data, Using this preset data, the timing counter 11003 for counting one symbol will be able to generate (output) an optimized FFT timing signal TFFT.

Since the position/timing conversion circuit 11002 knows in advance the relationship between the peak position of the cross-correlation and the optimized FFT timing, if the relative relationship between the rear end (edge) of the detection window DW and the peak position is known relationship, the timer counter 11003a can be optimally preset with the value of a symbol counter at the rear edge of the detection window DW.

The once-preset timing counter 11003 continues to periodically count the period of one symbol, and continuously outputs the FFT timing at a constant timing of each symbol.

The data preset in the counter 11003 by the position/timing conversion circuit 11002 will be described here with reference to FIGS. 17A to 17D.

17A to 17D are diagrams showing the relationship between the cross-correlation peak position and the data loaded into the counter.

DW shown in FIG. 17A denotes a detection window, CCP shown in FIGS. 17B to 17D denotes the cross-correlation power, and CC denotes a count value of a timer counter.

The examples of FIGS. 17A to 17D show a case where the window width WW of the detection window DW is set to 9 samples.

The timer counter 11003 is composed of, for example, a down counter. The data value DT to be loaded is set according to the following equation:

DT＝32-(WW-α) …(4)

The example of FIG. 17B shows a case where a peak is detected at the 3rd sample from the leading edge of the detection window.

In this case, 32-(9-2)=25 is loaded into counter 11003 at the trailing edge of the window.

The example of FIG. 17C shows a case where a peak is detected at the 5th sample from the leading edge of the detection window.

In this case, 32-(9-4)=27 is loaded into counter 11003 at the trailing edge of the window.

The example of FIG. 17D shows a case where a peak is detected at the 9th sample from the leading edge of the detection window.

In this case, 32-(9-8)=31 is loaded into counter 11003 at the trailing edge of the window.

Note that in the example of FIG. 17A , α in the above equation (4) is set to a value minus 1 from the number of samples at which a peak has been detected from the leading edge of the window, but the value can be set so that the number of samples is Subtract without changing.

For example, if half the width of the detection window DW consists of 10 samples and a peak is detected at the 7th sample from the leading edge of the detection window, the value loaded at the trailing edge of the window is 32-(20-7 )=19.

When the peak is at the 15th sample, the loaded value is 32-(20-15)=27

Through this processing, the position information of the peak can be converted into real-time information.

Note that the width WW of the detection window may be set approximately symmetrically to the reference position.

Note that when a lower limit is set for the cross-correlation value and the correlation value is smaller than the lower limit value, it is also possible to configure the system to consider no peak detected.

For example, it is possible to prevent peaks at the top or trailing edge of the window when continuing to enter 0's. In this case, the result is that no peaks are detected.

Furthermore, when the counter is constituted as a down counter, changing the input value of the counter after counting down to 0 will make it possible even for a packet in which a resynchronization reference symbol is inserted between data symbols An optimization of the FFT timing is achieved.

As shown in FIG. 4, in the case of the Wireless 1394 system, the C area of the second half of the preamble is formed by a guard interval C16 of 16 samples and two successively repeated reference data C64 of 64 samples.

The result is that 63 is loaded after the peak detection is corrected and the counter returns to zero.

On the other hand, in the area of a normalized data symbol, 71 is loaded.

Also, corresponding to the reference symbol in the data symbols, a reference symbol position is calculated, and the one symbol counter is adjusted to be exactly the same as the C area.

Also, at the boundary of the reference symbol, 80 is loaded in the one symbol counter.

18A to 18D are diagrams showing the operation timing of the timer counter (symbol counter).

Note that FIG. 18D shows a count value TVC, and timings indicated by (1) and (2) are timings at which data is loaded at the trailing edge of the detection window DW.

Furthermore, the timing controller 110 receives the peak timing of the cross-correlation power CCP from the peak position search circuit 11001 . The timing counter 11003 outputs the third synchronous detection signal cpulse to the amplification gain controller 111 after a constant time from the peak timing.

19A to 19G are timing charts showing from the autocorrelation processing of the burst detector to when the synchronous detection signals xpulse and ypulse are output.

Fig. 19A shows the reference (sy_re, sy_im) of the preamble and the input signal S106, Fig. 19B shows the delayed signal S108 obtained by delaying the signal S106 using the delay unit 108, Fig. 19C shows the autocorrelation power ACP, and Fig. 19D shows Timing window X, FIG. 19E shows timing window Y, FIG. 19F shows the first synchronization detection signal xpulse, and FIG. 19G shows the second synchronization detection signal ypulse.

As shown in Fig. 19A and Fig. 19B, the preamble signal of the Wireless 1394 system has 5 cycles of 16 clock cycle X part and Y part. As shown in Fig. 19C, the autocorrelation power ACP increases in the X and Y sections.

Thus, by adding the timing window X to the first half of the X portion as shown in Figures 19A, 19B, and 19D, and by adding the timing window Y to the second half of the Y portion as shown in Figures 19A, 19B, and 19E, The input of each part is detected, and thus the first synchronous detection signal xpulse and the second synchronous detection signal ypulse as shown in FIGS. 19F and 19G can be output.

20A to 20G are timing charts showing the time from the cross-correlation processing of the burst detection to when the third synchronous detection signal cpulse and the FFT timing signal TFFT are output.

Fig. 20A shows the input signal S106(sy_re, sy_im), Fig. 20B shows the autocorrelation power ACP, Fig. 20C shows the cross-correlation power CCP, Fig. 20D shows the detection window DW, and Fig. 20E shows the The data DT is loaded, and FIG. 20F shows the third synchronous detection signal cpulse, and FIG. 20G shows the FFT timing signal TFFT.

In this embodiment, according to the cross-correlation coefficient table 10903, the data values of the first 32 clock cycles of the C64 part are used. Therefore, as shown in FIG. 20C, the cross-correlation power CCP becomes maximum at the 32nd clock cycle of the C64 section.

As shown in FIG. 20D , by setting the detection window DW around the timing when the cross-correlation power CCP becomes the maximum value, more accurate peak detection can be performed. As shown in FIG. 20E, the position/timing conversion circuit 11002 then presets the timing counter 11003 with data capable of generating (outputting) the optimized FFT timing signal TFFT at the timing of detecting the trailing edge of the window DW.

Also, as shown in FIGS. 20F and 20G , after 32 clock cycles of the peak detection timing, the third synchronous detection signal cpulse and the FFT timing signal TFFT are output.

Subsequently, as shown in FIG. 20G, the FFT timing signal TFFT is output after 64 clocks, and then repeatedly output for 72 clock cycles.

The frequency error detection circuit 10922 finds the phase difference from the real and imaginary parts of the autocorrelation output signal and calculates the error detection frequency Δf according to the equation shown below:

Δf＝tan ^-1 (acim/acre)×(1/32)×20×10 ⁶ (Hz) …(5)

As will be described later in detail, according to the digital received signal S106 from the received signal processing unit 106 after the gain control by the automatic gain control amplifier 101, the received signal RS from the A/D converter 105 representing the received signal power monitor 102 The digital field strength signal RSSID of the peak value of the level, the first and second synchronous detection signals S109W (xpulse, ypulse) as synchronous timing window signals from the burst detector 109 and the third synchronous detection signal from the timing controller 110 signal S110 (cpulse), the amplification gain controller 111 controls the received signal to an optimum signal level by performing gain control that changes the control gain voltage Vagc, and outputs the control gain voltage signal Vagc to the automatic A gain control amplifier 101, wherein the control gain voltage Vagc is used to control the gain of the automatic gain control amplifier 101 to match the synchronization burst detection timing.

The gain control operation of the amplification gain controller 111 will be described in detail below based on the flowcharts of FIGS. 21, 22, and 23. FIG.

In this embodiment, three stages of level acquisition are performed in the preamble portion of the received signal in order to realize high-speed and high-performance level acquisition.

As the first stage, at the start of burst detection (ST1), the gain control signal Vagc is output from the automatic gain controller 111 with the maximum value (ST2), and the gain of the automatic gain control amplifier 101 is set to the maximum (the first gain ) (ST3), and burst detection is performed using the cooperation of the delay unit 108 and the burst detector 109.

At this time, the output signal of the A/D converter 103 stops being distorted, but since it is not a data signal, it does not degrade the quality of the received signal.

Furthermore, even if the preamble signal is distorted, since the burst detector 109 uses the autocorrelation circuit 10901, burst detection can be performed without lowering the detection rate.

In this way, the arrival of the preamble at the head of the reception signal RS is waited (ST4).

At the same time, the power of the received signal is monitored at the received signal power monitor 102, and the field strength signal RSSI of the received signal power signal is input as a digital signal RSSID through the A/D converter 105 (ST5).

Here, as previously described, peak values are detected instead of mean values in order to deal with abrupt signals. Note that a reset signal is given at the beginning of burst pulse detection to reset the peak value detection circuit, and then observe the largest peak value.

As the second stage, when performing burst pulse detection (ST6), when receiving the first synchronous detection signal S109W (xpulse) from the burst pulse detector 109 (ST7), according to the electric field intensity signal RSSID digital Calculate the gain (ST8), set the gain control signal Vagc to the calculated value CV1 (ST9), and set the gain of the automatic gain control amplifier 101 to the calculated value CV1 through the D/A converter 104 (the second gain ) (ST10).

At this time, calculate the control gain CG1 according to the following formula:

CG1(dB)＝VRSSI(dBv)-Vref1(dBv) ...(6)

Here, VRSSI represents a received signal power value monitored at received signal power detector 102 , and Vref1 represents a first reference signal power value of an appropriate value that does not distort A/D converter 103 .

Note that the gain of the automatic gain control amplifier 101 at this time includes analog signal processing in the calculation step of the peak value of the received signal power and includes slight variations, and thus is rough gain control.

For this reason, after passing the gain through the A/D converter 103 without distortion, the digital value of the received signal is integrated at the automatic gain controller 111, thereby measuring the correct signal power (ST11).

As the third stage, after a period of time has elapsed in the second stage, by receiving the second synchronous detection signal S109W (ypulse) (ST12) from the burst pulse detector 109, according to the A/D converter without distortion 103 of the digital integral value of the received signal, calculate the gain (ST13), set the gain control signal Vagc to the calculated value CV2 (ST14), and set the gain of the automatic gain control amplifier 101 to the set value through the D/A converter 104 The calculated value CV2 (third gain) is optimized (ST15).

At this time, the control gain CG2 is calculated according to the following formula:

CG2(dB)＝VI(dBv)-Vref2(dBv) ...(7)

Wherein, VI represents the received signal power value integrated in the amplification gain controller 111 and passed through the A/D converter 103, Vref2 represents the second reference signal power value and the optimal value of the received signal power after gain control.

In this way, the optimized gain value is fixed until thereafter the data signal ends and the next burst detection starts (ST16).

Then, when the third synchronous detection signal S110 (cpulse) from the timing controller 110 is input, the operation procedure shifts to the aforementioned processing of step ST1.

Note that from the start of burst detection, a reset signal is given to the received signal power monitor 102 to reset the peak detection circuit 1021, and then the maximum peak value is observed.

Through the above operation process, high-speed and accurate level acquisition can be realized according to the optimal gain value.

FIG. 24 is a circuit diagram showing an example of a specific structure of the amplification gain controller 111 of FIG. 1 .

As shown in FIG. 24, the amplification gain controller 111 has an initial gain table 11101, an RSSI adjustment table 11102, multipliers 11103 and 11104, adders 11105 to 11108, a delay unit 11109 that delays by 48 clock cycles, a delay unit 11110, a logarithmic A converter 11111 , a state machine circuit 11112 , a gain selection circuit 11113 and a control gain adjustment table 11114 .

Amplification gain controller 111 uses the state machine structure based on the timing pulse of synchronous detection, i.e. flip-flop signal rxwndw, first synchronous detection signal xpulse from burst pulse detector 109 and second synchronous detection signal ypulse and from timing controller 110 The third synchronous detection signal cpulse, and controls different gains agc to be output to the automatic gain control amplifier 101 according to states 0 to 3.

25A to 25H show timing charts illustrating the operation of the amplification gain controller of FIG. 24 .

Figure 25A shows the input signal S106 (sy_re, sy_im); Figure 25B shows the flip-flop signal rxwndw; Figure 25C shows the first synchronous detection signal xpulse; Figure 25D shows the second synchronous detection signal ypulse; Figure 25E FIG. 25F shows the state; FIG. 25G shows the gain control signal Vagc; and FIG. 25H shows the reception signal RX output from the automatic gain control amplifier 101 .

Hereinafter, the operation in the automatic gain controller of FIG. 24 in each state will be described with reference to FIGS. 25A to 25H.

State 0 (initial mode, rxwndw wait mode)

According to the sign signal Station (station) ID, select an appropriate gain from the initial gain table 11101. In this embodiment, the initial gain table 11101 is set so as to obtain the maximum gain.

Then, as shown in FIGS. 25B, 25F, and 25G, when the trigger signal rxwndw rises, the trigger signal rxwndw is passed through the gain selection circuit 11113 and output as the gain control signal Vagc from the control gain adjustment table 11114, and then the operation program shifts to the state 1.

State 1 (xpulse wait mode)

As shown in FIGS. 25F and 25G, the initial gain (maximum gain) determined by the initial F gain table 11101 is output as a gain control signal Vagc.

When the field strength signal RSSI is received by the A/D converter 105, according to formula (8), the adder 11108 calculates the RSSI gain gain_rssi based on the received signal power. Then, as shown in FIGS. 25C, 25F, and 25G, when the first synchronous detection signal xpulse is input, the gain selected by the gain selection circuit 11113 is switched from the initial gain to the RSSI gain gain_rssi obtained by the adder 11108, and is adjusted from the control gain The table 11114 is output as the gain control signal Vagc, and then the operation program shifts to state 2.

gain_rssi=rssiref-rssi+40 ...(8)

Here, since the bit width is determined by 8 bits in the reference value of RSSI, rssiref is a value obtained by subtracting 40 in advance, and it is corrected by adding 40 when calculating the gain.

State 2 (vpulse wait mode)

As shown in FIGS. 25F and 25G , the RSSI gain gain_rssi is output as the gain control signal Vagc.

By squaring the input signal sy_re at multiplier 11103, squaring the input signal sy_im at multiplier 11104, and adding them at adder 11105, the magnitude of the input received signal is found. Furthermore, the digital integral value is found through the adder 11106, the delay unit 11109 and the delay unit 11110, and the level adssi of the received signal is calculated in the logarithmic converter 11111 according to formula (9).

adssi＝4×10log(re ² +im ² ) …(9)

Then, the adssi gain gain_rssi is calculated according to formula (10) by using the received signal level adssi and the optimal value adssiref of the received signal power after gain control and the currently selected RSSI gain gain_rssi. Then, as shown in FIGS. 25D, 25F, and 25G, when the second synchronous detection signal ypulse is input, the gain selected by the gain selection circuit 11113 is switched from the RSSI gain gain_rssi to the adssi gain gain_rssi obtained by the adder 11108, and from the control gain The adjustment table 11114 is output as the gain control voltage signal Vagc, and then the operation program shifts to state 3.

gain_adssi=adssiref-adssi+gain_rssi ...(10)

State 3 (cpuse waiting mode)

As shown in FIGS. 25F and 25G , the adssi gain gain_rssi is output as the gain control signal Vagc.

Then, as shown in FIGS. 25E and 25F, when the third synchronous detection signal cpulse is input, the operation program shifts to state 0.

Note that the gain control voltage signal Vagc maintains the adssi gain gain_rssi.

Subsequently, operations performed by the structure of FIG. 1 will be explained.

First, when burst detection is started, the amplification gain controller 111 sets the gain signal Vagc to a maximum value and outputs it by triggering of the trigger signal rxwndw. This gain control signal Vagc is converted into an analog signal by the D/A converter 104 and supplied to the automatic gain control amplifier 101 .

The automatic gain control amplifier 101 receives this analog gain control signal Vagc, and sets the gain to the maximum first gain.

In this case, a state of waiting for the input of the reception signal RS is entered.

In such a case, first, the preamble signal at the head of the reception signal RS is input to the automatic gain control amplifier 101 .

The automatic gain control amplifier 101 amplifies an illustrative X portion of the first half of the preamble of the received signal RS with maximum gain, and outputs the result as a signal RX to the A/D converter 103 .

At the same time, the preamble signal of the received signal RS is input to the received signal power monitor 102 . The received signal power monitor 102 monitors the power of the received signal RS, measures the peak voltage, converts the result into the field strength signal RSSI of the voltage signal according to the value corresponding to the input received signal level, and outputs the result to A /D converter 105 .

The field intensity signal RSSI of this reception signal power signal is input to the amplification gain controller 111 as a digital signal RSSID through the A/D converter 105 .

The A/D converter 103 converts the preamble portion of the reception signal RS from an analog signal to a digital signal, and supplies the result as a signal RXD to the reception signal processing unit 106 .

At this time, the output signal of the A/D converter 103 stops being distorted, but it is not a data signal, and therefore does not cause degradation in the quality of the received signal.

The reception signal processing unit 106 converts the input digital reception signal RXD into baseband signals bb_re (real part) and bb_im (imaginary part), and converts the sampling frequency of the baseband signal to a low frequency.

Then, at this time, since the burst detector 109 has not provided the error detection frequency Δf, the frequency offset is not corrected, and then the signal S106 (sy_re, sy_im) is generated and output to the OFDM demodulator 107, the delay unit 108 and burst detector 109.

The delay unit 108 delays the output signal S106 of the received signal processing unit 106, that is, in order to perform burst detection, the signals sy_re and sy_im are delayed according to the burst period, and the result is output to the burst detection as a signal S108 device 109.

The burst detector 109 performs autocorrelation and cross-correlation between the signal S106 (sy_re, sy_im) from the reception signal processing unit 106 and the delayed signal S108 from the delay unit 108 .

Then, based on the result of autocorrelation, it detects a burst pulse signal whose period is determined by the communication system, first generates a first synchronous detection signal S109W(xpulse) indicating detection of the first half X portion of the preamble signal, and outputs it to Amplify the gain controller 111 .

Note that even if the preamble signal is distorted, since the burst detector 109 uses an autocorrelation circuit, burst detection can be performed without lowering the detection rate.

Also, the burst detector 109 calculates the error frequency from the phase difference between the real part and the imaginary part of the received signal based on the result of autocorrelation, generates an error detection signal Δf, and outputs it to the received signal processing unit 106 .

The amplification gain controller 111 receives the burst synchronous detection signal S109W (xpulse) from the burst detector 109, calculates the gain according to the level of the digital field strength signal RSSID, and sets the calculated value CV1 as the gain control signal Vagc.

At the D/A converter 104 , this gain control signal Vagc is converted into an analog signal, and supplied to the automatic gain control amplifier 101 .

The automatic gain control amplifier 101 receives the analog gain control signal Vagc, and sets the gain as the second gain according to the calculated value.

Note that the gain of the automatic gain control amplifier 101 at this time includes analog signal processing in the calculation step of the power peak value of the received signal, and includes minute changes, and thus is rough gain control.

The automatic gain control amplifier 101 amplifies the remaining X portion of the preamble signal of the received signal RS and the Y portion of the latter half with a second gain according to the received signal level, and outputs the result as a signal RX to the A/D converter 103.

The A/D converter 103 converts the preamble portion of the reception signal RS from an analog signal to a digital signal, and supplies the result as a signal RXD to the reception signal processing unit 106 .

At this time, the input signal of the A/D converter 103 has been amplified with a gain based on an appropriate value that does not distort the A/D converter 103 , and therefore, no distortion occurs in the output signal of the A/D converter 103 .

The reception signal processing unit 106 converts the input digital reception signal RXD into baseband signals bb_re (real part) and bb_im (imaginary part), and converts the sampling frequency of the baseband signal to a low frequency.

Then, the received signal processing unit 106 corrects the frequency offset according to the error detection frequency Δf from the burst detector 109 to generate a signal S106 (sy_re, sy_im), and the signal is output to the OFDM demodulator 107, the delay unit 108 and burst detector 109.

The delay unit 108 delays the output signal S106 of the received signal processing unit 106, that is, in order to perform burst detection, the signals sy_re and sy_im are delayed according to the burst period, and the result is output to the burst detection as a signal S108 device 109.

The burst detector 109 performs autocorrelation and cross-correlation between the signal S106 (sy_re, sy_im) from the received signal processing unit 106 and the delayed signal S108 from the delay unit 108 .

Then, based on the result of autocorrelation, it detects a burst signal whose period is determined by the communication system, generates a sync detection signal S109W(ypulse) indicating that the second half Y portion of the preamble is detected, and outputs it to the amplification gain controller 111.

Furthermore, the burst detector 109 calculates an error frequency from the phase difference between the real part and the imaginary part of the received signal based on the result of autocorrelation, generates an error detection frequency signal Δf, and outputs it to the received signal processing unit 106 .

The amplification gain controller 111 receives the signal S106 having a gain based on the received signal power and passes through the A/D converter 103 without distortion, integrates the digital value of the received signal, and measures the correct signal power.

In addition, the amplification gain controller 111 receives the second synchronous detection signal S109W(ypulse) from the burst detector 109, and calculates gain, and the calculated value CV2 is set as the gain control signal Vagc.

This gain control signal Vagc is converted into an analog signal at the D/A converter 104 and supplied to the automatic gain control amplifier 101 .

The automatic gain control amplifier 101 receives the analog gain control signal Vagc, and sets the gain as a third gain which is an optimum calculated value.

According to the level of the received signal, the automatic gain control amplifier 101 amplifies the remaining Y portion of the preamble signal of the received signal RS and the reference C64 after C16 with a third gain, and outputs the result as a signal RX to the A/D conversion device 103.

The A/D converter 103 converts the data portion of the received signal RS and the reference C64 from an analog signal to a digital signal, and supplies the result as a signal RXD to the received signal processing unit 106 .

At this time, since the input signal of the A/D converter 103 has been amplified with a gain based on an optimum value that does not distort the A/D converter 103, no distortion occurs in the output signal of the A/D converter 103 .

The reception signal processing unit 106 converts the input digital reception signal RXD into baseband signals bb_re (real part) and bb_im (imaginary part), and converts the sampling frequency of the baseband signal to a low frequency.

Then, according to the error detection frequency Δf from the burst detector 109, the frequency offset is corrected to generate a signal S106 (sy_re, sy_im), and the signal is output to the OFDM demodulator 107, the delay unit 108 and the burst detector 109 .

The delay unit 108 delays the output signal S106 of the received signal processing unit 106, that is, in order to perform burst detection, the signals sy_re and sy_im are delayed according to the burst period, and the result is output to the burst detection as a signal S108 device 109.

The burst detector 109 performs an autocorrelation between the signal S106 (sy_re, sy_im) from the received signal processing unit 106 and the delayed signal S108 from the delay unit 108, and performs an autocorrelation in the first half of the C area of the second half preamble of mutual correlation.

And according to the autocorrelation result, the burst detector 109 generates the detection window DW for the peak detection of the peak position search circuit 11001 of the timing controller 110 through the detection window circuit 10921, and sets it in the timing controller 110 The peak position search circuit 11001.

Then, the cross-correlation power of the cross-correlation result is supplied to the timing controller 110 .

The peak position search circuit 11001 searches for the maximum value of the cross-correlation power value CCP of the cross-correlation result in the detection window DW and the position of the maximum value at this time.

Note that what can be obtained at the end of the detection window DW is only peak information indicating where the detection peak is located in the detection window DW.

Subsequently, the position/timing conversion circuit 11002 converts the position information obtained by the peak position search circuit 11001 into a timing on the time axis, and presets data with which the timing counter 11003 for counting one symbol can An optimized FFT timing signal TFFT is generated (output) in the timing counter 11603 according to the converted data.

The once-preset timing counter 11003 continues to periodically count the period of one symbol, and continuously outputs the FFT timing signal TFFT at a constant timing of each symbol.

Then, after a predetermined time from the peak timing, the third synchronous detection signal S110 (cpulse) is output to the amplification gain controller 111, and when the preset data is counted down, the FFT timing signal TFFT is output to the OFDM demodulator 107.

The amplification gain controller 111 receiving the third synchronous detection signal S110 (cpulse) returns to the initial mode, that is, the waiting mode of the trigger signal rxwndw waiting mode.

Then, the optimal gain value is fixed until after the data signal is terminated, after which the next burst detection starts.

The OFDM demodulator 107 processes the output signal S106 of the reception signal processing unit 106, that is, the signals sy_re and sy_rim, by fast discrete Fourier transform in synchronization with the FFT timing signal TFFT supplied from the timing controller 110, so as to demodulate the OFDM signal .

As explained above, according to the first embodiment of the present invention, the burst detector 109 and the amplification gain controller 111 perform AGC control and Frequency offset correction, followed by providing a detection window period for cross-correlation detection, using the timing controller 110 to perform peak detection of the cross-correlation in the detection window DW, and loading data corresponding to the peak position in the counter 11003 In order to count the part of the OFDM symbol in the end (back edge) of the window, so that the setting of the optimal FFT timing is independent of the condition of the channel.

Also, the window width for detection can be changed according to conditions, so the width can be set according to reception conditions, making it possible to efficiently set the optimal FFT timing corresponding to the channel.

Also, by adopting a configuration that provides a lower limit for the cross-correlation value and considers no peak detected when the correlation value is smaller than the lower limit value, if 0 continues to be input in this state, it will be possible Prevents peaks from appearing at the top or trailing edge of the window.

Also, when the counter is constituted with a down counter and the load value of the counter is changed after counting down to 0, it will be made even for a packet in which a resynchronization reference symbol is inserted between data symbols, Optimization of the FFT timing can also be easily achieved.

Moreover, according to the first embodiment of the present invention: an amplification gain controller 111 is provided for outputting a gain control signal to the automatic gain control amplifier 101, for when a trigger signal indicating the start of burst pulse detection is received Amplify the maximum value, and calculate the second gain according to the received signal power value detected by the received signal power monitor 102, and output the gain control signal to the automatic gain control amplifier 101 so as to utilize the second gain to amplify, when the burst pulse is received When the first burst of the detector 109 detects the signal synchronously, a digital received signal amplified with the second gain is received and integrated to obtain the received signal power value, and a third gain is calculated based on the obtained received signal power value And the output gain control signal is to the automatic gain control amplifier 101, so that when receiving the second burst pulse synchronization detection signal of the burst pulse detector 109, the third gain is used to amplify, the first embodiment of the present invention can Get the following effects.

High-speed and precise level acquisition is possible. The result is an advantage of high-performance reception quality enabled in a burst-synchronous type communication system such as a wireless LAN.

Also, when burst detection for a preamble can be performed in two stages, by performing rough gain control at the time of first burst detection and fine gain control at the time of subsequent burst detection, it is possible to perform Recovery in case the timing of the first burst detection is wrong.

Also, it is possible to specify the mode of the signal to be digitally integrated to perform more correct level acquisition.

Also, even in the case where the first burst detection is wrong, it is possible to judge whether or not the second burst detection can be performed, and it is possible to avoid acquisition at the level of this wrong timing.

Note that when the second burst detection is not performed, even if a constant time elapses after the first burst detection, by resetting the level acquisition and returning to the first stage of the level acquisition, the Probabilistic detection of subsequently arriving burst signals.

Moreover, when the synchronous transmission mode is supported and a reference signal is inserted for every constant period in the data signal, by precisely adjusting the level acquisition for each reference signal, it is obtained that the electrical signal can be realized more correctly in a multipath environment. Advantages of flat acquisition.

second embodiment

Fig. 26 is a block diagram showing the structure of a second embodiment of a burst synchronous demodulation apparatus to which the FFT timing generating circuit according to the present invention is applied. Also, FIG. 27 is a circuit diagram of a specific structural example of the burst detector and timing controller of FIG. 26 according to the second embodiment of the present invention.

The second embodiment differs from the first embodiment explained above in that a frame synchronization function is added to the burst detector and the timing controller.

Specifically, in the second embodiment, by calculating the cross-correlation between the frame synchronization data (already known) and the input data, detection is performed only for the peak value that is in the detection window and exceeds the detection threshold, and after the synchronization is established according to The detection window is set by the frame period counted by the reference clock on the receiving side (mobile station side), and thus constitutes a burst synchronization system with high adaptability and stability, realizing more optimal demodulation timing of the received signal.

In the second embodiment, a timing controller 110A is provided with a frame synchronization circuit 11004 in addition to the structure of FIG. 14 .

The basic principles of the frame synchronization system of the second embodiment in FIG. 26 and FIG. 27 and the specific structures and functions of newly added components will be described in sequence below.

In order for this frame synchronization system to have such operating conditions, it is necessary that:

A) The frame period of the sender (base station side) is faithfully reproduced at the receiver (mobile station side), and

B) Realizing higher adaptability to base station frame cycle changes.

To satisfy condition A) it is necessary to obtain an average value of shifts in frame synchronization timing over many frames.

The offset that can actually be detected in each frame is in units of 1 clock cycle, but if multiple offsets are combined and averaged, the synchronization at the sender (base station side) can be performed with less than a fractional accuracy regeneration.

However, according to condition B), adaptation to frame period changes on the base station side is not possible. This is because, even if a large offset is input to the averaging circuit, the large offset cannot be directly reflected in the averaging result.

Therefore, if a correlation value exceeding a threshold is obtained, its peak timing is directly used to correct the frame counter itself.

If the amount of change of the frame period per frame is less than half the detection window width, adaptation is possible as long as the correlation can be detected.

FIG. 28 is a block diagram showing an example of the configuration of the frame synchronization circuit of FIG. 27. FIG.

As shown in FIG. 28, the frame synchronization circuit 11004 has a peak detection circuit 201, a synchronization determination circuit 202, a frame period counter 203, an average value circuit 204, and an adder 205 as a correction value setting circuit.

The peak detection circuit 201 receives as input the cross-correlation power CCP formed by the cross-correlation absolute value calculation circuit 10916 of the burst detector 109A, only for the detection window DW centered on the expected timing set by the frame period counter 203 And a value exceeding the threshold th cc performs peak detection, and the shift between the expected timing and the peak detection position is output to the average value circuit 204 as a signal S106.

Moreover, when detecting a peak in the detection window DW, when the peak does not exceed the threshold th_cc (when lower than the threshold), the peak detection circuit 204 judges that no correlation is detected and does not indicate the offset The signal S201 is output to the average value circuit 204.

Also, when the first frame sync is captured, the peak detection circuit 201 detects the correlation peak with the detection window always open and starts control, considering the time when the detection threshold th_cc first exceeds is the sync to be detected.

The synchronization determination circuit 202 receives the output signal S201a of the peak detection circuit 201 and determines whether synchronization is detected. When a sync is detected, it sets the frame period counter 203, eg by the output signal 201a of the peak detection circuit 201, to a count (eg 0) of the expected timing of the sync detection.

The frame period counter 203 is a counter that counts the frame period using the local reference clock, uses the set count value as the operation period, and generates the window timing of the detection window DW to instruct the peak detection circuit 201 according to the operation period.

Note that the detection window is set based on the frame period counted by the reference clock on the receiving side (mobile station side) after synchronization is established.

Also, the frame period counter 203 is loaded with a correction value by the output of the adder 205 as a signal S205, and the count value is corrected.

Then, the frame period counter 203 outputs a signal S203 to the timing counter 11003A so that the output timing of the FFT timing signal TFFT is finely adjusted from the expected timing based on the corrected count.

The averaging circuit 204 averages the deviation between the peak detection result of the frame synchronization input as the signal S201 from the peak detection circuit 201 and the expected timing of the synchronization detection from the frame period counter 203, and outputs the result to the adder 205 As the correction value S204.

The averaging circuit 204 includes an accumulation circuit, using a determined range of the upper bits (integer part) in the output as the first correction value ADJ1, accumulating the lower bits (decimal fractions) obtained by subtracting the upper bits including the sign by the accumulation circuit for each frame. part) part, a correction value of the second correction value ADJ2, eg, ±1, is added to the first correction value ADJ1 corresponding to the carry period, and the result is output to the adder 205 as a correction value S204.

FIG. 29 is a circuit diagram showing an example of the configuration of the averaging circuit 204 of FIG. 28 .

As shown in FIG. 29, the average value circuit 204 has delay units 2041 and 2042, adders 2043, 2044, and 2045, amplifiers 2046 and 2047, an absolute value calculation circuit 2048, selectors 2049 and 2050, and a numerically controlled oscillator (NCO). 2051.

Delay units 2041 and 2042, adders 2043 and 2044, and amplifiers 2046 and 2047 form an integrated circuit.

The averaging circuit 204 of FIG. 29 is a case where the offset value is signed 8 bits and the output of the averaging circuit 204 is signed 17 bits.

Depending on both the direct and integral gain settings of the integrated circuit, if the 7 upper bits are considered to be the "integer" part, the result is a maximum displacement of 9 bits. This equates to an average of about 500 runs.

Offsets below the decimal point are then added together by inputting the low bit portion into a numerically controlled oscillator (NCO) 2051 . When it reaches one clock cycle, it is added to the integer part in the adder 2045 to form the corrected data S204.

In the above example, with this structure, the reference clock error between the transmitter (base station) and receiver (mobile station) can be corrected with an accuracy of about 1/1000 of one clock cycle.

This means that frame synchronization is maintained as usual even in transmission conditions where frame synchronization correlation detection cannot be performed for several hundred consecutive frames. After the transmission condition is restored, it is possible to switch to the transmission/reception operation immediately.

FIG. 30 is a circuit diagram showing an example of the configuration of the numerically controlled oscillator (NCO) of FIG. 29 .

As shown in FIG. 30 , this numerically controlled oscillator 2051 has an adder 20511 , flip-flops (FF) 20512 and 20513 , and an overflow detection circuit 20514 .

That is, the numerically controlled oscillator 2051 is composed of an integrated circuit having the same bit width as the input bit width.

FIG. 31A and FIG. 31B are diagrams showing states of accumulating low bits.

FIG. 31A shows the case where the input ncoin is greater than 0, and FIG. 31B shows the case where the input ncoin is less than 0.

When a symbol is given and the 11-bit input ncom is greater than 0, the input ncoin is "010 (hexadecimal)" and "100 (hexadecimal)", and when the input ncoin is less than 0, the input ncoin is "101 (hexadecimal)" and "011 (hexadecimal)".

Then, when overflowing and crossing zero, a carry is output as the second correction value ADJ2 (±1).

FIG. 32 is a schematic diagram showing a state of overflow detection of the numerically controlled oscillator of FIG. 30 .

As shown in FIG. 32 , the second correction value ADJ2 is 0 by default.

In the case of "010", the input ncoin[10] is 0, the output nco[10] of the flip-flop 20512 is 1, and the output ovf of the flip-flop 20513 is 0. The state of nco in this case becomes ncoin>0 and nco overflows, so the second correction value ADJ2 becomes +1.

In the case of "011", the input ncoin[10] is 1, the output nco[10] of the flip-flop 20512 is 1, and the output ovf of the flip-flop 20513 is 0. The state of nco in this case is ncoin<0 and nco crosses zero, so the second correction value ADJ2 becomes -1.

In the "100" case, the input ncoin[10] is 0, the output nco[10] of the flip-flop 20512 is 0, and the output ovf of the flip-flop 20513 is 1. The state of nco in this case is ncoin>0 and nco crosses zero, so the second correction value ADJ2 becomes +1.

In the case of "101", the input ncoin[10] is 1, the output nco[10] of the flip-flop 20512 is 0, and the output ovf of the flip-flop 20513 is 1. The state of nco in this case is ncoin<0 and nco underflows, so the second correction value ADJ2 becomes -1.

The adder 205 adds the correction value of the averaging circuit 204 to a reference period, and sets the result in accordance with the correction value of the frame period of the frame period counter 203 as its count.

The operation of the frame synchronization circuit 11004 of FIG. 28 is described next with reference to FIGS. 33A to 33D , FIGS. 34A to 34D and FIGS. 35A to 35D .

33A to 33D and FIGS. 34A to 34D are timing charts showing an example of operation timing of frame synchronization according to the second embodiment.

Note that FIG. 33A shows the detection window DTW, FIG. 33B shows the cross-correlation power CCP, FIG. 33C shows the signal S201 indicating the offset, and FIG. 33D shows the count value CNT of the frame period counter 203.

Similarly, FIG. 34A shows the detection window DTW, FIG. 34B shows the cross-correlation power CCP, FIG. 34C shows the signal S201 indicating the offset, and FIG. 34D shows the count value CNT of the frame period counter 203.

35A to 35D are timing charts showing an example of operation timing at the time of frame synchronization initial capture according to the second embodiment of the present invention.

Fig. 35A shows the detection window DTW, Fig. 35B shows the cross-correlation power CCP, Fig. 35C shows a consecutive sync number CSN, and Fig. 35D shows the sync flag FLG.

First, the operation of frame synchronization will be described with reference to Figs. 33A to 33D.

In this case, as shown in FIGS. 33A and 33D , the detection window DTW is set to a width of 7 clock cycles centered on the count value 100.

In this example, as shown in FIG. 33B and FIG. 33D , the peak value of the actual cross-correlation power (correlation value) CCP is obtained not at the count value 100, but at a time when the peak value detection circuit 201 is shifted from 100 by 2 clock cycles. Obtained in 98 places.

This means that the frame period counted by the base station's reference clock is longer than the frame period counted by the mobile station's side reference clock. That is, the crystal oscillation frequency on the mobile station side is high.

In this case, if the value of the frame counter +2 is realized in the next frame, a correlation peak is ideally obtained at the same position 98 in the next frame.

The offset +2 is input to the averaging circuit 204 as a signal S201. The correction value approaches +2 from 0 in the direction in which the number of received frames increases.

Thereby, peak detection of the correlation value can be obtained at the count value of 100 at the expected timing.

Next, the operation of frame synchronization will be described with reference to FIGS. 34A to 34D. The operation in case the correlation value in the detection window does not exceed the threshold value is shown.

This state occurs when, for example, reception conditions temporarily deteriorate.

In this case, the correlation peaks in the detection window DTW are not necessarily important.

Control of the frame cycle counter based on such peak detection timing becomes a cause of frame synchronization shift.

For this reason, if the correlation value does not exceed the threshold value, the count value of the frame period counter 203 is not corrected and no data is input to the averaging circuit 204 .

Subsequently, the operation at the time of initial capture of synchronization will be described with reference to FIGS. 35A to 35D .

When the first frame sync is captured, the peak of the cross-correlation value is detected with the detection window always open, and the time when the threshold is first exceeded is considered as the time of sync detection. In this example, the synchronization judging circuit 20 judges that synchronization is established using three consecutive synchronization detections.

If the peak value of the correlation value can be detected at this timing in the next detection, frame synchronization is obtained, and if the correlation cannot be continuously detected at the same timing, the first detection is considered to be an erroneous detection, and as As shown in Fig. 35C, return to the initial correlation detection waiting mode.

According to this second embodiment, in addition to the effects of the first embodiment described above, in wireless communication where the channel state is unstable, frame synchronization once established can be maintained for a relatively long period.

Furthermore, when the frame period of the base station has to be adapted to another system, such as in the Wireless 1394 system, there is an advantage that performance and adaptability of synchronization accuracy which are inherently contradictory can be achieved.

As a result, it is possible to set an optimal FFT timing regardless of the channel state.

Note that in the second embodiment described above, the case of using one threshold as the threshold for peak detection was explained as an example, but various modifications can be made, such as using a plurality of thresholds in the averaging circuit to control the setting of the counter and Offset loading.

Better control is also possible, such as setting a counter or loading an offset using the first threshold and a second threshold less than the first threshold when this correlation value peak is greater than the first threshold, and when it is less than the second threshold Does not set a counter but loads an offset.

Industrial Applicability

Since the demodulation timing generation circuit and the demodulation device according to the present invention can set the optimal FFT timing regardless of the channel state, the width of the detection window can be changed according to the conditions, the window width can be set according to the reception conditions, and the corresponding window width can be efficiently set. The optimized FFT timing based on the channel can be used in wireless communication systems etc. that receive a radio signal modulated by, for example, OFDM modulation method and having a preamble value added to the modulated packet signal.

Furthermore, since the demodulation timing generation circuit and demodulation apparatus of the present invention can continuously maintain the once-established frame synchronization for a long time, it can be used in a wireless communication system in which the channel state is unstable.

Moreover, since the demodulation timing generation circuit and demodulation device of the present invention can realize the inherently contradictory synchronization accuracy performance and adaptability, it can be used in a wireless communication system in which the frame cycle of the base station must be adapted to other systems, such as being used in For Wireless 1394 systems.

Claims (13)

1. A demodulation timing generating circuit for generating a timing signal for initiating demodulation of a received signal having a frame synchronization signal added to a header portion of a data symbol, the burst portion of which is used as a synchronization training signal, The circuit consists of: a burst detector for performing correlation operations in the burst portion of the frame sync signal; a peak detection circuit for performing peak detection of relative power by the burst detection unit, detecting a peak in a detection window centered around an expected timing and exceeding a detection threshold, and outputting an indication of the expected timing and a peak detection position The offset signal between; a frame period counter for counting a frame period by a reference clock, the counter of which uses the set count as an operation period, generates window timing for instructing the detection window of the peak detection circuit according to the operation period, and generates a window timing based on the set count The timing of the expected timing is used to instruct the output of the timing signal; an average value circuit for averaging a deviation between a result of peak detection of frame synchronization by the peak detection circuit and an expected timing of synchronization detection by the frame period counter, and outputting the average result as a correction value; and A correction value setting circuit for setting a period of correction of the correction value of the average value circuit as a count value to the frame period counter. 2. The demodulation timing generation circuit according to claim 1, wherein when the peak detection circuit performs peak detection in the detection window and when its peak value does not exceed a detection threshold, it is judged that no correlation is detected and the indication is not shifted The signal output to the averaging circuit. 3. The demodulation timing generation circuit according to claim 1, wherein when the first frame sync is captured, the peak detection circuit detects the relevant peak in the state in which the detection window is always opened, and considers that the first Synchronization is detected at points beyond the threshold. 4. According to the demodulation timing generating circuit of claim 3, further comprising: a synchronization judging circuit for judging whether or not synchronization is detected upon receiving the output signal of the peak detection circuit, and setting a count of an expected timing of synchronization detection of the frame period counter by the output signal of the peak detection circuit in a case where synchronization is detected value. 5. according to the demodulation timing generation circuit of claim 1, wherein this mean value circuit comprises integration circuit, use the upper bit in the output, i.e. the certain range of the integer part as the first correction value, accumulated by the accumulation circuit and subtracted by each frame The low bits including the sign obtained by removing the high bits, ie the fractional part, add a second correction value to the first correction value corresponding to the transfer period, and output the result as a correction value to the correction value setting circuit. 6. The demodulation timing generating circuit according to claim 1, wherein the burst detector performs a cross-correlation operation on the reference signal portion of the latter half of the burst portion of the received signal. 7. Demodulation means for generating a timing signal for initiating demodulation of a received signal having a frame synchronization signal added to the header portion of a data symbol, the burst portion of which serves as a synchronization training signal, the demodulation Tuning devices include: a burst detector for performing correlation operations in the burst portion of the frame sync signal; a peak detection circuit for performing peak detection of the relevant power by the burst pulse detection unit, detecting a peak only in a detection window centered around an expected timing and exceeding a detection threshold, and outputting an output indicative of the expected timing and the peak A signal to detect an offset between positions; a frame period counter for counting a frame period by a reference clock, the counter of which uses the set count as an operation period, generates window timing for instructing the detection window of the peak detection circuit according to the operation period, and generates a window timing based on the set count The timing of the expected timing to command the output of the timing signal; an average value circuit for averaging a deviation between a result of peak detection of frame synchronization by the peak detection circuit and an expected timing of synchronization detection by the frame period counter, and outputting the average result as a correction value; a correction value setting circuit for setting a period corrected by the correction value of the average value circuit as a count value to the frame period counter; and A demodulation unit for performing Fourier transform on the received signal, and demodulating the received signal when receiving a timing signal according to an instruction output from the frame period counter. 8. The demodulation device according to claim 7, wherein when the peak detection circuit performs peak detection in the detection window and when its peak value does not exceed the detection threshold, it judges that no correlation is detected and does not indicate the offset The signal is output to this averaging circuit. 9. The demodulation device according to claim 7, wherein when the first frame sync is captured, the peak detection circuit detects the relevant peak in the state where the detection window is always opened and considers that the peak first exceeds the threshold Sync detected. 10. The demodulation device according to claim 9, further comprising: a synchronous judging circuit for judging whether synchronism is detected when receiving an output signal of a peak detection circuit, and in the case of synchronous detection by the peak detection circuit Output signal that sets the count value of the expected timing of synchronization detection of this frame period counter. 11. according to the demodulation apparatus of claim 7, wherein this average value circuit comprises integration circuit, uses the upper bit in the output, i.e. the determined range of the integer part as the first correction value, is accumulated by the accumulation circuit and subtracts the The lower bits including the sign obtained by the upper bits, ie, the fractional part, add a second correction value to the first correction value corresponding to its transfer period, and output the result as a correction value to the correction value setting circuit. 12. The demodulation apparatus according to claim 7, wherein the burst detector performs a cross-correlation operation on the reference signal portion of the second half of the burst portion of the received signal. 13. The demodulation apparatus according to claim 7, wherein the reception signal is modulated according to an orthogonal frequency division multiplexing method.

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