CN113345846B - Package structure and method for manufacturing package structure - Google Patents
Package structure and method for manufacturing package structure Download PDFInfo
- Publication number
- CN113345846B CN113345846B CN202110620047.8A CN202110620047A CN113345846B CN 113345846 B CN113345846 B CN 113345846B CN 202110620047 A CN202110620047 A CN 202110620047A CN 113345846 B CN113345846 B CN 113345846B
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- solid frame
- interlayer
- structure layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/54—Providing fillings in containers, e.g. gas fillings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Dispersion Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The present disclosure relates to a package structure, including a substrate; the chip is arranged above the substrate in a stacking manner along the thickness direction of the substrate, and one surface of the chip is provided with a lug; the interlayer is arranged between the substrate and the chips and/or between two adjacent chips; wherein, the orthographic projection area of the interlayer on the substrate is larger than that of the chip on the substrate. The intermediate layer in this disclosure sets up between base plate and chip, and/or, sets up between two adjacent chips, and the orthographic projection area of intermediate layer on the base plate is greater than the orthographic projection area of chip on the base plate, and the matching nature of the thermal expansion coefficient between intermediate layer and the chip is better for produced heat can scatter through the intermediate layer rapidly when the chip moves, has effectively promoted the radiating effect of chip.
Description
Technical Field
The present disclosure relates to the field of semiconductor packaging technology, and in particular, to a package structure and a method for manufacturing the same.
Background
Dynamic Random Access Memory (DRAM) is the most common system Memory.
During the chip packaging process, a Non-conductive Film (NCF) is usually disposed between the chip and the substrate or between the chip and the chip to form a physical connection.
NCF is made by mixing a resin material with a Filler (Filler). The conventional NCF is liable to generate voids (void) during operations between chips and a substrate, and between chips, has a poor heat dissipation effect, is mismatched with a Coefficient of Thermal Expansion (CTE) of a chip or a substrate, and is further liable to cause adhesive overflow during thermal-Compression bonding (TCB), thereby affecting reliability of a packaged product.
Disclosure of Invention
It is an object of the present disclosure to provide a package structure and a method for manufacturing the package structure to solve the above technical problems.
According to a first aspect of the embodiments of the present disclosure, there is provided a package structure, including:
a substrate;
the chip is arranged above the substrate in a stacking mode along the thickness direction of the substrate, and a bump is arranged on one surface of the chip;
the interlayer is arranged between the substrate and the chips and/or between two adjacent chips; wherein an orthographic projection area of the interlayer on the substrate is larger than an orthographic projection area of the chip on the substrate.
Optionally, the interlayer is of a frame structure, wherein the interlayer includes a package body and a filling material, and the filling material is accommodated in an accommodating area formed by the package body.
Optionally, the package body includes a solid frame, and at least one grid structure layer connected to the solid frame and located inside the solid frame;
the at least one grid structure layer is stacked along the thickness direction of the substrate.
Optionally, an orthographic projection area of the grid structure layer on the substrate is smaller than an orthographic projection area of the chip on the substrate.
Optionally, along the thickness direction of the substrate, a protrusion is formed on the upper surface of the solid frame, and/or a protrusion is formed on the lower surface of the solid frame, so that a step difference is formed between the solid frame and the protrusion.
Optionally, an orthographic projection area of the grid structure layer on the substrate is equal to an orthographic projection area of the chip on the substrate.
Optionally, the grid structure layer is plate-shaped, and along the thickness direction of the substrate, the grid structure layer is lower than the upper surface of the solid frame; and/or the grid structure layer is higher than the lower surface of the solid frame body.
Optionally, the grid structure layer is arc-shaped, and along the thickness direction of the substrate, the grid structure layer is flush with the upper surface of the solid frame body; and/or the grid structure layer is flush with the lower surface of the solid frame body.
Optionally, the solid frame and the at least one grid structure layer are of an integral structure.
Optionally, the height of the solid frame body in the thickness direction of the substrate is greater than a preset height;
the preset height is a bonding height between the substrate and the chip, or a bonding height between two adjacent chips.
Optionally, the solid frame is a rectangular frame.
Optionally, a pad is disposed on the substrate, and the bump penetrates through the frame structure through the mesh structure layer and is electrically connected to the pad.
According to a second aspect of embodiments of the present disclosure, there is provided a memory device comprising the package structure as described above.
According to a third aspect of embodiments of the present disclosure, there is provided a method for manufacturing a package structure, comprising:
providing a substrate;
providing at least one chip, and stacking the at least one chip above the substrate along the thickness direction of the substrate;
disposing an interlayer between the substrate and the chips, and/or disposing an interlayer between two adjacent chips; wherein an orthographic projection area of the interlayer on the substrate is larger than an orthographic projection area of the chip on the substrate.
Optionally, forming a package body;
providing a filling material, and filling the filling material into the accommodating area formed by the packaging body to form the interlayer; wherein the interlayer is in a frame structure.
Optionally, forming a solid frame;
at least one grid structure layer is formed on the inner side of the solid frame body; the at least one grid structure layer is stacked along the thickness direction of the substrate.
Optionally, the solid frame is integrally formed with the at least one grid structure layer.
The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects: the intermediate layer in this disclosure sets up between base plate and chip, and/or, sets up between two adjacent chips, and the orthographic projection area of intermediate layer on the base plate is greater than the orthographic projection area of chip on the base plate, and the matching nature of the thermal expansion coefficient between intermediate layer and the chip is better for produced heat can scatter through the intermediate layer rapidly when the chip moves, has effectively promoted the radiating effect of chip.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic longitudinal cross-sectional view of a package structure shown in accordance with an example embodiment.
Fig. 2 is a schematic longitudinal cross-sectional view of a package structure shown in accordance with an example embodiment.
Fig. 3 is a schematic structural diagram of the package body shown in fig. 1.
Fig. 4 is a schematic longitudinal cross-sectional view of a package structure shown in accordance with an example embodiment.
Fig. 5 is a schematic structural diagram of the package body shown in fig. 4.
Fig. 6 is a schematic longitudinal cross-sectional view of a package structure shown in accordance with an example embodiment.
Fig. 7 is a schematic structural diagram of the package body shown in fig. 6.
Fig. 8 is a flow diagram illustrating a method for fabricating a package structure according to an example embodiment.
Fig. 9 is a flow diagram illustrating a method for fabricating a package structure according to an example embodiment.
Reference numerals:
1: a substrate; 11: a carrier substrate; 12: a package substrate; 121: a pad; 13: a pad; 14: a groove;
2: an interlayer; a first interlayer 2A; a second interlayer 2B;
21: a package body; 22: a filler material; 211: an accommodating area; 212: a solid frame body; 213: a grid structure layer; 2121: a boss portion;
3: a chip; 31: a substrate; 32: a circuit layer; 33: a bump; 333: a solder ball;
3A: a first chip; 3B: a second chip; 331: a first bump; 332: and a second bump.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
The present disclosure provides a package structure including a substrate, an interlayer, and at least one chip. At least one chip is arranged above the substrate in a stacking mode along the thickness direction of the substrate, and a lug is arranged on one surface of the chip. The interlayer is arranged between the substrate and the chips and/or between two adjacent chips. Wherein, the orthographic projection area of intermediate layer on the base plate is greater than the orthographic projection area of chip on the base plate, and the matching nature of the thermal expansion coefficient between intermediate layer and the chip is better for produced heat can disperse through the intermediate layer rapidly when the chip operation, has effectively promoted the radiating effect of chip.
As shown in fig. 1, a package structure includes a substrate 1, an interlayer 2, and a chip 3. The interlayer 2 is bonded to the chip 3, and the two are combined into a whole and then stacked on the substrate 1. A hot press is applied to the chip 3 so that the chip 3 forms a physical connection with the substrate 1 through the interlayer 2.
Wherein, the orthographic projection area of the interlayer 2 on the substrate 1 is larger than that of the chip 3 on the substrate 1, the contact area of the chip 3 and the interlayer 2 is increased, and the heat dissipation effect of the chip 3 is improved. The coefficient of thermal expansion (CTE for short) between the interlayer 2 and the chip 3 has good matching performance, and heat generated by the chip 3 can be transferred to the interlayer 2 in the running state of the chip 3, so that the heat is rapidly dispersed, the heat dissipation efficiency of the chip 3 is improved, and the performance of the chip 3 is ensured.
The chips 3 are stacked on the substrate 1 in the thickness direction of the substrate 1 (see the Y-axis direction shown in fig. 1). The chip 3 may be a memory chip such as SRAM, DRAM, or MARM.
The chip 3 may include a substrate 31, and a circuit layer 32 formed on the substrate 31. The substrate 31 may be a single crystal silicon, glass, or sapphire substrate, but the embodiment is not limited thereto.
One side of the chip 3 is provided with bumps 33, and the circuit layer 32 may be connected to the bumps 33 in a wired manner to achieve electrical connection. One end of the bump 33 is mounted to the chip 3, and the other end of the bump 33 is electrically connected to the substrate 1 through the interlayer 2. The bump 33 may be made of a conductive material such as gold, silver, platinum, copper, tin, or a combination of any of these conductive materials, and is formed by chemical vapor deposition, physical vapor deposition, electroplating, or the like.
The substrate 1 includes a carrier substrate 11 and a package substrate 12, the carrier substrate 11 may be a Circuit Board (PCB) with an integrated Circuit, and the package substrate 12 is soldered to the carrier substrate 11 through a pad 121.
The pad 121 may be made of a metal material, and may be made of copper, aluminum, tungsten, or other metal material having a conductive function. The number of the pads 121 may be plural and may be rectangular, circular, or other shapes. Various electronic components can be soldered to the package substrate 12 to implement different functions.
In order to electrically connect the chip 3 and the substrate 1, the substrate 1 is provided with a pad 13. The substrate 1 is etched, so that a groove 14 is formed on the substrate 1, and the bonding pad 13 is placed in the groove 14, so that the area where the bonding pad 13 is located is in an exposed state. When the chip 3 is stacked on the surface of the substrate 1, the bump 33 of the chip 3 can extend into the groove 14 to form an electrical connection with the pad 13, and the pad 13 is electrically connected to the substrate 1, so as to realize signal transmission of the chip 3.
The other end of the bump 33 is provided with a solder ball 333, and the bump 33 is electrically connected to the pad 13 on the substrate 1 through the solder ball 333.
As shown in fig. 2, a package structure further includes a substrate 1, a plurality of interlayers 2, and a plurality of chips 3. The interlayer 2 is provided between the substrate 1 and the chips 3, and between every adjacent two chips 3. The detailed structure of the substrate 1 and the connection manner between the substrate and the interlayer 2 and the chip 3 have been described in detail in the above embodiments, and thus, the detailed description is not repeated here.
As for the arrangement between the chip 3 and the interlayer 2, two are exemplified below.
In one example, chip 3 includes a first chip 3A and a second chip 3B, and interlayer 2 includes a first interlayer 2A and a second interlayer 2B. The first interlayer 2A is attached to one surface of the first chip 3A, and after the first interlayer and the first chip are combined into a whole, the first interlayer and the first chip are stacked on the substrate 1, and hot pressing is applied to the first chip 3A, so that the first chip 3A is physically connected with the substrate 1 through the first interlayer 2A. The second interlayer 2B is attached to one surface of the second chip 3B, the two are combined into a whole, the second interlayer is stacked on the other surface of the first chip 3A, and hot pressing is applied to the second chip 3B, so that the second chip 3B is physically connected with the first chip 3A through the second interlayer 2B.
One surface of the first chip 3A is provided with a first bump 331, the first bump 331 penetrates through the first interlayer 2A to be connected with the substrate 1, and the first chip 3A is electrically connected with the substrate 1 through the first bump 331. One side of the second chip 3B is provided with a second bump 332, and the second bump 332 sequentially passes through the second interlayer 2B and the first chip 3A and is connected to the first bump 331, so as to interconnect the first chip 3A and the second chip 3B.
A through-Silicon Via (TSV) structure is disposed in the first chip 3A, and the TSV structure penetrates through the first chip 3A along a thickness direction of the substrate 1 (see a Y-axis direction shown in fig. 2), the second bump 332 is connected to the TSV structure, and the TSV structure is connected to the first bump 331, so that the first chip 3A and the second chip 3B are interconnected. The TSV structure can be formed through a through hole in an etching mode, and a conductive material is filled in the through hole to form the TSV structure.
Here, it should be noted that the first chip 3A and the second chip 3B are defined for distinguishing and exemplarily explaining the chip 3 above the substrate 1. The first chip 3A and the second chip 3B do not limit the present application, and the chips 3 are not limited to one, two, three, or the like, and are specifically designed. And the interconnection between each adjacent two chips 3 is as described above.
In this embodiment, a plurality of chips 3 are provided, thereby realizing various functions of the package structure. Every chip 3 can correspond a function, all be provided with an intermediate layer 2 between every two adjacent chips 3, guarantee packaging structure under the user state, produced heat when every chip 3 moves, can both transmit intermediate layer 2 that corresponds, the orthographic projection area of intermediate layer 2 on base plate 1 is greater than the orthographic projection area of chip 3 on base plate 1, chip 3 and intermediate layer 2's area of contact has been increased, the radiating effect of chip 3 has been promoted, extension chip 3's life.
As shown in fig. 1 and 3, the interlayer 2 proposed by the present disclosure is of a frame structure. The interlayer 2 includes a package body 21 and a filling material 22, and the filling material 22 is accommodated in an accommodating area 211 formed by the package body 21.
In the process of chip 3 mounting, the interlayer 2 is attached to one surface of the chip 3 and is disposed on the substrate 1 or another chip 3, and is integrated by hot pressing. When the temperature rises, the filling material 22 becomes liquid and has fluidity, so that it can smoothly fill the gap between the package body 21 and the chip 3, the gap between the package body 21 and the substrate 1, and the gap between the package body 21 and the groove 14, and finally the assembly of the package structure is completed. The package body 21 is disposed outside the filling material 22, and can intercept the liquid filling material 22, thereby effectively avoiding the occurrence of glue overflow.
The package body 21 is made of an inorganic material and has good thermal conductivity. Under 3 running state of chip, can produce a large amount of heats, and the matching nature of the thermal expansion coefficient between packaging body 21 and the chip 3 is better, and the heat of chip 3 can be dispersed fast through packaging body 21, promotes the radiating effect, guarantees chip 3's operating performance.
The filling material 22 is made of resin adhesive material, and is in a liquid state when combined with the package body 21. The filling material 22 is accommodated in the accommodating area 211 formed by the package body 21, and the process integration is performed to change the filling material 22 into a solid state, so that the solid filling material 22 and the package body 21 are integrated into a whole, and finally the interlayer 2 is formed.
As shown in fig. 1 and fig. 3, the package body 21 of the present disclosure includes a solid frame 212 and a grid structure layer 213 connected to the solid frame 212 and located inside the solid frame 212, and the solid frame 212 and the grid structure layer 213 are an integral structure, which can simplify the process steps and reduce the production cost.
The solid frame 212 is a rectangular frame, an area enclosed by the solid frame 212 is the accommodation area 211, and the grid structure layer 213 is disposed in the accommodation area 211. Wherein, the orthographic projection area of the grid structure layer 213 on the substrate 1 is equal to the orthographic projection area of the chip 3 on the substrate 1, and the bump 33 passes through the grid structure layer 213 to be electrically connected with the pad 13.
The grid structure layer 213 is plate-shaped, and in the mounted state, along the thickness direction of the substrate 1 (refer to the Y-axis direction shown in fig. 1), the upper surface of the grid structure layer 213 is lower than the upper surface of the solid frame 212, and the lower surface of the grid structure layer 213 is higher than the lower surface of the solid frame 212, so that a height difference is formed between the solid frame 212 and the grid structure layer 213. The partial structure of the chip 3 can be embedded in the accommodating area 211 of the solid frame 212, so that the solid frame 212 can wrap the chip 3 along the circumferential direction, and the phenomenon of glue overflow is avoided. And the chip 3 may be disposed on the surface of the mesh structure layer 213 so that the mesh structure layer 213 can support it.
The upper surface and the lower surface of the solid frame 212 are defined with reference to the illustrated orientation for explaining the present embodiment, and do not limit the present invention.
It should be noted that the grid structure layer 213 proposed by the present disclosure is not limited to one, and may be two, three or more. The package body 21 provided by the present disclosure includes a solid frame 212, and at least one grid structure layer 213 connected to the solid frame 212 and located inside the solid frame 212, where the at least one grid structure layer 213 is stacked along a thickness direction of the substrate 1 (refer to a Y-axis direction shown in fig. 1).
When the package body 21 includes a plurality of grid structure layers 213, an upper surface of the grid structure layer 213 at the uppermost layer is lower than an upper surface of the solid frame 212, and a lower surface of the grid structure layer 213 at the lowermost layer is higher than a lower surface of the solid frame 212, so that a height difference is formed between the solid frame 212 and the grid structure layer 213.
As shown in fig. 4 and 5, the package body 21 provided by the present disclosure includes a solid frame 212 and a grid structure layer 213 connected to the solid frame 212 and located inside the solid frame 212, where the solid frame 212 and the grid structure layer 213 are an integral structure, so as to simplify the process steps and reduce the production cost.
The solid frame 212 is a rectangular frame, an area enclosed by the solid frame 212 is the accommodation area 211, and the grid structure layer 213 is disposed in the accommodation area 211. The area of the grid structure layer 213 projected forward on the substrate 1 is equal to the area of the chip 3 projected forward on the substrate 1, and the bump 33 passes through the grid structure layer 213 and is electrically connected to the pad 13.
The mesh structure layer 213 is arc-shaped, and in the mounted state, the upper surface of the mesh structure layer 213 is flush with the upper surface of the solid frame 212 along the thickness direction of the substrate 1 (see the Y-axis direction shown in fig. 4). In the mounted state, the chip 3 can press the grid structure layer 213 downward, so that the connection between the grid structure layer 213 and the chip 3 is tighter, and the glue overflow is avoided. And the grid structure layer 213 is made of inorganic material and directly contacts with the chip 3, so as to improve the heat dissipation effect of the chip 3.
The upper surface and the lower surface of the solid frame 212 are defined with reference to the illustrated orientation for explaining the present embodiment, and do not limit the present invention.
It should be noted that the grid structure layer 213 proposed by the present disclosure is not limited to one, and may be two, three or more. The package body 21 proposed by the present disclosure includes a solid frame 212, and at least one grid structure layer 213 connected to the solid frame 212 and located inside the solid frame 212, where the at least one grid structure layer 213 is stacked along a thickness direction of the substrate 1 (refer to a Y-axis direction shown in fig. 4).
When the package body 21 includes a plurality of grid structure layers 213, an upper surface of the grid structure layer 213 at the uppermost layer is flush with an upper surface of the solid frame 212, and a lower surface of the grid structure layer 213 at the lowermost layer is flush with a lower surface of the solid frame 212.
As shown in fig. 6 and 7, the package body 21 provided by the present disclosure includes a solid frame 212 and a grid structure layer 213 connected to the solid frame 212 and located inside the solid frame 212, and the solid frame 212 and the grid structure layer 213 are an integral structure, which can simplify the process steps and reduce the production cost.
The solid frame 212 is a rectangular frame, an area enclosed by the solid frame 212 is the accommodation area 211, and the grid structure layer 213 is disposed in the accommodation area 211. The orthographic projection area of the grid structure layer 213 on the substrate 1 is smaller than the orthographic projection area of the chip 3 on the substrate 1 and larger than the orthographic projection area of all the bumps 33 on the substrate 1, so that the bumps 33 can penetrate through the frame structure through the grid structure layer 213 to be electrically connected with the pads 13.
The area of the solid frame 212 projected from the substrate 1 is larger than the area of the chip 3 projected from the substrate 1, and a projection 2121 is formed on the upper surface of the solid frame 212 in the thickness direction of the substrate 1 (see the Y-axis direction shown in fig. 6) so that a step is formed between the solid frame 212 and the projection 2121. The protruding portion 2121 is arranged in a surrounding manner along the circumferential direction, so that the chip 3 can be wrapped by the protruding portion 2121 of the solid frame body 212, and the phenomenon of glue overflow is effectively avoided during the chip 3 mounting process.
The solid frame 212 is matched with the grid structure layer 213, so that on the premise of ensuring the flowability and filling property of the filling material 22, the area of the grid structure layer 213 is reduced, the area of the solid frame 212 is increased, the contact area between the solid frame 212 and the chip 3 is increased, and the heat dissipation effect is further improved.
The upper surface and the lower surface of the solid frame 212 are defined with reference to the illustrated orientation for explaining the present embodiment, and do not limit the present invention.
It should be noted that the grid structure layer 213 proposed by the present disclosure is not limited to one, and may be two, three or more. The package body 21 provided by the present disclosure includes a solid frame 212, and at least one grid structure layer 213 connected to the solid frame 212 and located inside the solid frame 212, where the at least one grid structure layer 213 is stacked along a thickness direction of the substrate 1 (refer to a Y-axis direction shown in fig. 6).
When the package body 21 includes the multi-layer mesh structure layer 213, the upper surface of the solid frame 212 is formed with the protrusion 2121, and the lower surface of the solid frame 212 is also formed with the protrusion 2121, so that a step difference is formed between the solid frame 212 and the protrusion 2121.
As shown in fig. 1, the height of the solid frame 212 in the thickness direction of the substrate 1 (see the Y-axis direction shown in fig. 1) is greater than a predetermined height. The preset height is a bonding height between the substrate 1 and the chip 3, or a bonding height between two adjacent chips 3, so as to further protect a connection portion between the substrate 1 and the chip 3, or a connection portion between two adjacent chips 3. Meanwhile, the thickness of the solid frame body 212 is higher than the bonding height, so that the periphery of the chip 3 is intercepted, and the problem of NCF (non-conductive plasma) glue overflow is solved.
The present disclosure also proposes a memory device, which includes the package structure in any of the above embodiments, and the memory device is SRAM, DRAM, or MARM, etc.
The packaging structure in the storage device can solve the problem of glue overflow in the chip mounting process and fill gaps. Meanwhile, the matching performance and the heat transfer performance of the thermal expansion coefficient of the packaging body of the packaging structure and the chip are enhanced, the heat of the chip can be rapidly dispersed in the operating state of the chip, the heat dissipation effect is improved, and the performance of the storage device is ensured.
In the implementation process, if the filling material overflows to the lateral part of base plate or chip, probably produce the risk of electronic components trouble, when the chip pressfitting was in the base plate, solid framework can intercept the filling material, avoids the filling material to spill over, promotes the security of storage device.
The present disclosure also proposes a method for manufacturing a package structure.
As shown in fig. 1 and 8, a method for manufacturing a package structure includes:
step S110, providing a substrate.
In this step, the substrate 1 is a printed circuit board or a glass substrate.
Step S120, providing chips, and stacking the chips above the substrate along the thickness direction of the substrate.
In this step, as shown in fig. 1, the chip 3 is electrically connected to the substrate 1. Bumps 33 are formed on one surface of the chip 3, and the bumps 33 are made of a conductive material. The substrate 1 is etched with a groove 14, and the bonding pad 13 is disposed in the groove 14, so that the region where the bonding pad 13 is located is exposed. In the mounting state, the bump 33 extends into the groove 14, and the chip 3 is electrically connected with the pad 13 of the substrate 1 through the bump 33, so that signal transmission is realized.
Wherein the chip 3 comprises a substrate 31, the substrate 31 may be made of a silicon material. A circuit layer 32 is formed on one surface of the substrate 31, and the circuit layer 32 is connected to the bump 33 by a wiring method to form an electrical connection.
Before step S120, forming an interlayer disposed between the substrate and the chip; wherein, the orthographic projection area of the interlayer on the substrate is larger than that of the chip on the substrate.
In this step, the interlayer 2 is attached to one surface of the chip 3, and after the two are integrated, the interlayer is stacked on the substrate 1. A hot pressure is applied to the chip 3 so that the chip 3 forms a physical connection with the substrate 1 through the interlayer 2.
The thermal expansion coefficient matching of the interlayer 2 and the chip 3 is good, the orthographic projection area of the interlayer 2 on the substrate 1 is larger than that of the chip 3 on the substrate 1, the contact area between the chip 3 and the interlayer 2 is increased, and the heat dissipation effect of the chip 3 is improved, so that the chip 3 can dissipate heat quickly.
Steps S1201-S1202 may also be included in step S120, wherein,
step S1201, a package body is formed.
In this step, as shown in fig. 1, an inorganic material is provided, and the package body 21 is formed by in-mold molding. The specific form of the package body 21 may be formed by one-step molding with a matching mold, or may be formed by forming a plate-shaped package body 21 and forming the final form of the package body 21 by etching.
Step S1202, providing a filling material, and filling the filling material into the accommodating region formed by the package body to form an interlayer; wherein, the interlayer is of a frame structure.
In this step, as shown in fig. 1, the filling material 22 is a resin adhesive material, the package body 21 is formed with an accommodating area 211, the filling material 22 is in a liquid state, and is accommodated in the accommodating area 211, and the filling material 22 is integrated and cooled through a process, so that the filling material 22 is in a solid state. The filling material 22 is combined with the package body 21 to finally form the interlayer 2 in a frame structure.
When chip 3 paster technology process is carried out, chip 3 and intermediate layer 2 are laminated and are arranged on base plate 1, and chip 3 is fixed on base plate 1 by hot pressing. The filling material 22 in the interlayer 2 becomes liquid and has fluidity, and further fills the gaps between the package body 21 and the chip 3, between the package body and the substrate 1, and between the groove 14 and the package body 21. The package body 21 can intercept the filling material 22, so as to prevent the filling material 22 from overflowing the chip 3 to affect the assembly of the package structure.
Steps S12011-S12012 may also be included in step S1201, wherein,
in step S12011, a solid frame is formed.
In this step, as shown in fig. 1, an inorganic material is supplied, and the solid frame body 212 is formed by in-mold molding. The solid frame 212 is a rectangular frame, and an area enclosed by the rectangular frame is the accommodating area 211.
The thickness of the solid frame 212 is higher than the bonding height between the substrate 1 and the chip 3, so as to intercept the periphery of the chip 3, thereby solving the problem of NCF flash.
Step S12012, a mesh structure layer is formed inside the solid frame.
In this step, as shown in fig. 1, the inner side of the solid frame 212, i.e., the receiving area 211, is provided with a mesh structure layer 213. The grid structure layer 213 may be fabricated separately from the solid frame 212 and assembled with the solid frame 212 in an assembled manner. Alternatively, the solid frame 212 may be integrally formed with the grid structure layer 213, so as to simplify the process flow, shorten the production time, and reduce the labor cost and the production cost.
The mesh structure layer 213 is not limited to the above-mentioned one layer, and the mesh structure layer 213 may be two layers, three layers, or multiple layers. The plurality of mesh structure layers 213 are stacked in the thickness direction of the substrate 1 (see the Y axis shown in fig. 1). The area of the orthographic projection of the grid structure layer 213 on the substrate 1 may be smaller than the area of the orthographic projection of the chip 3 on the substrate 1, or equal to the area of the orthographic projection of the chip 3 on the substrate 1, which is not specifically stated herein.
As shown in fig. 2 and 9, a method for manufacturing a package structure includes:
step S210, providing a substrate.
Step S220 is to provide a plurality of chips, and stack the plurality of chips above the substrate along the thickness direction of the substrate.
In this step, when a plurality of chips 3 are provided, the chips 3 are stacked in order in the thickness direction of the substrate 1.
Before step S220, forming an interlayer disposed between the substrate and the chip and between two adjacent chips; wherein, the orthographic projection area of the interlayer on the substrate is larger than that of the chip on the substrate.
The specific structures and forming manners of the chip 3 and the interlayer 2 have been described in detail in the above embodiments, and are not repeated herein. In the present embodiment, only the arrangement of the plurality of interlayers 2 and the plurality of chips 3 will be explained, and two chips 3 and interlayers 2 are provided as an example.
A first chip 3A is provided, and a first bump 331 is formed on one side of the first chip 3A.
Forming a first interlayer 2A, attaching the first interlayer 2A to one surface of the first chip 3A, and the first bump 331 penetrates the first interlayer 2A. After the two are combined into a whole, they are stacked on the substrate 1, and the first bump 331 is electrically connected to the substrate 1. A hot press is applied to the first chip 3A such that the first chip 3A forms a physical connection with the substrate 1 through the first interlayer 2A. The filling material 22 in the first interlayer 2A is liquid and has fluidity to fill the gap between the package body 21 and the first chip 3A and the gap between the package body 21 and the substrate 1.
A second chip 3B is provided, and a second bump 332 is formed on one surface of the second chip 3B.
Forming a second interlayer 2B, attaching the second interlayer 2B to one surface of the second chip 3B, and the second bump 332 penetrates the second interlayer 2B. After the two are combined into a whole, they are stacked on the first chip 3A, and the second bump 332 passes through the first chip 3A and is electrically connected to the first bump 331. A hot press is applied to the second chip 3B such that the second chip 3B forms a physical connection with the first chip 3A through the second interlayer 2B. The filling material 22 in the second interlayer 2B is in a liquid state and has fluidity so as to fill the gap between the package body 21 and the first chip 3A and the gap between the package body 21 and the second chip 3B.
A plurality of through holes are formed in the first chip 3A by etching, and the through holes correspond to the first bumps 331 one to one. And filling the through hole with a conductive material to form the TSV structure. The first bump 331 and the second bump 332 are respectively connected to the TSV structure to realize interconnection between the first chip 3A and the second chip 3B.
Of course, it is understood that the shape and size of the first chip 3A and the second chip 3B may be the same or different, and are not limited specifically herein.
In the present embodiment, when the plurality of chips 3 are provided, the plurality of chips 3 and the plurality of interlayers 2 are alternately stacked in sequence to form a stacked structure, which realizes various functions of the package structure. And the height of the solid frame 213 is higher than the bonding height between two adjacent chips 3, so as to intercept the filling material 22, and prevent the filling material 22 from overflowing the chips 3 when being in a liquid state, thereby avoiding affecting the overall assembly of the package structure.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (15)
1. A package structure, comprising:
a substrate;
the chip is arranged above the substrate in a stacking mode along the thickness direction of the substrate, and a bump is arranged on one surface of the chip;
the interlayer is arranged between the substrate and the chips and/or between two adjacent chips; wherein an orthographic projection area of the interlayer on the substrate is larger than an orthographic projection area of the chip on the substrate;
the interlayer is of a frame structure and comprises a packaging body and a filling material, and the filling material is contained in a containing area formed by the packaging body.
2. The package structure of claim 1, wherein the package body comprises a solid frame and at least one grid structure layer connected to the solid frame and located inside the solid frame;
the at least one grid structure layer is stacked along the thickness direction of the substrate.
3. The package structure of claim 2, wherein an orthographic area of the grid structure layer on the substrate is smaller than an orthographic area of the chip on the substrate.
4. The package structure according to claim 3, wherein a protrusion is formed on an upper surface side of the solid frame in a thickness direction of the substrate, and/or a protrusion is formed on a lower surface of the solid frame such that a step difference is formed between the solid frame and the protrusion.
5. The package structure of claim 2, wherein an orthographic area of the grid structure layer on the substrate is equal to an orthographic area of the chip on the substrate.
6. The package structure of claim 5, wherein the grid structure layer is plate-shaped and is lower than the upper surface of the solid frame along the thickness direction of the substrate; and/or the grid structure layer is higher than the lower surface of the solid frame body.
7. The package structure of claim 5, wherein the grid structure layer is arc-shaped, and along a thickness direction of the substrate, the grid structure layer is flush with an upper surface of the solid frame; and/or the grid structure layer is flush with the lower surface of the solid frame body.
8. The package structure of claim 2, wherein the solid frame is integral with the at least one grid structure layer.
9. The package structure of claim 2, wherein a height of the solid frame in a thickness direction of the substrate is greater than a predetermined height;
the preset height is a bonding height between the substrate and the chip, or a bonding height between two adjacent chips.
10. The package structure of claim 2, wherein the solid frame is a rectangular frame.
11. The package structure of claim 2, wherein a pad is disposed on the substrate, and the bump is electrically connected to the pad through the frame structure by a mesh structure layer.
12. A memory device, characterized in that it comprises a package structure according to any one of claims 1 to 11.
13. A method for fabricating a package structure, comprising:
providing a substrate;
providing at least one chip, and stacking the at least one chip above the substrate along the thickness direction of the substrate;
disposing an interlayer between the substrate and the chips, and/or disposing an interlayer between two adjacent chips; wherein an orthographic projection area of the interlayer on the substrate is larger than an orthographic projection area of the chip on the substrate;
forming a package body;
providing a filling material, and filling the filling material into the accommodating area formed by the packaging body to form the interlayer; wherein the interlayer is in a frame structure.
14. The method for manufacturing a package structure according to claim 13,
forming a solid frame;
at least one grid structure layer is formed on the inner side of the solid frame body; the at least one grid structure layer is stacked along the thickness direction of the substrate.
15. The method of claim 14, wherein the solid frame is integrally formed with the at least one grid structure layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110620047.8A CN113345846B (en) | 2021-06-03 | 2021-06-03 | Package structure and method for manufacturing package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110620047.8A CN113345846B (en) | 2021-06-03 | 2021-06-03 | Package structure and method for manufacturing package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113345846A CN113345846A (en) | 2021-09-03 |
| CN113345846B true CN113345846B (en) | 2022-03-22 |
Family
ID=77473405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110620047.8A Active CN113345846B (en) | 2021-06-03 | 2021-06-03 | Package structure and method for manufacturing package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113345846B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001267478A (en) * | 2000-03-17 | 2001-09-28 | Hitachi Chem Co Ltd | Method of manufacturing semiconductor device and semiconductor device obtained thereby |
| CN2733595Y (en) * | 2003-05-28 | 2005-10-12 | 雅马哈株式会社 | Lead-frame and semiconductor device using the same |
| JP2009147094A (en) * | 2007-12-14 | 2009-07-02 | Panasonic Corp | Semiconductor device |
| JP2012119485A (en) * | 2010-11-30 | 2012-06-21 | Panasonic Corp | Die-bond junction structure of semiconductor element, sub-mount substrate, light-emitting device using the junction structure or the substrate, lighting equipment using the light-emitting device, and semiconductor element package manufacturing method |
| CN103295926A (en) * | 2013-05-31 | 2013-09-11 | 中国航天科技集团公司第九研究院第七七一研究所 | Interconnection and package method on basis of TSV (through silicon via) chips |
| CN106910723A (en) * | 2015-07-29 | 2017-06-30 | 三星半导体(中国)研究开发有限公司 | Semiconductor package part and the method for manufacturing the semiconductor package part |
| CN111128766A (en) * | 2019-12-20 | 2020-05-08 | 江苏长电科技股份有限公司 | A packaging method to improve warpage |
| CN211045465U (en) * | 2019-08-13 | 2020-07-17 | 徐州致诚会计服务有限公司 | High-power flip L ED packaging structure |
| CN111834355A (en) * | 2019-04-15 | 2020-10-27 | 三星电子株式会社 | Semiconductor packaging |
-
2021
- 2021-06-03 CN CN202110620047.8A patent/CN113345846B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001267478A (en) * | 2000-03-17 | 2001-09-28 | Hitachi Chem Co Ltd | Method of manufacturing semiconductor device and semiconductor device obtained thereby |
| CN2733595Y (en) * | 2003-05-28 | 2005-10-12 | 雅马哈株式会社 | Lead-frame and semiconductor device using the same |
| JP2009147094A (en) * | 2007-12-14 | 2009-07-02 | Panasonic Corp | Semiconductor device |
| JP2012119485A (en) * | 2010-11-30 | 2012-06-21 | Panasonic Corp | Die-bond junction structure of semiconductor element, sub-mount substrate, light-emitting device using the junction structure or the substrate, lighting equipment using the light-emitting device, and semiconductor element package manufacturing method |
| CN103295926A (en) * | 2013-05-31 | 2013-09-11 | 中国航天科技集团公司第九研究院第七七一研究所 | Interconnection and package method on basis of TSV (through silicon via) chips |
| CN106910723A (en) * | 2015-07-29 | 2017-06-30 | 三星半导体(中国)研究开发有限公司 | Semiconductor package part and the method for manufacturing the semiconductor package part |
| CN111834355A (en) * | 2019-04-15 | 2020-10-27 | 三星电子株式会社 | Semiconductor packaging |
| CN211045465U (en) * | 2019-08-13 | 2020-07-17 | 徐州致诚会计服务有限公司 | High-power flip L ED packaging structure |
| CN111128766A (en) * | 2019-12-20 | 2020-05-08 | 江苏长电科技股份有限公司 | A packaging method to improve warpage |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113345846A (en) | 2021-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11437326B2 (en) | Semiconductor package | |
| US9640518B2 (en) | Semiconductor package with package-on-package stacking capability and method of manufacturing the same | |
| US9349711B2 (en) | Semiconductor device with face-to-face chips on interposer and method of manufacturing the same | |
| KR101019793B1 (en) | Semiconductor device and manufacturing method thereof | |
| US8786070B2 (en) | Microelectronic package with stacked microelectronic elements and method for manufacture thereof | |
| US7656015B2 (en) | Packaging substrate having heat-dissipating structure | |
| JP4742079B2 (en) | Wafer level system-in-package and manufacturing method thereof | |
| US20130334698A1 (en) | Microelectronic assembly tolerant to misplacement of microelectronic elements therein | |
| CN112510022B (en) | Electronic packaging and method of manufacturing the same | |
| KR20140130395A (en) | Method of manufacturing semiconductor device | |
| US8274153B2 (en) | Electronic component built-in wiring substrate | |
| JP2010515242A (en) | Flip chip semiconductor package and strip having encapsulant retention structure | |
| US9875949B2 (en) | Electronic package having circuit structure with plurality of metal layers, and fabrication method thereof | |
| US20100290193A1 (en) | Stacked-chip packaging structure and fabrication method thereof | |
| CN102610594A (en) | Stacked semiconductor assembly with heat sink and build-up circuitry | |
| JPH0846085A (en) | Semiconductor device and manufacturing method thereof | |
| US20240136297A1 (en) | Multi-chip interconnection package structure with heat dissipation plate and preparation method thereof | |
| JP2013021058A (en) | Manufacturing method of semiconductor device | |
| KR20230016520A (en) | Semiconductor package | |
| US7763983B2 (en) | Stackable microelectronic device carriers, stacked device carriers and methods of making the same | |
| CN113345846B (en) | Package structure and method for manufacturing package structure | |
| CN115332187A (en) | Package based on interposer | |
| CN110867385A (en) | Packaging structure and preparation method thereof | |
| KR101440340B1 (en) | Supporting device and method for manufacturing semiconductor package using the same | |
| CN115565968A (en) | Packaging structure with stacked multilayer chips and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |