CN113192851B - Wafer packaging method - Google Patents
Wafer packaging method Download PDFInfo
- Publication number
- CN113192851B CN113192851B CN202110476477.7A CN202110476477A CN113192851B CN 113192851 B CN113192851 B CN 113192851B CN 202110476477 A CN202110476477 A CN 202110476477A CN 113192851 B CN113192851 B CN 113192851B
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- wafer
- packaging
- chip
- chips
- separation assembly
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000000926 separation method Methods 0.000 claims abstract description 28
- 239000002245 particle Substances 0.000 claims abstract description 20
- 230000001681 protective effect Effects 0.000 claims abstract description 18
- 239000012528 membrane Substances 0.000 claims description 14
- 235000012431 wafers Nutrition 0.000 claims 13
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 206010036872 Prolonged labour Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000009347 mechanical transmission Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention discloses a wafer packaging method, and relates to the technical field of semiconductor packaging. The packaging method of the wafer comprises the following steps: s1: placing the wafer in a working area of the separation assembly; s2: dicing the wafer into a chipset of individual chips; s3: using the separation assembly to diffuse the chips in the chip set to the periphery so that intervals exist between the adjacent chips; s4: placing the diffused chip set on one side of a protective film; s5: performing plastic packaging on the chip set; s6: removing the protective film; s7: and cutting the chip group after plastic packaging along the interval to form independent packaging particles. The wafer packaging method can package and mold the cut wafer once and then cut the cut wafer into single particles, so that the working time and the cost are reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a wafer packaging method.
Background
In the current semiconductor industry, electronic packaging has become an important aspect of industry development, and the development of packaging technology for decades has made high-density, small-size packaging a mainstream direction of packaging. As electronic products are developed to be thinner, lighter, higher in pin density, and lower in cost, the use of single chip packaging technology has not been able to meet the industrial needs.
The existing packaging method of the ultra-small chip is that after a wafer is cut, a thimble is used for jacking a single chip, and then a suction nozzle is used for taking down the chips from a UV (ultraviolet) die one by one and placing the chips on a frame or a substrate for subsequent packaging operation. Because of the extremely small size of the microminiature chips, tens of thousands of chip particles are often arranged on a wafer, and the traditional piece-by-piece taking method consumes extremely long working hours and has high cost.
Aiming at the problems, a wafer packaging method needs to be developed to solve the problems of long labor consumption and high cost caused by packaging after taking pieces one by one.
Disclosure of Invention
The invention aims to provide a wafer packaging method which can cut a cut wafer into single particles after one-time packaging and molding, thereby reducing working hours and cost.
To achieve the purpose, the invention adopts the following technical scheme:
a wafer packaging method comprises the following steps:
s1: placing the wafer in a working area of the separation assembly;
s2: dicing the wafer into a chipset of individual chips;
s3: using the separation assembly to diffuse the chips in the chip set to the periphery so that intervals exist between the adjacent chips;
s4: placing the diffused chip set on one side of a protective film;
s5: performing plastic packaging on the chip set;
s6: removing the protective film;
s7: and cutting the chip group after plastic packaging along the interval to form independent packaging particles.
Preferably, the separation assembly comprises a plurality of suction nozzles, each suction nozzle is used for sucking one chip, and the plurality of suction nozzles can independently and horizontally move.
Preferably, the suction nozzles are all adsorbed at the center of the corresponding chip.
Preferably, the separation assembly further comprises an expansion membrane, and the suction nozzles are arranged on the expansion membrane at intervals and can uniformly increase the distance between the adjacent suction nozzles along with the expansion of the expansion membrane.
Preferably, the separation assembly includes an elastic film, the chipset is placed on the elastic film in step S1, and the chipset is uniformly spread around by stretching the elastic film around in step S3.
Preferably, the separation assembly further comprises a clamping ring and a stretching ring, the clamping ring can clamp the peripheral ring of the elastic membrane, the stretching ring is arranged in the clamping ring and concentric with the clamping ring, and the stretching ring is abutted with the elastic membrane.
Preferably, when the wafer is cut, the wafer is cut and then cut down to 30% -70% of the thickness of the elastic film.
Preferably, the separation assembly further comprises a baffle plate, the baffle plate is arranged on one side of the elastic film, where the chip set is placed, and when the elastic film stretches, the baffle plate abuts against the chip in the chip set.
Preferably, plasma dicing is used in dicing the wafer.
Preferably, the intervals between adjacent chips are equal in size.
The invention has the beneficial effects that:
the invention provides a wafer packaging method. In the packaging method, the chip groups cut into independent chips are diffused and separated to the periphery by utilizing the separation assembly, so that certain gaps exist between the adjacent chips, then the chip groups are placed on the protective film for plastic packaging, and after the plastic packaging is finished, the plastic-packaged chip groups are cut along the intervals among the chips to form independent packaging particles.
The packaging method provided by the invention does not need to take down the chips one by one, but directly adopts once packaging and forming and then cuts into single particles. Greatly reduces the manufacturing cost and the processing time of the ultra-small packaged particles in the traditional process.
Drawings
FIG. 1 is a flow chart of a method for packaging a wafer provided by the invention;
FIG. 2 is a schematic diagram of a wafer according to the present invention;
FIG. 3 is a schematic view of a separation assembly according to a first embodiment of the present invention;
fig. 4 is a schematic structural view of a separation assembly according to a second embodiment of the present invention.
In the figure:
1. a wafer; 2. a separation assembly; 3. a protective film;
11. a chipset; 21. a suction nozzle; 22. expanding the membrane; 23. an elastic film; 24. a clamping ring; 25. a tension ring;
111. and a chip.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Wherein the terms "first position" and "second position" are two different positions.
Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "fixed" are to be construed broadly, and may be, for example, either fixed or removable; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include the first feature and the second feature being in direct contact, or may include the first feature and the second feature not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.
First embodiment
The embodiment provides a wafer packaging method. As shown in fig. 1 and 2, the wafer packaging method includes the following steps:
s1: the wafer 1 is placed in the working area of the separation assembly 2.
S2: the wafer 1 is diced into chip sets 11 consisting of individual chips 111.
This step requires that the wafer 1 is cut into chips 111 of corresponding sizes according to the final required chip 111 size to form the chip set 11, and no gaps exist between the chips 111, which are all in contact state.
S3: the separation assembly 2 is used to spread the chips 111 in the chip set 11 around so that there is a space between adjacent chips 111.
The spacing between the chips 111 is determined by the size of the package particles at the time of molding, and each spacing should be at least twice the distance between the edge of the chip 111 in the package particles and the outside of the package particles, plus the width of the dicing marks at the time of final dicing of the molded chip set 11.
S4: the diffused chip set 11 is placed on one side of the protective film 3.
S5: the chip set 11 is plastic-encapsulated.
S6: the protective film 3 is removed.
Since the encapsulated particles are finally required to be placed on the circuit board and electrically connected with the circuit in the circuit board, the encapsulated particles need to expose one side of the chip 111, so that one side of the chip 111 needs to be shielded before encapsulation, and both ends of the chip 111 are prevented from being encapsulated during plastic encapsulation. Therefore, the diffused chip set 11 needs to be placed on one side of the protective film 3, then the plastic package is performed, the plastic package material is shielded by the protective film 3, and after the plastic package is finished, the protective film 3 is removed to expose one side of the chip 111.
S7: the encapsulated chip sets 11 are singulated along the gaps to form individual encapsulated particles.
After the molding is completed, the chip sets 11 are cut along the gaps between the chips 111 of the previous chip sets 11, so as to obtain individual package particles. The packaging method of the wafer does not need to take down the chips 111 one by one for packaging, but directly adopts once packaging molding and then cutting into single particles, thereby greatly improving the production efficiency. Meanwhile, the picking procedure of the chip 111 before packaging in the traditional process can be reduced, the production flow is simplified, and the manufacturing cost and the processing time are reduced.
Preferably, the separating assembly 2 includes a plurality of suction nozzles 21, as shown in fig. 3, each suction nozzle 21 sucks one chip 111, and the plurality of suction nozzles 21 can be independently horizontally moved.
In step S3, each suction nozzle 21 sucks one chip 111, and then controls the suction nozzles 21 to uniformly translate and spread around, so as to achieve the purpose of separating the chips 111. Then, in step S4, the suction nozzle 21 prevents the chip 111 from being attached to the protective film 3 by canceling the suction after the chip 111 is attached to the protective film 3.
The size of the gap between the chips 111 can be more accurately adjusted by using the suction nozzle 21, so that the chips 111 can be conveniently adjusted to an equidistant state, and the qualification rate of finally cut packaging particles is greatly improved.
It is understood that the suction nozzles 21 are each attracted to the center of the corresponding chip 111.
Preferably, the separation assembly 2 further includes an expansion film 22, and the suction nozzles 21 are disposed at intervals of the expansion film 22, and can uniformly increase the distance between adjacent suction nozzles 21 as the expansion film 22 expands. Because of the small size and close distance of each chip 111, the size of the separation assembly 2 is limited, and conventional mechanical transmission structures cannot achieve individual control of the movement of each suction nozzle 21 at such small sizes. The suction nozzles 21 are provided on the expansion film 22, and the suction nozzles 21 are spread as the expansion film 22 is stretched, thereby adjusting the pitch between the chips 111.
Preferably, plasma dicing is used when dicing the wafer 1. The plasma cutting speed is high, the cutting surface is smooth and clean, the thermal deformation is small, the wafer 1 cannot be greatly deformed, and the heat affected zone range is small.
Preferably, the intervals between adjacent chips 111 are equal in size. The space between the chips 111 is equal, so that the dividing line of the packaged particles is in a straight line, the cutter wiring during cutting is simple, the efficiency is high, and partial packaged particles cannot be used due to the fact that the inside of the chips 111 is cut.
Second embodiment
This embodiment is a modification of the structure of the separation assembly 2 on the basis of the first embodiment, as shown in fig. 4.
The separation module 2 in this embodiment includes an elastic film 23, and the chip set 11 is placed on the elastic film 23 in step S1, and the chip set 11 is uniformly spread around by stretching the elastic film 23 around in step S3.
The elastic film 23 is stretched to diffuse the elastic film 23 to the periphery, and the chips 111 on the elastic film 23 are driven by the elastic film 23 to diffuse to the periphery, and the process is stopped when the space between the chips 111 reaches the proper injection molding space. Then the elastic film 23 and the separated chip 111 are turned over and attached to one side of the protective film 3, and the circuit layer on the chip 111 is protected by the protective film 3. After the chip 111 is attached to the protective film 3, the elastic film 23 is removed, and the plastic packaging can be started.
Preferably, the separation assembly 2 further comprises a clamping ring 24 and a stretching ring 25, the clamping ring 24 is capable of clamping the circumference of the elastic membrane 23, the stretching ring 25 is arranged in the clamping ring 24 and concentric with the clamping ring 24, and the stretching ring 25 is abutted against the elastic membrane 23.
When the clamping ring 24 and the stretching ring 25 are relatively far away in the axial direction, the stretching ring 25 can jack up the middle of the elastic film 23, and as the edge of the elastic film 23 is clamped by the clamping ring 24, the elastic film 23 can be stretched by the stretching ring 25, and the stretching forces at all positions of the circumference of the stretching ring 25 are equal, so that the region of the elastic film 23 inside the stretching ring 25 can be uniformly stretched, and the size of the interval between the chips 111 can be freely adjusted according to the distance between the stretching ring 25 and the clamping ring 24.
Preferably, when the wafer 1 is cut in step S2, the cut wafer 1 is continued to be cut down to 30% -70% of the thickness of the elastic film 23. This can ensure that the wafer 1 can be cut, prevent the chips 111 from being connected and not separated, and reduce the strength of the elastic film 23, so that the chips 111 can be more easily and uniformly spread when the elastic film 23 is stretched by the separating assembly 2. Wherein the optimal cutting depth is cut to half the thickness of the elastic membrane 23.
The separation assembly 2 further includes a baffle plate disposed on a side of the elastic film 23 where the chipset 11 is disposed, and when the elastic film 23 stretches, the baffle plate abuts against the chip 111 in the chipset 11.
In the process of stretching the elastic film 23 to the periphery, the elastic film 23 in the range of each chip 111 is in an expanded state, the unbalanced acting force between the elastic film and the chip 111 easily causes the ejection of the chip 111, so that loss is caused, and the subsequent inspection is needed, so that the detection content is improved, and the cost is correspondingly increased. The baffle can press the chip 111 on the elastic film 23, even if the local stress is unbalanced, the chip 111 does not move in a large range, but the contact surface between the chip 111 and the elastic film 23 is re-attached to establish balance, so that the chip 111 throwing caused by the stress problem during the stretching of the elastic film 23 can be effectively prevented.
The foregoing is merely exemplary of the present invention, and those skilled in the art should not be considered as limiting the invention, since modifications may be made in the specific embodiments and application scope of the invention in light of the teachings of the present invention.
Claims (8)
1. The wafer packaging method is characterized by comprising the following steps of:
s1: placing a wafer (1) in a working area of a separation assembly (2);
s2: dicing the wafer (1) into chip sets (11) of individual chips (111);
s3: diffusing the chips (111) in the chip set (11) to the periphery by using the separation assembly (2) so that intervals exist between the adjacent chips (111);
s4: placing the diffused chip set (11) on one side of a protective film (3);
s5: -plastic packaging the chip set (11);
s6: removing the protective film (3);
s7: cutting the chip group (11) after plastic package along the interval to form independent packaging particles;
the separation assembly (2) comprises a plurality of suction nozzles (21), each suction nozzle (21) is used for sucking one chip (111) correspondingly, and the suction nozzles (21) can independently and horizontally move;
the separation assembly (2) further comprises an expansion membrane (22), and the suction nozzles (21) are arranged on the expansion membrane (22) at intervals and can uniformly increase the distance between the adjacent suction nozzles (21) along with the expansion of the expansion membrane (22).
2. The method of packaging a wafer according to claim 1, wherein the suction nozzles (21) are each attracted to the center of the corresponding chip (111).
3. The method of packaging a wafer according to claim 1, wherein the separation assembly (2) comprises an elastic film (23), and wherein the step S1 places the chip set (11) on the elastic film (23), and wherein the step S3 uniformly spreads the chip set (11) around by stretching the elastic film (23) around.
4. A method of packaging a wafer according to claim 3, wherein the separation assembly (2) further comprises a clamping ring (24) and a stretching ring (25), the clamping ring (24) being capable of clamping the circumference of the elastic membrane (23), the stretching ring (25) being arranged in the clamping ring (24) and concentric with the clamping ring (24), the stretching ring (25) being in abutment with the elastic membrane (23).
5. A method of packaging wafers according to claim 3, wherein the wafer (1) is cut and then cut down to 30% -70% of the thickness of the elastic film (23) after cutting the wafer (1).
6. A method of packaging a wafer according to claim 3, wherein the separation assembly (2) further comprises a baffle plate, the baffle plate being arranged on the side of the elastic film (23) on which the chip set (11) is placed, the baffle plate abutting the chips (111) in the chip set (11) when the elastic film (23) is stretched.
7. The method of packaging wafers according to claim 1, characterized in that plasma dicing is used for dicing the wafers (1).
8. The method of packaging wafers according to claim 1, wherein the spacing between adjacent chips (111) is equal in size.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110476477.7A CN113192851B (en) | 2021-04-29 | 2021-04-29 | Wafer packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110476477.7A CN113192851B (en) | 2021-04-29 | 2021-04-29 | Wafer packaging method |
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| Publication Number | Publication Date |
|---|---|
| CN113192851A CN113192851A (en) | 2021-07-30 |
| CN113192851B true CN113192851B (en) | 2024-03-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110476477.7A Active CN113192851B (en) | 2021-04-29 | 2021-04-29 | Wafer packaging method |
Country Status (1)
| Country | Link |
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| CN (1) | CN113192851B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114613700B (en) * | 2022-03-15 | 2024-11-29 | 合肥矽迈微电子科技有限公司 | Cutting reworking method of chip package |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1217564A (en) * | 1997-11-19 | 1999-05-26 | 芝浦机械电子装置股份有限公司 | Dry film stretching apparatus |
| CN101013674A (en) * | 2006-02-03 | 2007-08-08 | 株式会社半导体能源研究所 | Apparatus and method for manufacturing semiconductor device |
| JP2011096961A (en) * | 2009-11-02 | 2011-05-12 | Citizen Electronics Co Ltd | Method of manufacturing led element |
| CN106796893A (en) * | 2014-08-29 | 2017-05-31 | 住友电木株式会社 | The manufacture method and semiconductor device of semiconductor device |
-
2021
- 2021-04-29 CN CN202110476477.7A patent/CN113192851B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1217564A (en) * | 1997-11-19 | 1999-05-26 | 芝浦机械电子装置股份有限公司 | Dry film stretching apparatus |
| CN101013674A (en) * | 2006-02-03 | 2007-08-08 | 株式会社半导体能源研究所 | Apparatus and method for manufacturing semiconductor device |
| JP2011096961A (en) * | 2009-11-02 | 2011-05-12 | Citizen Electronics Co Ltd | Method of manufacturing led element |
| CN106796893A (en) * | 2014-08-29 | 2017-05-31 | 住友电木株式会社 | The manufacture method and semiconductor device of semiconductor device |
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| CN113192851A (en) | 2021-07-30 |
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