CN112816897B - Detection system - Google Patents
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- CN112816897B CN112816897B CN202011622671.3A CN202011622671A CN112816897B CN 112816897 B CN112816897 B CN 112816897B CN 202011622671 A CN202011622671 A CN 202011622671A CN 112816897 B CN112816897 B CN 112816897B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
本申请公开了一种检测系统，包括检测装置、控制装置，检测装置包括：使能参数检测模块，用于检测待检测电源管理芯片的使能电压及使能引脚电流；buck参数检测模块，用于检测待检测电源管理芯片中buck控制器的参数；电源与逻辑检测模块，用于检测待检测电源管理芯片的关断电源电流，对待检测电源管理芯片进行断路/短路测试；控制装置，用于根据测试需求控制检测装置中对应的检测模块进行检测，还用于获取各检测模块进行检测时的测试数据，根据所有检测模块的测试数据确定待检测电源管理芯片的性能。本申请公开的上述技术方案，可以确定待检测电源管理芯片的性能，以便于根据性能筛选出性能优良的电源管理芯片。
The present application discloses a detection system, including a detection device and a control device. The detection device includes: an enable parameter detection module, which is used to detect the enable voltage and enable pin current of a power management chip to be detected; a buck parameter detection module, It is used to detect the parameters of the buck controller in the power management chip to be tested; the power and logic detection module is used to detect the power-off current of the power management chip to be tested, and to perform an open/short circuit test of the power management chip to be tested; the control device, with It is used to control the corresponding detection modules in the detection device to perform detection according to the test requirements, and is also used to obtain the test data of each detection module during detection, and to determine the performance of the power management chip to be detected according to the test data of all the detection modules. The above technical solutions disclosed in the present application can determine the performance of the power management chip to be detected, so as to screen out the power management chip with excellent performance according to the performance.
Description
Technical Field
The application relates to the technical field of power supply detection, in particular to a detection system.
Background
With the development of SV (Server) technology and the continuous innovation of chip manufacturing process, people have higher and higher requirements for SV stability.
The stability of the SV depends on the internal power management chip, and the power management chip with excellent performance can more stably provide the power required by the SV operation. Therefore, the power management chip needs to be tested to select a power management chip with better performance, so as to improve the stability of the SV.
In summary, how to facilitate the selection of a power management chip with better performance is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present application is to provide a detection system for facilitating screening of a power management chip with better performance.
In order to achieve the above object, the present application provides the following technical solutions:
a detection system comprises a detection device and a control device connected with the detection device, wherein the detection device comprises an enabling parameter detection module, a buck parameter detection module, a power supply and logic detection module, and the detection device comprises:
the enabling parameter detection module is used for detecting enabling voltage and enabling pin current of a power management chip to be detected;
the buck parameter detection module is used for detecting the parameter of the buck controller in the power management chip to be detected; the parameters of the buck controller comprise an adjustable output voltage range, a reference voltage, a line adjustment rate, a starting time, a minimum duty ratio and a minimum shutdown time;
the power supply and logic detection module is used for detecting the power supply off current of the power supply management chip to be detected and carrying out open circuit/short circuit test on the power supply management chip to be detected;
the control device is used for controlling the corresponding detection modules in the detection device to detect according to the test requirements, acquiring test data of each detection module during detection, and determining the performance of the power management chip to be detected according to the test data of all the detection modules in the detection device.
Preferably, the enabling parameter detection module includes a first switch, a first resistor, a second resistor, a first capacitor, a second switch, a third switch, a second capacitor, a third capacitor, a fourth switch, a fourth capacitor, a fifth switch, a first power board, a second power board, a third power board, a fourth power board, a fifth power board, and a sixth power board, wherein:
a first end of the first switch is connected to a feedback pin of an LDO in the power management chip to be detected, the feedback pin of the LDO is connected to the first power board, an enable pin of the LDO is connected to the second power board, a second end of the first switch is connected to a first end of the first resistor and a first end of the second resistor, a second end of the first resistor is connected to a first end of the second switch and a first end of the first capacitor, a second end of the second resistor is grounded, a second end of the first capacitor is grounded, a second end of the second switch is connected to an output pin of the LDO, the output pin of the LDO is connected to the third power board, a first end of the third switch is connected to an input current signal pin of the LDO, and an input current signal pin of the LDO is connected to the fourth power supply, the second end of the third switch is connected with the first end of the second capacitor and the first end of the third capacitor, the second end of the second capacitor and the second end of the third capacitor are both grounded, the first end of the fourth switch is connected to a common connection pin of the LDO, the common connection pin of the LDO is connected with the fifth power supply board card, the second end of the fourth switch is connected with the first end of the fourth capacitor, the second end of the fourth capacitor is grounded, the first end of the fifth switch is connected to an analog ground pin of the power management chip to be detected, the analog ground pin of the power management chip to be detected is grounded, the digital ground pin of the buck controller is grounded, and the second end of the fifth switch is connected with the sixth power supply board card;
when the enabling parameter detection module is used for detecting enabling high voltage of the power management chip to be detected, the control device controls the first switch to be closed, the second switch to be closed, the third switch to be closed, the fourth switch to be closed and the fifth switch to be opened, controls the buck controller and the LDO to be in an invalid state, obtains a first upper and lower limit voltage value in a data table and loads the first upper and lower limit voltage value on an enabling pin of the LDO, measures whether voltage at an output pin end of the LDO is high level, and if yes, obtains the voltage value of the enabling pin of the LDO as enabling high voltage;
when the enabling parameter detection module is used for detecting the enabling low voltage of the power management chip to be detected, the control device controls the first switch to be closed, the second switch to be closed, the third switch to be closed, the fourth switch to be closed and the fifth switch to be opened, controls the buck controller and the LDO to be in an enabling state, takes the second upper and lower limit voltage values in the data table and loads the second upper and lower limit voltage values on an enabling pin of the LDO, measures whether the voltage at the output pin end of the LDO is low level, and if yes, obtains the voltage value of the enabling pin of the LDO as the enabling low voltage.
Preferably, when the enabling parameter detection module is used for detecting the current of the enabling pin of the power management chip to be detected, the control device controls the first switch to be closed, the second switch to be closed, the third switch to be closed, the fourth switch to be closed and the fifth switch to be opened, and when the voltage value of the enabling pin end of the LDO is equal to the enabling high voltage, the current of the enabling pin of the LDO in the power management chip to be detected is measured by using an ammeter arranged in the second power board card.
Preferably, the buck parameter detecting module includes a sixth switch, a seventh switch, an eighth switch, a ninth switch, a fifth capacitor, a third resistor, a tenth switch, a first switch tube, a first inductor, a first zener diode, an eleventh switch, a twelfth switch, a sixth capacitor, a thirteenth switch, a seventh power board, an eighth power board, a first OTMU _ CHA, a ninth power board, a tenth power board, an eleventh power board, a second OTMU _ CHA, a twelfth power board, a thirteenth power board, and a fourteenth power board:
a first end of the sixth switch is connected to the seventh power board, a second end of the sixth switch is connected to the feedback pin of the buck controller, a first end of the seventh switch is connected to the feedback pin of the buck controller and is connected to the first end of the sixth switch, a second end of the seventh switch is connected to the first end of the first inductor, the eighth power board and the first OTMU _ CHA, the eighth power board is used as a first output end for measurement, a first end of the eighth switch is connected to the input current signal pin of the buck controller, the input current signal pin of the buck controller is connected to the ninth power board, a second end of the eighth switch is connected to the first end of the first switch tube, and a second end of the first switch tube is connected to the second end of the first inductor and the first end of the first voltage regulator diode, a second end of the first zener diode is grounded, a first end of the ninth switch is connected to an input pin of a data signal in the buck controller and a first end of the third resistor, an input pin of the data signal in the buck controller is connected to the tenth power board, a second end of the ninth switch is connected to a first end of the fifth capacitor, a second end of the fifth capacitor is grounded, a second end of the third resistor is connected to a first end of the tenth switch, a second end of the tenth switch is connected to a second end of the eighth switch and a first end of the first switch tube, a first end of the eleventh switch is connected to a switch pin of the buck controller, a second end of the eleventh switch is connected to a third end of the first switch board, and a switch pin of the buck controller is connected to the eleventh power supply and the second mu _ otcha respectively, a first end of the twelfth switch is connected with a public connection pin of the buck controller, a second end of the twelfth switch is connected with a first end of the sixth capacitor, a second end of the sixth capacitor is grounded, the public connection pin of the buck controller is connected with the twelfth power board, an enable pin of the buck controller is connected with the thirteenth power board, a first end of the thirteenth switch is connected with an analog ground pin of the power management chip to be detected, the analog ground pin of the power management chip to be detected is grounded, a digital ground pin of the buck controller is grounded, and a second end of the thirteenth switch is connected with the fourteenth power board;
when the buck parameter detection module is used for detecting the adjustable output voltage range of the buck controller, the control device is used for controlling the sixth switch to be closed, the seventh switch to be opened, the eighth switch to be closed, the ninth switch to be closed, the tenth switch to be closed, the eleventh switch to be closed, the twelfth switch to be closed and the thirteenth switch to be opened, and controlling the buck controller to be in an enabling state, the thirteenth power supply board is used for applying a corresponding first specified voltage to an enabling pin of the buck controller, the tenth power supply board is used for applying a corresponding second specified voltage to an input current signal pin of the buck controller, the seventh power supply board is used for applying a corresponding third specified voltage to a feedback pin of the buck controller, and the buck controller is controlled to be in a conducting state, and measuring the voltage value of the first output end to obtain the adjustable output voltage range of the buck controller.
Preferably, when the reference voltage of the buck controller is detected by the buck parameter detecting module, the control device controls the sixth switch to be turned on, the seventh switch to be turned off, the eighth switch to be turned on, the ninth switch to be turned on, the tenth switch to be turned on, the eleventh switch to be turned on, the twelfth switch to be turned on, and the thirteenth switch to be turned off, and places the buck controller in an enable state, and applies a corresponding first specified voltage to an enable pin of the buck controller through the thirteenth power board, applies a corresponding second specified voltage to an input current signal pin of the buck controller through the tenth power board, inputs a voltage value which changes from low to high and is within a predetermined range on the input current signal pin of the buck controller through the ninth power board, and measures a voltage change of the switch pin of the buck controller, and taking the difference value between the voltage value of the corresponding input current signal pin and the voltage value of the data signal input pin when the voltage of the switch pin of the buck controller is lower than the preset voltage as the reference voltage of the buck controller.
Preferably, when the buck parameter detection module is used to detect the line adjustment rate of the buck controller, the control device controls the sixth switch to be turned on, the seventh switch to be turned off, the eighth switch to be turned on, the ninth switch to be turned on, the tenth switch to be turned on, the eleventh switch to be turned on, the twelfth switch to be turned on, and the thirteenth switch to be turned off, and places the buck controller in an enable state, and applies a corresponding first specified voltage to an enable pin of the buck controller through the thirteenth power board, applies a corresponding third specified voltage to a feedback pin of the buck controller through the seventh power board, outputs a first voltage value, a second voltage value and a third voltage value respectively to an input pin of a data signal in the buck controller through the tenth power board, and measures the first voltage value output by the first output terminal and the first voltage value through a voltmeter built-in voltage meter of the eighth power supply And calculating the line regulation rate by using any two voltage values of the first voltage value, the second voltage value and the third voltage value and the corresponding output voltages.
Preferably, when the start time of the buck controller is detected by the buck parameter detection module, the control device controls the sixth switch to be turned off, the seventh switch to be turned on, the eighth switch to be turned on, the ninth switch to be turned on, the tenth switch to be turned on, the eleventh switch to be turned on, the twelfth switch to be turned on, and the thirteenth switch to be turned off, and controls the buck controller to be in an invalid state, the tenth power board puts an input pin of a data signal of the buck controller at a high level, the thirteenth power board changes an enable pin of the buck controller to a high level, the first OTMU _ CHA is used to measure a rise time of the first output terminal changing state, and the rise time is used as the start time.
Preferably, when the minimum duty cycle of the buck controller is detected by the buck parameter detection module, the sixth switch is controlled to be open, the seventh switch is controlled to be closed, the eighth switch is controlled to be closed, the ninth switch is controlled to be closed, the tenth switch is controlled to be closed, the eleventh switch is controlled to be closed, the twelfth switch is controlled to be closed, and the thirteenth switch is controlled to be open, and the second OTMU _ CHA is used for testing the minimum duty cycle.
Preferably, when the shortest boot time of the buck controller is detected by using the buck parameter detection module, the sixth switch, the seventh switch, the eighth switch, the ninth switch, the tenth switch, the eleventh switch, the twelfth switch and the thirteenth switch are controlled to be opened by the control device, the buck controller is controlled to be in a closed state, and the second OTMU _ CHA is used to test the shortest boot time.
Preferably, the power supply and logic detection module includes a power supply current shutoff detection submodule, which includes a fifteenth power supply board card, a sixteenth power supply board card, a seventeenth power supply board card and an eighteenth power supply board card:
the fifteenth power supply board card is connected with an input current signal pin of the buck controller, the sixteenth power supply board card is connected with a switch pin of the buck controller, the seventeenth power supply board card is connected with a common connection pin of the buck controller, the eighteenth power supply board card is connected with an enabling pin of the buck controller, and an analog ground pin of the power management chip to be detected and a digital ground pin of the buck controller are both grounded;
when a power supply and logic detection module is used for detecting the power supply off current of the power supply management chip to be detected, the enable pin of the buck controller is set at a low level through the eighteenth power supply board card, a corresponding fourth specified voltage is applied to the input current signal pin of the buck controller through the fifteenth power supply board card, when the buck controller and an LDO (low dropout regulator) in the power supply management chip to be detected do not operate, the current of the input current signal pin of the buck controller is measured through an ammeter arranged in the fifteenth power supply board card, and the current of the input current signal pin of the buck controller is used as the power supply off current of the power supply management chip to be detected.
The application provides a detection system, including detection device, the controlling means who links to each other with detection device, detection device can be including enabling parameter detection module, buck parameter detection module, power and logic detection module, wherein: the enabling parameter detection module is used for detecting enabling voltage and enabling pin current of the power management chip to be detected; the buck parameter detection module is used for detecting the parameter of the buck controller in the power management chip to be detected; parameters of the buck controller may include an adjustable output voltage range, a reference voltage, a line regulation rate, a start-up time, a minimum duty cycle, and a minimum shutdown time; the power supply and logic detection module is used for detecting the power supply current of the power supply management chip to be detected and carrying out open circuit/short circuit test on the power supply management chip to be detected; and the control device is used for controlling the corresponding detection modules in the detection device to detect according to the test requirements, also used for acquiring test data of each detection module during detection, and determining the performance of the power management chip to be detected according to the test data of all the detection modules in the detection device.
The technical scheme disclosed by the application comprises the steps of detecting the enabling voltage and the enabling pin current of a power management chip to be detected by using an enabling parameter detection module in a detection device, detecting the adjustable output voltage range, the reference voltage, the line adjustment rate, the starting time, the minimum duty ratio and the shortest shutdown time of a buck controller in the power management chip to be detected by using the buck parameter detection module in the detection device, detecting the shutdown power current of the power management chip to be detected by using a power and logic detection module in the detection device, performing open circuit/short circuit test on the power management chip to be detected by using the power and logic detection module, controlling the corresponding detection module in the detection device to perform test according to test requirements by using a control device connected with the detection device, and acquiring test data when each detection module in the detection device performs test by using the control device, and the performance of the power management chip to be detected is determined according to the test data of all the detection modules, so that the power management chip with excellent performance is screened out according to the determined performance of the power management chip to be detected, the work stability of the SV can be better improved by the screened power management chip with excellent performance, the user experience is effectively improved, and the product competitiveness is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a detection system according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a detection system provided in an embodiment of the present application;
FIG. 3 is a schematic structural diagram of a power management chip to be tested according to an embodiment of the present disclosure;
FIG. 4 is a circuit diagram of a test circuit for detecting an enable voltage and an enable pin current by an enable parameter detection module according to an embodiment of the present disclosure;
FIG. 5 is a first test circuit diagram of a buck parameter detecting module according to an embodiment of the present invention for performing a parameter test;
FIG. 6 is a second test circuit diagram of the buck parameter detecting module according to the embodiment of the present invention for performing parameter testing;
fig. 7 is a circuit diagram of a test performed by the power-off current detection submodule according to the embodiment of the present application.
Detailed Description
With the development of SV technology and the continuous innovation of chip manufacturing process, the stability of SV is a point of particular importance, and the market share of SV is also determined by the stability degree of a SV. The stability of the SV depends on the power management chip therein, and the power management chip with superior performance can more stably provide the power required by the SV operation, and can also provide a more effective and active processing mode to ensure the operation of the whole system when encountering an emergency (such as overcurrent and overtemperature …).
When the power management chip is actually applied, a user generally wants the power management chip to have small working current and energy loss, and when the power management chip is turned off, the power management chip has very fast voltage rising and falling reaction time, stable output capability under the condition of fluctuating input voltage and the like, and the power management chip are important bases for detecting the quality of the power management chip.
Therefore, the performance of the power management chip can be detected, so that the power management chip with better performance can be screened out, the stability of the SV can be better improved by the power management chip with better performance, the user experience is effectively improved, and the product competitiveness is improved.
In order to make the technical solutions more clearly understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, which shows a schematic structural diagram of a detection system provided in an embodiment of the present application, the detection system provided in an embodiment of the present application may include a detection apparatus 2, and a control apparatus 3 connected to the detection apparatus 2, and the detection apparatus 2 may include an enabling parameter detection module 21, a buck parameter detection module 22, and a power supply and logic detection module 23, where:
the enabling parameter detection module 21 is used for detecting the enabling voltage and the enabling pin current of the power management chip 1 to be detected;
the buck parameter detection module 22 is used for detecting the parameter of the buck controller in the power management chip 1 to be detected; the parameters of the buck controller may include an adjustable output voltage range, a reference voltage, a line regulation rate, a start-up time, a minimum duty cycle, and a minimum shutdown time;
the power supply and logic detection module 23 is used for detecting the power supply current of the power supply management chip 1 to be detected and performing open circuit/short circuit test on the power supply management chip 1 to be detected;
and the control device 3 is used for controlling the corresponding detection modules in the detection device 2 to detect according to the test requirements, acquiring test data of each detection module during detection, and determining the performance of the power management chip 1 to be detected according to the test data of all the detection modules in the detection device 2.
The detection system that this application provided can realize treating the detection of detecting power management chip 1 based on ATE (Automatic Test Equipment, circuit Automatic Test machine), and this detection system specifically can include detection device 2, with detection device 2 and the controlling means 3 that waits to detect power management chip 1 and link to each other.
Wherein, the detecting device 2 can include an enabling parameter detecting module 21, a buck (buck chopper circuit) parameter detecting module, and a power Supply and logic detecting module 23, the enabling parameter detecting module 21 is used for detecting an enabling Voltage (Enable Voltage) and an enabling pin Current (Enable pin Current) of the power management chip 1 to be detected, the buck parameter detecting module 22 is used for detecting an Adjustable Output Voltage Range (Adjustable Output Voltage Range), a Reference Voltage (Reference Voltage for Current sensor), a Line Regulation rate (Line Regulation), a start Time (start Time), a Minimum duty cycle (Minimum On Time) and a Minimum Off Time (Minimum Off f) of a buck controller in the power management chip 1 to be detected, the power Supply and logic detecting module 23 is used for detecting a Shutdown power Supply Current (Shutdown Supply Current) of the power management chip 1 to be detected, and performs Open/Short (Open/Short) test on the power management chip 1 to be detected.
The control device 3 is configured to control corresponding detection modules (specifically, the detection modules included in the aforementioned detection device 2) in the detection device 2 according to test requirements of the power management chip 1 to be detected, and the control device 3 is further configured to acquire test data acquired by all the detection modules in the detection device 2 during detection, and determine the performance of the power management chip 1 to be detected based on the test data and corresponding intermediate values (specifically, the intermediate values can be used as bases for criteria) in a product datasheet (data sheet), so that power management chips with excellent performance are screened from the power management chip 1 to be detected with determined performance, and therefore the power management chips can better improve the working stability of an SV (space vector system) and effectively improve the use experience of a customer and the competitiveness of a product. It should be noted that, for specific values in the data table, the test specification of each test item may be preset by the software of the ATE device itself and according to the product datasheet.
In the technical scheme disclosed by the application, the enabling parameter detection module 21 in the detection device 2 is used for detecting the enabling voltage and the enabling pin current of the power management chip 1 to be detected, the buck parameter detection module 22 in the detection device 2 is used for detecting the adjustable output voltage range, the reference voltage, the line adjustment rate, the starting time, the minimum duty cycle and the shortest shutdown time of the buck controller in the power management chip 1 to be detected, the power and logic detection module 23 in the detection device 2 is used for detecting the power-off current of the power management chip 1 to be detected, the power and logic detection module 23 is used for carrying out open circuit/short circuit test on the power management chip 1 to be detected, the control device 3 connected with the detection device 2 is used for controlling the corresponding detection module in the detection device 2 to carry out the test according to the test requirements, and the control device 3 is used for obtaining the test data of each detection module in the detection device 2 during the test, and confirm the performance of the power management chip 1 to be tested according to the test data of all detection modules to select the power management chip with excellent performance according to the performance of the power management chip 1 to be tested that is determined, thereby make the power management chip with excellent performance that selects can improve SV's job stabilization nature better, in order to improve user experience effectively, improve product competitiveness.
Referring to fig. 2 and fig. 3, fig. 2 shows a specific structural schematic diagram of a detection system provided by an embodiment of the present application, fig. 3 shows a structural schematic diagram of a power management chip to be detected, it should be noted that the present application uses a power management chip of model TPS75003 as a power management chip 1 to be detected for testing, wherein two 3A buck controllers with 95% efficiency and a low dropout regulator (LDO) controller of 300mA are integrated IN the power management chip, FB1 IN the figure IS a feedback pin of one of the buck controllers, IN1 IS an input pin of a data signal of the buck controller, SS1 IS a common connection pin of the buck controller, EN1 IS an enable pin of the data signal of the buck controller, IS1 IS an input current signal pin of the buck controller, SW1 IS a switching pin of the buck controller, and DGND IS a digital pin of the buck controller, FB2 IS the feedback pin of another buck controller, IN1 IS the input pin of the data signal of the buck controller, SS1 IS the common connection pin of the buck controller, EN1 IS the enable pin of the data signal of the buck controller, IS1 IS the input current signal pin of the buck controller, SW1 IS the switch pin of the buck controller, DGND IS the digital ground pin of the buck controller, IN3 IS the input pin of the data signal of the LDO, EN3 IS the enable pin of the LDO, SS3 IS the common connection pin of the LDO, FB3 IS the feedback pin of the LDO, OUT3 IS the output pin of the LDO, AGND IS the analog ground pin of the power management chip 1 to be detected. The detection method is similar to that of other similar power management chips, and in addition, the detection method can also be only used for detecting the power management chip comprising one buck controller or more buck controllers and LDOs, and the detection method is similar to that, but compared with the circuit structure shown in FIG. 2, the circuit structure correspondingly arranged for detecting the buck controller can be reduced. In addition, it should be noted that the power board mentioned in the present application is a test board in which voltage and current are integrated, that is, the power board can be used as both a voltage source and a current source, and in addition, voltage and current can be measured, that is, the power board includes a voltage source, a current source, a voltmeter, and an ammeter.
In the detection system provided in the embodiment of the present application, the enabling parameter detection module 21 may include a first switch K1, a first resistor R1, a second resistor R2, a first capacitor C1, a second switch K2, a third switch K3, a second capacitor C2, a third capacitor C3, a fourth switch K4, a fourth capacitor C4, a fifth switch K5, a first power board HVI _1, a second power board HVI _2, a third power board HOVI _3, a fourth power board HVI _4, a fifth power board HVI _5, and a sixth power board HVI _6, where:
a first terminal of the first switch K1 is connected to a feedback pin of an LDO in the power management chip 1 to be tested, the feedback pin of the LDO is connected to the first power board HVI _1, an enable pin of the LDO is connected to the second power board HVI _2, a second terminal of the first switch K1 is connected to a first terminal of the first resistor R1 and a first terminal of the second resistor R2, a second terminal of the first resistor R1 is connected to a first terminal of the second switch K2 and a first terminal of the first capacitor C1, a second terminal of the second resistor R2 is connected to ground, a second terminal of the first capacitor C1 is connected to ground, a second terminal of the second switch K2 is connected to an output pin of the LDO, an output pin of the LDO is connected to the third power board HOVI _3, a first terminal of the third switch K3 is connected to an input current signal pin of the LDO, an input current signal pin of the LDO is connected to the fourth power supply board HVI _4, a second terminal of the third switch K3 is connected to a second terminal of the third capacitor C3, the second end of the second capacitor C2 and the second end of the third capacitor C3 are both grounded, the first end of a fourth switch K4 is connected to a common connection pin of the LDO, the common connection pin of the LDO is connected with a fifth power supply board card HVI _5, the second end of a fourth switch K4 is connected with the first end of a fourth capacitor C4, the second end of a fourth capacitor C4 is grounded, the first end of a fifth switch K5 is connected to an analog ground pin of the power management chip 1 to be detected, the analog ground pin of the power management chip 1 to be detected is grounded, the digital ground pin of the buck controller is grounded, and the second end of a fifth switch K5 is connected with a sixth power supply board card HVI _ 6;
when the enabling parameter detection module 21 is used for detecting the enabling high voltage of the power management chip 1 to be detected, the control device 3 is used for controlling the first switch K1 to be closed, the second switch K2 to be closed, the third switch K3 to be closed, the fourth switch K4 to be closed and the fifth switch K5 to be opened, controlling the buck controller and the LDO to be in an invalid state, taking the first upper and lower limit voltage values in the data table and loading the first upper and lower limit voltage values on an enabling pin of the LDO, measuring whether the voltage at the output pin end of the LDO is high level, and if yes, obtaining the voltage value of the enabling pin of the LDO as the enabling high voltage;
when the enabling parameter detection module 21 is used for detecting the enabling low voltage of the power management chip 1 to be detected, the control device 3 is used for controlling the first switch K1 to be closed, the second switch K2 to be closed, the third switch K3 to be closed, the fourth switch K4 to be closed and the fifth switch K5 to be opened, controlling the buck controller and the LDO to be in an enabling state, fetching the second upper and lower limit voltage values in the data table and loading the second upper and lower limit voltage values on an enabling pin of the LDO, measuring whether the voltage of the output pin end of the LDO is a low level, and if the voltage value of the enabling pin of the LDO is the enabling low voltage.
It should be noted that, in the figure, the resistance of the first resistor R1 may be 61.9kohm, the resistance of the second resistor R2 may be 15.4kohm, the capacitance of the first capacitor C1 may be specifically 10uF, the capacitance of the second capacitor C2 may be specifically 1uF, and the capacitance of the third capacitor C3 may be specifically 100uF, but the invention is not limited thereto.
Referring specifically to fig. 4, which shows a test circuit diagram of the enabling parameter detection module provided IN this embodiment of the present application for detecting the enabling voltage and the enabling pin current, when the enabling parameter detection module 21 IN the detection device 2 is used to detect the enabling high voltage of the power management chip 1 to be detected, the control device 3 (or the corresponding power board) may control the first switch K1 IN the enabling parameter detection module 21 to be closed, the second switch K2 to be closed, the third switch K3 to be closed, the fourth switch K4 to be closed, and the fifth switch K5 to be opened, and then all buck controllers and LDOs IN the power management chip 1 to be detected may be IN an invalid (Disable) state, specifically, that is, the En pin (enabling pin) IN the power management chip 1 to be detected is set to a low level by the corresponding power board, and the IN pin (input pin of the data signal) is set to a high level (specifically, the En pin, the data signal is set to a high level (specifically, the end pin, and the LDO IN all buck controllers and the LDO, IN pin performs the above operation), the first upper and lower limit voltage values 1.4V-Vin IN the data table are loaded on the enable pin of the LDO through the second power board HVI _2, and whether the voltage at the output pin end of the LDO is high level can be measured through the voltmeter built IN the third power board HOVI _3, if so, the voltage value of the enable pin of the LDO can be obtained as an enable high voltage (Vih _ En).
When the enabling parameter detection module 21 IN the detection device 2 is used to detect the enabling low voltage of the power management chip 1 to be detected, the control device 3 (or the corresponding power board) can be used to control the first switch K1, the second switch K2, the third switch K3, the fourth switch K4 and the fifth switch K5 IN the enabling parameter detection module 21 to be closed, then all the buck controllers and the LDOs IN the power management chip 1 to be detected can be IN an enabling state, specifically, the En pin and the IN pin IN the power management chip 1 to be detected are set at a high level and set at a high level through the corresponding power board (specifically, the operation is performed on the En pins and the IN pins of all the buck controllers and all the LDOs), and the second upper and lower limit voltage values 0V-0.3V IN the second power HVI _2 data table are loaded on the enabling pin of the LDO, and whether the voltage at the output pin end of the LDO is low level can be measured through a voltmeter built in the third power board HOVI _3, and if the voltage is low level, the voltage value of the enable pin of the LDO can be obtained as an enable low voltage (Vil _ En).
It should be noted that the test conditions for performing the enable high voltage and enable low voltage tests are specifically shown in table 1:
TABLE 1 test condition Table enabling high-Voltage and Low-Voltage tests
In addition, when the enable voltage is performed by the enable parameter detection module 21, the lower limit value may be 1.4V or 0.3V for performing the corresponding test. It should be noted that, this application is follow-up to buck controller and LDO enable state or invalid state all can realize through the power integrated circuit board that corresponds, and follow-up no longer gives unnecessary details.
When the enabling parameter detection module 21 is used to detect the enabling pin current of the power management chip 1 to be detected, the control device 3 controls the first switch K1 to be closed, the second switch K2 to be closed, the third switch K3 to be closed, the fourth switch K4 to be closed, and the fifth switch K5 to be opened, and when the voltage value of the enabling pin terminal of the LDO is equal to the enabling high voltage, the enabling pin current of the LDO in the power management chip 1 to be detected is measured by using the current meter built in the second power board HVI _ 2.
When the enabling parameter detection module 21 in the detection device 2 is used for detecting the enabling pin current of the power management chip 1 to be detected, the control device 3 can be used for controlling the first switch K1 to be closed, the second switch K2 to be closed, the third switch K3 to be closed, the fourth switch K4 to be closed and the fifth switch K5 to be opened, the specific test circuit is shown in fig. 4, and when the voltage value of the enabling pin end of the LDO is equal to the enabling high voltage, the current of the enabling pin of the LDO in the power management chip 1 to be detected can be measured by using an ammeter arranged in the second power board HVI _ 2. Of course, when the voltage value of the enable pin terminal of the LDO is equal to the enable low voltage, the current of the enable pin of the LDO in the power management chip 1 to be detected may be measured by using the ammeter built in the second power board HVI _2, that is, the current of the enable pin of the LDO may be measured while the Vih _ En or the Vil _ En is tested.
In the detection system provided in the embodiment of the present application, the buck parameter detection module 22 may include a sixth switch K6, a seventh switch K7, an eighth switch K8, a ninth switch K9, a fifth capacitor C5, a third resistor R3, a tenth switch K10, a first switch Q1, a first inductor L1, a first zener diode D1, an eleventh switch K11, a twelfth switch K12, a sixth capacitor C6, a thirteenth switch K13, a seventh power board HVI _7, an eighth power board HVI _8, a first OTMU _ CHA, a ninth power board HVI _9, a tenth power board HVI _10, an eleventh power board HVI _11, a second mu _ CHA, a twelfth power board HVI _12, a thirteenth power HVI _13, and a fourteenth power board HVI _ 13:
a first terminal of a sixth switch K6 is connected to a seventh power board HVI _7, a second terminal of a sixth switch K6 is connected to a feedback pin of the buck controller, a first terminal of a seventh switch K7 is connected to a feedback pin of the buck controller and to a first terminal of a sixth switch K6, a second terminal of a seventh switch K7 is connected to a first terminal of a first inductor L1, an eighth power board HOVI _8 and a first OTMU _ CHA, and the eighth power board HOVI _8 is used as a first output terminal for measurement, a first terminal of the eighth switch K8 is connected to an input current signal pin of the buck controller, the input current signal pin of the buck controller is connected to a ninth power board HVI _9, a second terminal of the eighth switch K8 is connected to a first terminal of a first switching tube Q1, a second terminal of the first switching tube Q1 is connected to the second terminal of the first inductor L1 and a second terminal of a first diode 1D 1, a first terminal of a ninth switch K9 is connected to an input pin of a data signal in the buck controller and a first terminal of a third resistor R3, the input pin of the data signal in the buck controller is connected to a tenth power board HOVI _10, a second terminal of the ninth switch K9 is connected to a first terminal of a fifth capacitor C5, a second terminal of the fifth capacitor C5 is grounded, a second terminal of the third resistor R3 is connected to a first terminal of a tenth switch K10, a second terminal of the tenth switch K10 is connected to a second terminal of the eighth switch K8 and a first terminal of a first switch tube Q1, a first terminal of the eleventh switch K11 is connected to a switch pin of the buck controller, a second terminal of the eleventh switch K11 is connected to a third terminal of a first switch tube Q1, switch pins of the buck controller are connected to an eleventh power supply i _11 and a second switch pin of the buck controller, a second terminal of the twelfth switch K12 is connected to a second terminal of the hvk switch K12, a second terminal of the twelfth switch K12 is connected to a second terminal of the first switch C12, the second end of the sixth capacitor C6 is grounded, the common connection pin of the buck controller is connected with the twelfth power supply board card HVI _12, the enable pin of the buck controller is connected with the thirteenth power supply board card HVI _13, the first end of the thirteenth switch K13 is connected with the analog ground pin of the power management chip 1 to be detected, the analog ground pin of the power management chip 1 to be detected is grounded, the digital ground pin of the buck controller is grounded, and the second end of the thirteenth switch K13 is connected with the fourteenth power supply board card;
when the buck parameter detection module 22 is used to detect the adjustable output voltage range of the buck controller, the control device 3 controls the sixth switch K6 to be closed, the seventh switch K7 to be opened, the eighth switch K8 to be closed, the ninth switch K9 to be closed, the tenth switch K10 to be closed, the eleventh switch K11 to be closed, the twelfth switch K12 to be closed and the thirteenth switch K13 to be opened, and controls the buck controller to be in an enabling state, and applies a corresponding first specified voltage on an enabling pin of the buck controller through the thirteenth power board HVI _13, applies a corresponding second specified voltage on an input current signal pin of the buck controller through the tenth power board HOVI _10, applies a corresponding third specified voltage on a feedback pin of the buck controller through the seventh power board HVI _7, and controlling the buck controller to be in a conducting state, and measuring the voltage value of the first output end to obtain the adjustable output voltage range of the buck controller.
It should be noted that the thirteenth switch K13 in the buck parameter detection module 22 and the fifth switch K5 in the enable parameter detection module 21 are the same switch, the fourteenth power board in the buck parameter detection module 22 and the sixth power board HVI _6 in the enable parameter detection module 21 are the same power board, and the OTMU (eight time measurement unit) in the OTMU _ CHA in the present application is a board of the test device, and can be used to measure a time interval, and the CHA represents channel a (channel a), that is, the present application uses the CHA of the OTMU to perform the test of the time-related parameter, where the first OTMU _ CHA is the OTMU _1_ CHA in fig. 2, and the second OTMU _ CHA is the OTMU _2_ CHA in fig. 2. In addition, the capacitance of the fifth capacitor C5 may be specifically 0.1uF, the resistance of the third resistor R3 may be specifically 33mohm, and the inductance of the first inductor L1 may be specifically 15uH, which is not limited to these specific values. In addition, the first switching tube Q1 may be specifically Si2323DS, and the first inductor L1 may be specifically CDRH8D43-150, although the model is not limited to this.
Referring specifically to fig. 5, which shows a first test circuit diagram of the buck parameter detecting module for performing parameter test according to the embodiment of the present invention, when the buck parameter detecting module 22 is used to detect the adjustable output voltage range of the buck controller, the control device 3 may control the sixth switch K6 to be closed, the seventh switch K7 to be opened, the eighth switch K8 to be closed, the ninth switch K9 to be closed, the tenth switch K10 to be closed, the eleventh switch K11 to be closed, the twelfth switch K12 to be closed, the thirteenth switch K13 to be opened, and control the buck controller to be in the enabling state, i.e., the buck controller makes the enable pin and the input pin of the data signal to be at high level, and applies a corresponding first specified voltage (specifically, 2.2V) to the enable pin of the buck controller through the thirteenth power board HVI _13, and applies a corresponding second specified voltage (specifically, 2.2V) to the input current signal pin of the buck controller through the tenth power board HOVI _10, And applying a corresponding third specified voltage (specifically, 0V) to the feedback pin of the buck controller through the seventh power board HVI _7 (applying the corresponding third specified voltage to the feedback pin of the buck controller to enable the buck controller to be in a conducting state), and measuring the voltage value of the first output end at this time to obtain an adjustable output voltage range of the buck controller.
It should be noted that, the buck parameter detecting module 22 mentioned in this application is a module for detecting one buck controller in the power management chip 1 to be detected, and for another buck controller (i.e. corresponding to the buck controller with pin number 2 in fig. 2), the corresponding buck parameter detecting module 22 has a similar structure to the above-mentioned buck parameter detecting module 22, and specifically, refer to fig. 2, that is, specifically, may include a fourteenth switch K14 (the position corresponds to the sixth switch K6), a fifteenth switch K15 (the position corresponds to the seventh switch K7), a sixteenth switch K16 (the position corresponds to the eighth switch K8), a seventeenth switch K17 (the position corresponds to the ninth switch K9), an eighteenth switch K18 (the position corresponds to the tenth switch K10), a nineteenth switch K19 (the position corresponds to the eleventh switch), a twentieth switch K20 (the position corresponds to the twelfth switch K12), and a twelfth switch K12) A nineteenth power board HVI _19 (position corresponding to the seventh power board HVI _7), a twentieth power board HOVI _20 (position corresponding to the eighth power board HOVI _ 8), a twenty-first power board HVI _21 (position corresponding to the ninth power board HVI _ 9), a twenty-second power board HOVI _22 (position corresponding to the tenth power board HOVI _10), a twenty-third power board HVI _23 (position corresponding to the eleventh power board HVI _ 11), a twenty-fourth power board HVI _24 (position corresponding to the twelfth power board HVI _ 12), a twenty-fifth power board HVI _25 (position corresponding to the thirteenth power board HVI _ 13), a second inductor L1 (position corresponding to the first inductor L1), a second switch tube Q2 (position corresponding to the first switch tube Q1), a second zener diode D2 (position corresponding to the first zener diode D1), a second zener diode D1, A third OTMU _ CHA (corresponding to the second OTMU _ CHA in position, specifically, OTMU _3_ CHA in fig. 2), a seventh capacitor C7 (corresponding to the fifth capacitor C5 in position), an eighth capacitor C8 (corresponding to the sixth capacitor C6 in position), and a fourth resistor R4 (corresponding to the third resistor R3 in position), wherein the connection relationship between the above-mentioned devices (specifically, the fourteenth switch K14, the twentieth switch, the nineteenth power board HVI _19, the twenty-fifth power board HVI _25, etc.) and another buck controller (i.e., the buck controller corresponding to pin number 2 in fig. 2) and the connection relationship between the devices in the buck parameter detection module 22 described in this application (i.e., the sixth switch K6, the twelfth switch K12, the seventh power board HVI _7, the thirteenth power HVI _13, etc.) and one of the buck controllers (i.e., the connections corresponding to pins 1 in fig. 2) are similar to each other, the difference is that the detection circuit for another buck controller (i.e., the buck controller corresponding to pin number 2 in fig. 2) further includes a twenty-first switch K21 and a twenty-sixth power board HVI _26, where a first end of the twenty-first switch K21 is connected to a digital ground pin of another buck controller, a second end of the twenty-first switch K21 is connected to the twenty-sixth power board HVI _26, the second inductor L2 may be specifically CDRH6D38-5R0, and the second zener diode D2 may be specifically MBRM120, but the detection circuit is the same as the test process and the process for detecting the parameter of one of the buck controllers (i.e., the buck controller corresponding to pin number 1 in fig. 2), and details of the present application are omitted.
In the detection system provided by the embodiment of the application, when the reference voltage of the buck controller is detected by the buck parameter detection module 22, the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10, the eleventh switch K11, the twelfth switch K12 and the thirteenth switch K13 are controlled to be closed by the control device 3, the buck controller is placed in an enabling state, a corresponding first specified voltage is applied to an enabling pin of the buck controller through the thirteenth power board HVI _13, a corresponding second specified voltage is applied to an input current signal pin of the buck controller through the tenth power board HOVI _10, a voltage value which changes from low to high and is within a predetermined range is input to the input current signal pin of the buck controller through the ninth power supply HVI _9, and the voltage change of the switch pin of the buck controller is measured, and the difference value between the voltage value of the corresponding input current signal pin and the voltage value of the data signal input pin when the voltage of the switch pin of the buck controller is lower than the preset voltage is used as the reference voltage of the buck controller.
When the reference voltage of the buck controller is detected by the buck parameter detecting module 22, the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10, the eleventh switch K11, the twelfth switch K12 and the thirteenth switch K13 can be controlled by the control device 3 to be closed (as shown in fig. 5 in particular), and the buck controller can be set to an enabled state, and simultaneously, a corresponding first specified voltage (2.2V) can be applied to the enable pin of the buck controller through the thirteenth power board HVI _13, a corresponding second specified voltage (2.2V) can be applied to the input current signal pin of the buck controller through the tenth power board HOVI _10, and a voltage value which changes from low to high and is within a predetermined range can be input to the input current signal pin of the buck controller through the ninth power board HVI _9, the predetermined range may be specifically 2V to 2.2V, and the voltage change of the switch pin of the buck controller may be measured in the process, and when the voltage of the switch pin of the buck controller is lower than a preset voltage (specifically, may be 1.22V), a difference between a voltage value of the input current signal pin of the buck controller and a voltage value of the input pin of the data signal of the buck controller is a reference voltage of the input current signal pin of the buck controller.
When the detection system provided by the embodiment of the application detects the line adjustment rate of the buck controller by using the buck parameter detection module 22, the control device 3 controls the sixth switch K6 to be closed, the seventh switch K7 to be opened, the eighth switch K8 to be closed, the ninth switch K9 to be closed, the tenth switch K10 to be closed, the eleventh switch K11 to be closed, the twelfth switch K12 to be closed, and the thirteenth switch K13 to be opened, and places the buck controller in an enable state, and applies a corresponding first specified voltage to an enable pin of the buck controller through the thirteenth power board HVI _13, applies a corresponding third specified voltage to a feedback pin of the buck controller through the seventh power board HVI _7, outputs a first voltage value, a second voltage value and a third voltage value on an input pin of a data signal of the buck controller through the tenth power board HOVI _10, and measures a corresponding output voltage value of an output terminal of a first voltage table and a corresponding output value of the first output voltage value through an output terminal of the eighth power board HOVI _8 The circuit adjusting rate is calculated by using any two voltage values of the first voltage value, the second voltage value and the third voltage value and the corresponding output voltages.
When the buck parameter detecting module 22 is used to detect the line adjustment rate of the buck controller, the control device 3 may control the sixth switch K6 to be closed, the seventh switch K7 to be opened, the eighth switch K8 to be closed, the ninth switch K9 to be closed, the tenth switch K10 to be closed, the eleventh switch K11 to be closed, the twelfth switch K12 to be closed, and the thirteenth switch K13 to be opened (as specifically shown in fig. 5), and may place the buck controller in an enable state, and at the same time, the thirteenth power board HVI _13 may apply a corresponding first specified voltage (2.2V) to an enable pin of the buck controller, and the seventh power source HVI _7 may apply a corresponding third specified voltage (2.2V) to a feedback pin of the buck controllerA third designated voltage (0V), a first voltage value (2.2V), a second voltage value (3.2V) and a third voltage value (Vnimax 6.5V) are respectively output through the tenth power board HOVI _10 on an input pin of a data signal in the buck controller, and a first output voltage (Vout) corresponding to the first voltage value is measured through a voltmeter built in the eighth power board HOVI _81) And a second output voltage (Vout) corresponding to the second voltage value2) A third output voltage (Vout) corresponding to the third voltage value3) Then, two voltage values can be arbitrarily selected from the three voltage values of the first voltage value, the second voltage value and the third voltage value, and the output voltage corresponding to the two selected voltage values is obtained, and then Line Regulation is taken as fabs ((vout2-vout1) - (vin2-vin 1))/(vin 2-vin1), wherein vin2 and vin1 are the two selected voltage values, vout2 and vout1 are the two output voltages corresponding to the two selected voltage values, and the remaining one voltage value and the corresponding output voltage can be used for monitoring.
When the start time of the buck controller is detected by using the buck parameter detection module 22, the control device 3 controls the sixth switch K6 to be open, the seventh switch K7 to be closed, the eighth switch K8 to be closed, the ninth switch K9 to be closed, the tenth switch K10 to be closed, the eleventh switch K11 to be closed, the twelfth switch K12 to be closed, and the thirteenth switch K13 to be open, and controls the buck controller to be in an inactive state, the tenth power board HOVI _10 is used to set the input pin of the data signal of the buck controller to a high level, the thirteenth power board HVI _13 is used to set the enable pin of the buck controller to a high level, the first OTMU _ CHA is used to measure the rise time of the first output terminal in a state change, and the rise time is used as the start time.
Specifically, referring to fig. 6, which shows a second test circuit diagram of the buck parameter detecting module for performing parameter test according to the embodiment of the present application, when the buck parameter detecting module 22 is used to detect the start time of the buck controller, the control device 3 may control the sixth switch K6 to be opened, the seventh switch K7 to be closed, the eighth switch K8 to be closed, the ninth switch K9 to be closed, the tenth switch K10 to be closed, the eleventh switch K11 to be closed, the twelfth switch K12 to be closed, and the thirteenth switch K13 to be opened, wherein the feedback pin of the buck controller may be connected to the peripheral circuit formed by the first switch tube Q1, the first inductor L1, the first zener diode D1, the third resistor R3, etc. by opening the sixth switch K6 and the seventh switch K7 to be closed, and the buck controller may be controlled to be in an inactive state, that is to put the input pin of the data signal of the buck controller in a high capacitance state, the enable pin of the buck controller is changed to high level, and at the same time, the first OTMU _ CHA may be used to measure the rise time of the first output terminal changing state, and the measured rise time may be used as the start time.
When the minimum duty cycle of the buck controller is detected by using the buck parameter detection module 22, the control device 3 controls the sixth switch K6 to be open, the seventh switch K7 to be closed, the eighth switch K8 to be closed, the ninth switch K9 to be closed, the tenth switch K10 to be closed, the eleventh switch K11 to be closed, the twelfth switch K12 to be closed, and the thirteenth switch K13 to be open, controls the buck controller to be in the on state, and uses the second OTMU _ CHA to test the minimum duty cycle.
When the minimum duty cycle of the buck controller is detected by the buck parameter detecting module 22, the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10, the eleventh switch K11, the twelfth switch K12, and the thirteenth switch K13 may be controlled to be opened by the control device 3 (as shown in fig. 6 in particular), wherein the feedback pin of the buck controller may be connected to a peripheral circuit formed by the first switch tube Q1, the first inductor L1, the first zener diode D1, the third resistor R3, and the like by opening the sixth switch K6 and closing the seventh switch K7, and the buck controller is controlled to be in the on state, and in the on state, the switch pin of the buck controller (i.e. the second otcha) may see a low-frequency pulse (low-frequency) with a fixed voltage, each occurrence of the internal Mosfet (specifically, the first switching tube Q1) indicates a conduction, the test item and the width of the low burst are tested, and the minimum duty cycle is determined according to the width of the low burst.
Specifically, referring to fig. 7, which shows a test circuit diagram of the shutdown power supply current detection submodule for testing, when the buck parameter detection module 22 is used to detect the shortest startup time of the buck controller, the detection system provided in the embodiment of the present application controls, by the control device 3, the sixth switch K6 to be opened, the seventh switch K7 to be closed, the eighth switch K8 to be closed, the ninth switch K9 to be closed, the tenth switch K10 to be closed, the eleventh switch K11 to be closed, the twelfth switch K12 to be closed, the thirteenth switch K13 to be opened, controls the buck controller to be in a closed state, and uses the second OTMU _ CHA to test the shortest startup time.
When the shortest boot time of the burst controller is detected by the burst parameter detecting module 22, the sixth switch K6 is controlled to be open, the seventh switch K7 is controlled to be closed, the eighth switch K8 is controlled to be closed, the ninth switch K9 is controlled to be closed, the tenth switch K10 is controlled to be closed, the eleventh switch K11 is controlled to be closed, the twelfth switch K12 is controlled to be closed, and the thirteenth switch K13 is controlled to be open (see fig. 6 specifically), meanwhile, the burst controller is controlled to be in an off state, when the burst controller is in the off state, a switch pin (i.e., the second OTMU _ CHA) of the burst controller can see that a high-burst (high-frequency pulse) with a fixed frequency exists in voltage, and each occurrence represents that an internal Mosfet (i.e., the first switch tube Q1) is closed, the test item and the width (gh) of the low-burst are tested, and the shortest boot time is determined according to the width of the high-burst.
The detection system that this application embodiment provided, power and logic detection module 23 can be including shutting off power supply current detection submodule, and shutting off power supply current detection submodule can include fifteenth power supply integrated circuit board, sixteenth power supply integrated circuit board, seventeenth power supply integrated circuit board, eighteenth power supply integrated circuit board:
the fifteenth power supply board card is connected with an input current signal pin of the buck controller, the sixteenth power supply board card is connected with a switch pin of the buck controller, the seventeenth power supply board card is connected with a common connection pin of the buck controller, the eighteenth power supply board card is connected with an enable pin of the buck controller, and an analog ground pin of the power management chip 1 to be detected and a digital ground pin of the buck controller are both grounded;
when the power supply and logic detection module 23 is used for detecting the power supply off current of the power supply management chip 1 to be detected, the enable pin of the buck controller is set at a low level through the eighteenth power supply board card, a corresponding fourth specified voltage is applied to the input current signal pin of the buck controller through the fifteenth power supply board card, when the buck controller and the LDO in the power supply management chip 1 to be detected do not act, the current of the input current signal pin of the buck controller is measured through an ammeter arranged in the fifteenth power supply board card, and the current of the input current signal pin of the buck controller is used as the power supply off current of the power supply management chip 1 to be detected.
In the detection system provided by the present application, the power and logic detection module 23 includes a power-off current detection submodule, where the power-off current detection submodule may include a fifteenth power board, a sixteenth power board, a seventeenth power board, and an eighteenth power board, where the fifteenth power board and the above-mentioned tenth power board HOVI _10 are the same power board, the sixteenth power board and the above-mentioned eleventh power board HVI _11 are the same power board, the seventeenth power board and the above-mentioned twelfth power board HVI _12 are the same power board, the eighteenth power board and the above-mentioned thirteenth power board HVI _13 are the same power board, and the test circuit diagram shown in fig. 7 is equivalent to that the sixth switch K6 of the buck parameter detection module 22 in fig. 2 disconnects the power supply, Seventh switch K7 off, eighth switch K8 off, ninth switch K9 off, tenth switch K10 off, eleventh switch K11 off, twelfth switch K12 off, and no second OTMU _ CHA.
In addition, the power and logic detection module 23 provided by the present application may further include an open circuit and short circuit detection sub-module, wherein the open circuit and short circuit detection sub-module may specifically include a power board (for a buck controller, the tenth power board HOVI _10 in fig. 2) connected to an input pin of a data signal of the buck controller in the power management chip 1 to be detected, a power board (for a buck controller, the fourth power board HOVI _4 in fig. 2) connected to an input pin of a data signal of the LDO, a power board (for a buck controller, the seventh power board HVI _7 in fig. 2) connected to a feedback pin of the buck controller, a power board (for a third power board HOVI _3 in fig. 2) connected to an output pin of the LDO, and the pins corresponding to the power boards are used to send-100 uA currents, and the corresponding points in the power boards are used to set internal voltage values of each pin at both sides, and confirming that the pin of the power management chip 1 to be detected has no open circuit or short circuit, wherein when the open circuit or short circuit is detected, the test conditions are Max:0.2V and Min: minus 1V, namely the voltage value of the corresponding power board card needs to be in the range.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include elements inherent in the list. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. In addition, parts of the above technical solutions provided in the embodiments of the present application, which are consistent with the implementation principles of corresponding technical solutions in the prior art, are not described in detail so as to avoid redundant description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
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