CN112711779A - Self-destruction circuit and electronic equipment - Google Patents
Self-destruction circuit and electronic equipment Download PDFInfo
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- CN112711779A CN112711779A CN202110062347.9A CN202110062347A CN112711779A CN 112711779 A CN112711779 A CN 112711779A CN 202110062347 A CN202110062347 A CN 202110062347A CN 112711779 A CN112711779 A CN 112711779A
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
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Abstract
The embodiment of the application relates to the technical field of information security, and provides a self-destruction circuit and electronic equipment, wherein the self-destruction circuit comprises a signal sampling processing circuit, a first signal conversion circuit and a main processor, and when the electronic equipment receives a high-level self-destruction signal through a signal interface, on one hand, the first signal conversion circuit converts the high-level self-destruction signal into a power supply signal so as to supply power to the signal sampling processing circuit and the main processor; on the other hand, the signal sampling processing circuit converts the high-level self-destruction signal into a soft self-destruction signal and then sends the soft self-destruction signal to the main processor, and the main processor sends a soft self-destruction instruction to a circuit to be destroyed of the electronic equipment after determining that the soft self-destruction signal is effective, so that the circuit to be destroyed is self-destroyed. That is, once receiving the high level self-destruction signal, the high level self-destruction signal is utilized to supply power, so that the self-destruction effect of the circuit to be destroyed cannot be influenced no matter whether the electronic equipment is unstably powered on or powered off.
Description
Technical Field
The embodiment of the application relates to the technical field of information security, in particular to a self-destruction circuit and electronic equipment.
Background
Today, important data leakage in various devices, which contain important data such as personal privacy information, company business secrets, military secrets and the like, and once leaked, the important data leakage has immeasurable influence on individuals and corporations, becomes a potential important threat of data security. Therefore, it is very important and necessary to add a self-destruction device of a key device to an important electronic device.
However, in the process of executing self-destruction, if the power supply of the whole equipment is unstable or the power is cut off, the conventional soft self-destruction circuit cannot realize the self-destruction function or cannot completely destroy the equipment, and potential safety hazards exist.
Disclosure of Invention
An object of the present invention is to provide a self-destruction circuit and an electronic device, so as to improve the above-mentioned problems.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in a first aspect, an embodiment of the present application provides a self-destruction circuit, which is applied to an electronic device, and includes a signal sampling processing circuit, a first signal conversion circuit, and a main processor; the input end of the first signal conversion circuit is electrically connected with a signal interface of the electronic equipment, and the output end of the first signal conversion circuit is electrically connected with the signal sampling processing circuit and the main processor; the signal interface, the signal sampling processing circuit, the main processor and a circuit to be destroyed of the electronic equipment are electrically connected in sequence;
the first signal conversion circuit is used for receiving a high-level self-destruction signal and converting the high-level self-destruction signal into a power supply signal to supply power to the signal sampling processing circuit and the main processor;
the signal sampling processing circuit is used for receiving the high-level self-destruction signal, converting the high-level self-destruction signal into a soft self-destruction signal and then sending the soft self-destruction signal to the main processor;
and the main processor is used for sending a soft self-destruction instruction to the circuit to be destroyed to enable the circuit to be destroyed by self after the soft self-destruction signal is determined to be effective.
Optionally, the self-destruction circuit further includes a control circuit, the control circuit is electrically connected to the output end of the first signal conversion circuit, and the control circuit is electrically connected to both the main processor and the circuit to be destroyed; the first signal conversion circuit is further used for transmitting the power supply signal to the control circuit to supply power to the control circuit; the main processor is further used for sending a soft self-destruction instruction to the control circuit after the soft self-destruction signal is determined to be valid; and the control circuit is used for controlling the self-destruction of the circuit to be destroyed according to the soft self-destruction instruction.
Optionally, the self-destruction circuit further includes a switch circuit, an input end of the switch circuit is electrically connected to the signal interface, an output end of the switch circuit is electrically connected to the main processor and the circuit to be destroyed, respectively, and a control end of the switch circuit is electrically connected to the control circuit;
the main processor is also used for sending a hard self-destruction instruction to the control circuit after receiving a soft self-destruction completion signal returned by the circuit to be destroyed;
the control circuit is further configured to control the switch circuit to be turned on according to the hard self-destruction instruction, and transmit the high-level self-destruction signal to the circuit to be destroyed and the main processor, so as to burn the circuit to be destroyed and the main processor.
Optionally, the self-destruction circuit further includes a second signal conversion circuit, an input end of the second signal conversion circuit is electrically connected to a power supply of the electronic device, and an output end of the second signal conversion circuit is electrically connected to the signal sampling processing circuit, the main processor, the control circuit, and other circuits of the electronic device, respectively;
and the second signal conversion circuit is used for respectively transmitting the power supply signal provided by the power supply to the signal sampling processing circuit, the main processor, the control circuit and the other circuits when the power supply is normally supplied with power, and supplying power to the signal sampling processing circuit, the main processor, the control circuit and the other circuits.
Optionally, the second signal conversion circuit comprises a first isolation circuit and a switch control circuit; the input end of the first isolation circuit is electrically connected with the power supply, the output end of the first isolation circuit is electrically connected with the signal sampling processing circuit, the main processor, the control circuit and the switch control circuit respectively, and the control end of the first isolation circuit is electrically connected with the control circuit; the control circuit is electrically connected with the switch control circuit, and the switch control circuit is electrically connected with the other circuits;
the first isolation circuit is used for respectively transmitting the power supply signal to the signal sampling processing circuit, the main processor and the control circuit when the power supply is normally powered, and transmitting the power supply signal to the other circuits through the switch control circuit.
Optionally, the first signal conversion circuit comprises a first power conversion circuit and a second isolation circuit; the input end of the first power supply conversion circuit is electrically connected with the signal interface, and the output end of the first power supply conversion circuit is electrically connected with the first isolation circuit, the second isolation circuit and the control circuit respectively; the second isolation circuit is respectively and electrically connected with the signal sampling processing circuit, the main processor, the control circuit and the switch control circuit;
the first power supply conversion circuit is used for converting the high-level self-destruction signal into the power supply signal;
the first power conversion circuit is further configured to:
transmitting the power supply signal to the first isolation circuit to turn off the first isolation circuit;
transmitting the power supply signal to the control circuit to enable the control circuit to turn off the switch control circuit according to the power supply signal and stop supplying power to other circuits;
and transmitting the power supply signal to the signal sampling processing circuit, the main processor and the control circuit through the second isolation circuit to supply power to the signal sampling processing circuit, the main processor and the control circuit.
Optionally, the first isolation circuit includes a first MOS transistor, a first resistor, and a second resistor;
the drain electrode of the first MOS tube is electrically connected with the power supply, and the source electrode of the first MOS tube is respectively and electrically connected with the signal sampling processing circuit, the main processor, the control circuit and the switch control circuit; the grid electrode of the first MOS tube is electrically connected with the output end of the first power supply conversion circuit through the first resistor, one end of the second resistor is electrically connected with the grid electrode of the first MOS tube, and the other end of the second resistor is grounded.
Optionally, the switch control circuit includes a second MOS transistor, a first triode, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a first capacitor;
the source electrode of the second MOS tube is electrically connected with the first isolation circuit; one end of the first capacitor is electrically connected with the source electrode of the second MOS tube, and the other end of the first capacitor is grounded; the drain electrode of the second MOS tube is electrically connected with the other circuit; the grid electrode of the second MOS tube is electrically connected with the collector electrode of the first triode through the third resistor; one end of the fourth resistor is electrically connected with the source electrode of the second MOS tube, and the other end of the fourth resistor is electrically connected with the grid electrode of the second MOS tube;
the base electrode of the first triode is electrically connected to the control circuit through the fifth resistor; one end of the sixth resistor is electrically connected with the control circuit, and the other end of the sixth resistor is grounded; and the emitter of the first triode is grounded.
Optionally, the switching circuit comprises a relay, a second capacitor, a seventh resistor, an eighth resistor, and a ninth resistor; a first end of a coil of the relay is electrically connected to the control circuit through the seventh resistor, and a second end of the coil of the relay is grounded through the eighth resistor; one end of the ninth resistor is electrically connected with the control circuit, and the other end of the ninth resistor is grounded; one contact of the relay is electrically connected with the signal interface, and the other contact of the relay is electrically connected with the circuit to be destroyed and the main processor.
In a second aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes the self-destruction circuit described above.
Compared with the prior art, the self-destruction circuit and the electronic equipment provided by the embodiment of the application comprise a signal sampling processing circuit, a first signal conversion circuit and a main processor, wherein when the electronic equipment receives a high-level self-destruction signal through a signal interface, on one hand, the first signal conversion circuit converts the high-level self-destruction signal into a power supply signal so as to supply power to the signal sampling processing circuit and the main processor; on the other hand, the signal sampling processing circuit converts the high-level self-destruction signal into a soft self-destruction signal and then sends the soft self-destruction signal to the main processor, and the main processor sends a soft self-destruction instruction to a circuit to be destroyed of the electronic equipment after determining that the soft self-destruction signal is effective, so that the circuit to be destroyed is self-destroyed. That is, once receiving the high level self-destruction signal, the high level self-destruction signal is utilized to supply power, so that the self-destruction effect of the circuit to be destroyed cannot be influenced no matter whether the electronic equipment is unstably powered on or powered off.
Drawings
Fig. 1 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.
Fig. 2 shows another schematic structural diagram of an electronic device provided in an embodiment of the present application.
Fig. 3 shows another schematic structural diagram of an electronic device provided in an embodiment of the present application.
Fig. 4 shows a circuit diagram of a signal sampling processing circuit provided in an embodiment of the present application.
Fig. 5 shows a circuit diagram of a first isolation circuit provided in an embodiment of the present application.
Fig. 6 shows a circuit diagram of a switch control circuit provided in an embodiment of the present application.
Fig. 7 shows a circuit diagram of a switching circuit provided in an embodiment of the present application.
Fig. 8 shows another circuit diagram of the switching circuit provided in the embodiment of the present application.
Icon: 10-an electronic device; 20-a signal interface; 30-a self-destruction circuit; 301-a first signal conversion circuit; 302-signal sampling processing circuitry; 303-a main processor; 304-a control circuit; 305-a second signal conversion circuit; 306-a switching circuit; 3011-a first power conversion circuit; 3012-a second isolation circuit; 3013-a second voltage divider circuit; 3051-a first isolation circuit; 3052-a second power conversion circuit; 3053-a first voltage dividing circuit; 3054-a third power conversion circuit; 3055-a switch control circuit; 3056-a fourth power conversion circuit; 40-a circuit to be destroyed; 50-a power supply; 60-other circuits.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an electronic device 10 according to an embodiment of the present disclosure. The electronic device 10 includes a signal interface 20, a self-destruction circuit 30 and a circuit to be destroyed 40, wherein the self-destruction circuit 30 is electrically connected between the signal interface 20 and the circuit to be destroyed 40.
The electronic device 10 may be a everyday commercial communication device, such as a smart phone, a tablet computer, a vehicle-mounted computer, a general-purpose computer, a special-purpose computer, a server, etc.; and the device can also be various vehicle-mounted and onboard devices in the military industry.
The electronic device 10 can receive the high-level self-destruction signal sent by the signal generating apparatus through the signal interface 20, that is, the high-level self-destruction signal is input to the self-destruction circuit 30 through the signal interface 20. The signal generating device may belong to the electronic device 10, or may belong to a device other than the electronic device 10. The voltage of the high-level self-destruction signal may be 18-36V, which is not limited herein.
The circuit to be destroyed 40 can be any storage device that stores important data such as private personal information, company business secrets, military secrets, etc., for example, various conventional data information storage media used by everyday business communication devices (e.g., smart phones, personal computers, etc.); or, the security chip used for storing the key or other sensitive data information in the military industry includes a PRM chip and a SIM chip.
The self-destruction circuit 30 includes a first signal conversion circuit 301, a signal sampling processing circuit 302, and a main processor 303. The first signal conversion circuit 301 has an input terminal electrically connected to the signal interface 20, and an output terminal electrically connected to the signal sampling processing circuit 302 and the main processor 303, respectively. The signal interface 20, the signal sampling processing circuit 302, the main processor 303 and the to-be-destroyed circuit 40 are electrically connected in sequence.
The first signal conversion circuit 301 is configured to receive the high-level self-destruction signal and convert the high-level self-destruction signal into a power supply signal to supply power to the signal sampling processing circuit 302 and the main processor 303.
The signal sampling processing circuit 302 is configured to receive the high-level self-destruction signal, convert the high-level self-destruction signal into a soft self-destruction signal, and send the soft self-destruction signal to the main processor 303.
And the main processor 303 is configured to send a soft self-destruction instruction to the circuit to be destroyed 40 to self-destroy the circuit to be destroyed 40 after determining that the soft self-destruction signal is valid.
On one hand, the high-level self-destruction signal input through the signal interface 20 can be converted into a power supply signal with the same power supply level as that of the signal sampling processing circuit 302 and the main processor 303 through the first signal conversion circuit 301, so as to supply power to the signal sampling processing circuit 302 and the main processor 303; on the other hand, the soft self-destruction signal can be converted into a soft self-destruction signal with a specified level through the signal sampling processing circuit 302 and sent to the main processor 303, wherein the value of the specified level is determined according to the I/O operating level of the main processor 303. After determining that the soft self-destruction signal is valid, the main processor 303 may send a soft self-destruction instruction to the circuit to be destroyed 40, so that the circuit to be destroyed 40 executes a preset self-destruction program according to the soft self-destruction instruction to realize self-destruction; thereby ensuring the normal realization of the soft self-destruction function.
Referring to fig. 2, the self-destruct circuit 30 further includes a control circuit 304. The control circuit 304 is electrically connected with the output end of the first signal conversion circuit 301, and the control circuit 304 is electrically connected with both the main processor 303 and the to-be-destroyed circuit 40.
The first signal conversion circuit 301 is further configured to transmit a power supply signal to the control circuit 304 to supply power to the control circuit 304.
The main processor 303 is further configured to send a soft self-destruction instruction to the control circuit 304 after determining that the soft self-destruction signal is valid.
The control circuit 304 is used for controlling the self-destruction of the circuit to be destroyed 40 according to the soft self-destruction instruction.
The high-level self-destruction signal inputted through the signal interface 20 can be converted into a power supply signal having the same power supply level as the control circuit 304 by the first signal conversion circuit 301, so as to supply power to the control circuit 304. After determining that the soft self-destruction signal is valid, the main processor 303 may further send a soft self-destruction instruction to the control circuit 304, so as to control the to-be-destroyed circuit 40 to implement self-destruction through a self-destruction program preset in the control circuit 304.
In some embodiments, the self-destruct circuit 30 also includes a second signal conversion circuit 305. The second signal conversion circuit 305 has an input terminal electrically connected to the power supply 50 of the electronic device 10, and an output terminal electrically connected to the signal sampling processing circuit 302, the main processor 303, the control circuit 304, and the other circuits 60 of the electronic device 10, respectively.
And the second signal conversion circuit 305 is configured to transmit the power supply signal provided by the power supply 50 to the signal sampling processing circuit 302, the main processor 303, the control circuit 304 and the other circuits 60 respectively to supply power to the signal sampling processing circuit 302, the main processor 303, the control circuit 304 and the other circuits 60 when the power supply 50 is normally powered.
The power supply 50 may be a conventional board-level dc power supply, and in a normal power supply state, the power supply 50 supplies power to the signal sampling processing circuit 302, the main processor 303, the control circuit 304 and the other circuits 60 through the second signal conversion circuit 305, so as to ensure normal operation of the circuits of the electronic device 10.
In some embodiments, the self-destruct circuit 30 also includes a switch circuit 306. The input end of the switch circuit 306 is electrically connected with the signal interface 20, the output end is electrically connected with the main processor 303 and the to-be-destroyed circuit 40 respectively, and the control end is electrically connected with the control circuit 304.
The main processor 303 is further configured to send a hard self-destruction instruction to the control circuit 304 after receiving the soft self-destruction completion signal returned by the to-be-destroyed circuit 40.
The control circuit 304 is further configured to control the switch circuit 306 to be turned on according to the hard self-destruction instruction, and transmit a high-level self-destruction signal to the circuit to be destroyed 40 and the main processor 303, so as to burn out the circuit to be destroyed 40 and the main processor 303.
In the normal power supplying state of the power supply 50, the switching circuit 306 is in an off state. After the electronic device 10 receives the high-level self-destruction signal through the signal interface 20, the self-destruction circuit 30 performs a soft self-destruction operation on the circuit to be destroyed 40. After the pending damage circuit 40 completes the soft self-damage, the pending damage circuit 40 returns a soft self-damage complete signal to the main processor 303. The main processor 303 sends a hard self-destruction instruction to the control circuit 304 after receiving the soft self-destruction completion signal. After the control circuit 304 receives the hard self-destruction instruction, the switch circuit 306 is controlled to be turned on, the high-level self-destruction signal directly flows to the power supply terminals of the circuit to be destroyed 40 and the main processor 303 through the switch circuit 306, and the circuit to be destroyed 40 and the main processor 303 are directly burned out through the high voltage and the large current of the high-level self-destruction signal, so that the circuit hard self-destruction function of the electronic device 10 is completed.
The structures of the first signal conversion circuit 301 and the second signal conversion circuit 305 are described below.
Referring to fig. 3, the second signal conversion circuit 305 includes a first isolation circuit 3051 and a switch control circuit 3055. The first isolation circuit 3051 has an input terminal electrically connected to the power supply 50, an output terminal electrically connected to the signal sampling processing circuit 302, the main processor 303, the control circuit 304, and the switch control circuit 3055, respectively, and a control terminal electrically connected to the control circuit 304. The switch control circuit 3055 is electrically connected to the other circuit 60.
The first isolation circuit 3051 is configured to transmit the power supply signal to the signal sampling processing circuit 302, the main processor 303, and the control circuit 304, and to transmit the power supply signal to the other circuits 60 through the switch control circuit 3055, respectively, when the power supply 50 is normally powered.
In some embodiments, the second signal conversion circuit 305 further includes a second power conversion circuit 3052, a first voltage divider circuit 3053, a third power conversion circuit 3054, a switch control circuit 3055, and a fourth power conversion circuit 3056.
The output terminal of the first isolation circuit 3051 is electrically connected to the second power conversion circuit 3052, the first voltage division circuit 3053, the third power conversion circuit 3054, and the switch control circuit 3055, respectively.
The second power conversion circuit 3052 is electrically connected to the signal sampling processing circuit 302 and the main processor 303, respectively, and is configured to convert a power signal into a power supply signal having the same power supply level as that of the signal sampling processing circuit 302 and the main processor 303, and supply power to the signal sampling processing circuit 302 and the main processor 303.
The first voltage divider 3053 is electrically connected to the control circuit 304 and is used for sending a normal power signal to the control circuit 304 to indicate that the control circuit 304 is in a normal power state for the power supply 50.
The control circuit 304 is electrically connected to the switch control circuit 3055, and is configured to control the switch control circuit 3055 to be turned on and off. In a normal power supply state of the power supply 50, the switch control circuit 3055 is in a conducting state; when the electronic device 10 receives the high-level self-destruction signal through the signal interface 20, i.e., is in a power-on state of the high-level self-destruction signal, the control circuit 304 controls the switch control circuit 3055 to turn off.
The third power conversion circuit 3054 is electrically connected to the control circuit 304, and is configured to convert the power signal into a power signal having the same power level as that of the control circuit 304, so as to supply power to the control circuit 304.
The switch control circuit 3055, the fourth power conversion circuit 3056, and the other circuit 60 are electrically connected in sequence, and the fourth power conversion circuit 3056 is configured to convert the power supply signal into a power supply signal having the same power supply level as that of the other circuit 60, and supply power to the other circuit 60.
Referring to fig. 3 again, the first signal conversion circuit 301 includes a first power conversion circuit 3011 and a second isolation circuit 3012. The first power conversion circuit 3011 has an input terminal electrically connected to the signal interface 20, and an output terminal electrically connected to the first isolation circuit 3051, the second isolation circuit 3012, and the control circuit 304, respectively. The second isolation circuit 3012 is electrically connected to the signal sampling processing circuit 302, the main processor 303, the control circuit 304, and the switch control circuit 3055, respectively.
The first power conversion circuit 3011 is configured to convert the high-level self-destruction signal into a power supply signal.
The first power conversion circuit 3011 is further configured to:
transmitting the power supply signal to the first isolation circuitry 3051 to turn off the first isolation circuitry 3051;
and, transmit the power supply signal to the control circuit 304, so that the control circuit 304 turns off the switch control circuit 3055 according to the power supply signal, and stops supplying power to the other circuits 60;
and transmitting the power supply signal to the signal sampling processing circuit 302, the main processor 303 and the control circuit 304 through the second isolation circuit 3012 to supply power to the signal sampling processing circuit 302, the main processor 303 and the control circuit 304.
In some embodiments, the first signal conversion circuit 301 further includes a second voltage division circuit 3013, where the second voltage division circuit 3013 is electrically connected to the control circuit 304 and is configured to send a self-destruction signal indication to the control circuit 304 to prompt the control circuit 304 to power up a high-level self-destruction signal at this time.
In a state where the power supply 50 is normally supplied with power, a power supply signal is transmitted to the second power conversion circuit 3052, the first voltage dividing circuit 3053 and the third power conversion circuit 3054 through the first isolation circuit 3051 and the switch control circuit 3055, and is input to the fourth power conversion circuit 3056 at the same time. The normal power supply signal indication is sent to the control circuit 304 through the first voltage division circuit 3053, converted into the power supply voltage required by the signal sampling processing circuit 302 and the main processor 303 through the second power supply conversion circuit 3052, converted into the power supply voltage required by the control circuit 304 through the third power supply conversion circuit 3054, and converted into the power supply voltage required by the other circuits 60 through the fourth power supply conversion circuit 3056, thereby ensuring normal power supply of the respective circuits of the electronic apparatus 10.
After the electronic device 10 receives the high-level self-destruction signal through the signal interface 20, the high-level self-destruction signal is input to the first power conversion circuit 3011, and the first power conversion circuit 3011 outputs a power supply signal. Then, transmission is carried out through three branches:
one branch transmits the power supply signal as an isolation control signal to the first isolation circuit 3051, so that the first isolation circuit 3051 is turned off;
the other branch sends a self-destruction signal instruction to the control circuit 304 through the second voltage division circuit 3013, and after receiving the instruction, the control circuit 304 sends a switch control signal to the switch control circuit 3055 to turn off the switch control signal, so that the power supply of other circuits 60 is turned off, the overall power consumption of the electronic device 10 is reduced, and the self-destruction function is prevented from being influenced by the overload of the high-level self-destruction signal;
the third branch is transmitted to the second power conversion circuit 3052 and the third power conversion circuit 3054 through the second isolation circuit 3012, converted into a power supply voltage required by the signal sampling processing circuit 302 and the main processor 303 through the second power conversion circuit 3052, and converted into a power supply voltage required by the control circuit 304 through the third power conversion circuit 3054, thereby ensuring normal power supply of the signal sampling processing circuit 302, the main processor 303, and the control circuit 304.
Referring to fig. 4, fig. 4 is a circuit diagram of a signal sampling processing circuit 302 according to an embodiment of the present disclosure. The signal sampling processing circuit 302 may be a comparator circuit including an operational amplifier U1 and a voltage dividing resistor.
As shown in fig. 2, the positive input terminal of the operational amplifier U1 is electrically connected to the signal interface 20 through series resistors R2 "and R1", one terminal of the resistor R3 "is electrically connected between the resistors R2" and R1", and the other terminal is grounded. One end of the resistor R4 'is electrically connected between the resistor R2' and the positive input end of the operational amplifier U1, and the other end is grounded. One end of the capacitor C1 "is electrically connected between the signal interface 20 and the resistor R1", and the other end is grounded. The negative input terminal of the operational amplifier U1 is electrically connected to the second power conversion circuit 3052 through a resistor R5", and a resistor R6" has one end electrically connected between the resistor R5 "and the negative input terminal of the operational amplifier U1 and the other end grounded. The output of the operational amplifier U1 is electrically connected to the main processor 303 through resistor R8'. One end of the resistor R5 ' is electrically connected with the negative input end of the operational amplifier U1, the other end is electrically connected with the output end of the operational amplifier U1, and the capacitor C3 ' is connected in parallel with two ends of the resistor R5 '.
In the normal power state of the power supply 50, the positive input terminal of the operational amplifier U1 has a lower level than the negative input terminal, and the output is at a low level. When the high-level self-destruction signal is detected, the level of the positive input end answers the negative input end, and the output is high level, namely, the soft self-destruction signal is output.
Optionally, the first power conversion circuit 3011 is mainly composed of a power chip or a power module meeting the power supply index of the device, and mainly functions to convert the high-level self-destruction signal into a power supply signal and provide the self-destruction circuit 30 with necessary electric energy and a self-destruction determination signal.
Optionally, the main processor 303 is mainly composed of a combination of a DSP and an FPGA (Field Programmable Gate Array) or other high-performance processing chip and peripheral circuits, and is configured to complete all functions of signal processing, resolving, storing, and the like when the electronic device 10 operates normally, so as to ensure that each function of the electronic device 10 is implemented. When the electronic device 10 is in soft self-destruction, the highest priority self-destruction instruction is processed and sent out, so that the soft self-destruction function of the electronic device 10 is normally completed. In the case of hard self-destruction, the main processor 303 and the to-be-destroyed circuit 40 are burnt out together, so as to improve the self-destruction thoroughness of the electronic device 10.
It should be noted that the main processor 303 may also be a processor of the electronic device 10 itself. In practical application, the selection can be flexibly selected according to practical situations, and is not limited herein.
Alternatively, the control circuit 304 may be formed by a simple and fast processing chip such as a single chip, and is used to complete the control of the relevant execution-level instruction.
It should be noted that the control circuit 304 may also be a controller of the electronic device 10 itself. In practical application, the selection can be flexibly selected according to practical situations, and is not limited herein.
Referring to fig. 5, fig. 5 is a circuit diagram of a first isolation circuit 3051 according to an embodiment of the present disclosure. The first isolation circuit 3051 includes a first MOS transistor, a first resistor R1, and a second resistor R2. The drain of the first MOS transistor is electrically connected to the power supply 50, and the source of the first MOS transistor is electrically connected to the signal sampling processing circuit 302, the main processor 303, the control circuit 304, and the switch control circuit 3055, respectively. The gate of the first MOS transistor is electrically connected to the output terminal of the first power conversion circuit 3011 through a first resistor R1, and one end of a second resistor R2 is electrically connected to the gate of the first MOS transistor, and the other end is grounded.
The first MOS transistor may be a P-channel MOS transistor, and mainly functions to control the VGS level and turn off the first isolation circuit 3051 when a high-level self-destruction signal occurs, so as to prevent the converted self-destruction signal from flowing backward to the power supply 50. The MOS tube is selected for use, and the method has the advantages that: the forward voltage drop is small (about 60 mV), the power supply signal passes through the circuit, the voltage drop is small, no influence is caused on the normal work of each circuit of the rear stage, and the switch can be controlled by a self-destruction signal through a pin, so that the working stability of the equipment is improved.
Alternatively, the second isolation circuit 3012 is mainly composed of a low-dropout, high-power schottky diode having a P-terminal connected to the input and an N-terminal connected to the output, and conducting in the forward direction. When the power supply 50 supplies power normally, the current flows back to the first power conversion circuit, so that the self-destruction program is triggered by mistake and the electronic equipment 10 is prevented from being damaged.
Referring to fig. 6, fig. 6 is a circuit diagram of a switch control circuit 3055 according to an embodiment of the present disclosure. The switch control circuit 3055 includes a second MOS transistor, a first transistor, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a first capacitor C1.
The source of the second MOS transistor is electrically connected to the first isolation circuit 3051. One end of the first capacitor C1 is electrically connected to the source of the second MOS transistor, and the other end is grounded. The drain of the second MOS transistor is electrically connected to the other circuit 60. The grid electrode of the second MOS tube is electrically connected with the collector electrode of the first triode through a third resistor R3. One end of the fourth resistor R4 is electrically connected to the source of the second MOS transistor, and the other end is electrically connected to the gate of the second MOS transistor. The base of the first transistor is electrically connected to the control circuit 304 through a fifth resistor R5. One end of the sixth resistor R6 is electrically connected to the control circuit 304, and the other end is grounded. The emitter of the first triode is grounded.
The first transistor may be an NPN transistor, and the second MOS transistor may be a P-channel MOS transistor. In the normal power supply state of the power supply 50, the switch control signal output by the control circuit 304 is high, the gate to the drain of the second MOS transistor is turned on, and all the other circuits 60 operate normally. When the control circuit 304 receives the self-destruction signal indication, the switch control signal output by the control circuit 304 is low, the gate to drain of the second MOS transistor is disconnected, and the whole electronic device 10 stops working except for the circuit required for self-destruction, so that the power consumption is reduced, the high-level self-destruction signal can be stably output, and the high-level self-destruction signal is prevented from being overloaded to influence the realization of the self-destruction function.
Referring to fig. 7, fig. 7 is a circuit diagram of a switch circuit 306 according to an embodiment of the present disclosure. The switch circuit 306 includes a relay, a second capacitor C2, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.
A first end of the coil of the relay is electrically connected to the control circuit 304 through a seventh resistor R7, and a second end is grounded through an eighth resistor R8. One end of the ninth resistor R9 is electrically connected to the control circuit 304, and the other end is grounded. One contact of the relay is electrically connected to the signal interface 20 and the other contact is electrically connected to both the pending damage circuit 40 and the main processor 303.
Referring to fig. 8, fig. 8 is a circuit diagram of another switching circuit 306 according to an embodiment of the present disclosure. The switch circuit 306 comprises a MOS transistor, a triode, a resistor R10, a resistor R11, a resistor R12, a resistor R13 and a capacitor C10.
The source of the MOS transistor is electrically connected to the signal interface 20. One end of the capacitor C10 is electrically connected with the source electrode of the MOS tube, and the other end is grounded. The drain of the MOS transistor is electrically connected with the circuit to be destroyed 40 and the main processor 303. The gate of the MOS transistor is electrically connected with the collector of the triode through a resistor R10. One end of the resistor R11 is electrically connected with the source electrode of the MOS tube, and the other end is electrically connected with the grid electrode of the MOS tube. The base of the transistor is electrically connected to control circuit 304 through resistor R12. One end of the resistor R13 is electrically connected to the control circuit 304, and the other end is grounded. The emitter of the triode is grounded. The triode can be an NPN type triode, and the MOS tube can be a P-channel MOS tube.
In the normal power supplying state of the power supply 50, the control circuit 304 outputs the hard self-destruct switch control signal low, and the gate-to-drain of the MOS transistor in fig. 7 is disconnected or the relay in fig. 8 is disconnected. When the control circuit 304 receives the hard self-destruction instruction sent by the main processor 303, the control circuit 304 outputs a hard self-destruction switch control signal to be high, the gate to the drain of the MOS transistor in fig. 7 is conducted or the relay in fig. 8 is conducted, the high-level self-destruction signal directly flows to the circuit to be destroyed 40 and the main processor 303, the circuit to be destroyed 40 and the main processor 303 are burnt, and the hard self-destruction of the device is completed.
Optionally, the second power conversion circuit 3052 is formed by various power chips (e.g., DCDC power, LDO power, etc.) and peripheral circuits, and is used for providing various dc power for the main processor 303 and the to-be-destroyed circuit 40 to operate normally.
Optionally, the third power conversion circuit 3054 is formed by various power chips (e.g., a DCDC power supply, an LDO power supply, etc.) and peripheral circuits, and is configured to provide a normally operating dc power for the control circuit 304, so as to ensure that the control circuit 304 is not affected by a self-destruction signal during a self-destruction process of the device, and improve stability of the device.
The first voltage divider 3053 and the second voltage divider 3013 may be formed by voltage dividing resistors with corresponding values, and are configured to reduce the high-level indication signal to a level range suitable for the control circuit 304, so as to prevent the indication signal from being too high and damaging the relevant chips of the control circuit 304.
Compared with the prior art, the embodiment of the application has the following beneficial effects:
firstly, once a high-level self-destruction signal is received, the high-level self-destruction signal is utilized to supply power, so that the self-destruction effect of the circuit to be destroyed 40 cannot be influenced no matter whether the power supply of the electronic equipment 10 is unstable or the power is cut off;
secondly, after the circuit to be destroyed 40 completes the soft self-destruction, the control circuit 304 controls the switch circuit 306 to be conducted, the high-level self-destruction signal directly flows to the power supply terminals of the circuit to be destroyed 40 and the main processor 303 through the switch circuit 306, and the circuit to be destroyed 40 and the main processor 303 are directly burned out through the high voltage and the large current of the high-level self-destruction signal, so that the circuit hard self-destruction function of the electronic device 10 is completed. Namely, the soft and hard dual self-destruction can be completed, the non-restorability of the circuit 40 to be destroyed is ensured, and the safety of important data is greatly improved.
To sum up, the self-destruction circuit and the electronic device provided by the embodiment of the application utilize the high-level self-destruction signal to supply power once the high-level self-destruction signal is received, so that the self-destruction effect of the circuit to be destroyed cannot be influenced no matter whether the electronic device is unstable in power supply or is powered off. Meanwhile, soft and hard dual self-destruction can be completed, the non-restorability of the circuit 40 to be destroyed is ensured, and the safety of important data is greatly improved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A self-destruction circuit is applied to electronic equipment and comprises a signal sampling processing circuit, a first signal conversion circuit and a main processor;
the input end of the first signal conversion circuit is electrically connected with a signal interface of the electronic equipment, and the output end of the first signal conversion circuit is electrically connected with the signal sampling processing circuit and the main processor; the signal interface, the signal sampling processing circuit, the main processor and a circuit to be destroyed of the electronic equipment are electrically connected in sequence;
the first signal conversion circuit is used for receiving a high-level self-destruction signal and converting the high-level self-destruction signal into a power supply signal to supply power to the signal sampling processing circuit and the main processor;
the signal sampling processing circuit is used for receiving the high-level self-destruction signal, converting the high-level self-destruction signal into a soft self-destruction signal and then sending the soft self-destruction signal to the main processor;
and the main processor is used for sending a soft self-destruction instruction to the circuit to be destroyed to enable the circuit to be destroyed by self after the soft self-destruction signal is determined to be effective.
2. The self-destruct circuit of claim 1, further comprising a control circuit electrically connected to an output of the first signal conversion circuit, the control circuit electrically connected to both the main processor and the circuit to be destructed;
the first signal conversion circuit is further used for transmitting the power supply signal to the control circuit to supply power to the control circuit;
the main processor is further used for sending a soft self-destruction instruction to the control circuit after the soft self-destruction signal is determined to be valid;
and the control circuit is used for controlling the self-destruction of the circuit to be destroyed according to the soft self-destruction instruction.
3. The self-destruction circuit of claim 2, further comprising a switch circuit, wherein an input end of the switch circuit is electrically connected with the signal interface, an output end of the switch circuit is electrically connected with the main processor and the circuit to be destroyed respectively, and a control end of the switch circuit is electrically connected with the control circuit;
the main processor is also used for sending a hard self-destruction instruction to the control circuit after receiving a soft self-destruction completion signal returned by the circuit to be destroyed;
the control circuit is further configured to control the switch circuit to be turned on according to the hard self-destruction instruction, and transmit the high-level self-destruction signal to the circuit to be destroyed and the main processor, so as to burn the circuit to be destroyed and the main processor.
4. The self-destruction circuit of claim 2, further comprising a second signal conversion circuit, wherein an input end of the second signal conversion circuit is electrically connected with a power supply of the electronic device, and an output end of the second signal conversion circuit is electrically connected with the signal sampling processing circuit, the main processor, the control circuit and other circuits of the electronic device respectively;
and the second signal conversion circuit is used for respectively transmitting the power supply signal provided by the power supply to the signal sampling processing circuit, the main processor, the control circuit and the other circuits when the power supply is normally supplied with power, and supplying power to the signal sampling processing circuit, the main processor, the control circuit and the other circuits.
5. The self-destruct circuit of claim 4, wherein the second signal conversion circuit comprises a first isolation circuit and a switch control circuit;
the input end of the first isolation circuit is electrically connected with the power supply, the output end of the first isolation circuit is electrically connected with the signal sampling processing circuit, the main processor, the control circuit and the switch control circuit respectively, and the control end of the first isolation circuit is electrically connected with the control circuit; the control circuit is electrically connected with the switch control circuit, and the switch control circuit is electrically connected with the other circuits;
the first isolation circuit is used for respectively transmitting the power supply signal to the signal sampling processing circuit, the main processor and the control circuit when the power supply is normally powered, and transmitting the power supply signal to the other circuits through the switch control circuit.
6. The self-destruct circuit of claim 5, wherein the first signal conversion circuit comprises a first power conversion circuit and a second isolation circuit;
the input end of the first power supply conversion circuit is electrically connected with the signal interface, and the output end of the first power supply conversion circuit is electrically connected with the first isolation circuit, the second isolation circuit and the control circuit respectively; the second isolation circuit is respectively and electrically connected with the signal sampling processing circuit, the main processor, the control circuit and the switch control circuit;
the first power supply conversion circuit is used for converting the high-level self-destruction signal into the power supply signal;
the first power conversion circuit is further configured to:
transmitting the power supply signal to the first isolation circuit to turn off the first isolation circuit;
transmitting the power supply signal to the control circuit to enable the control circuit to turn off the switch control circuit according to the power supply signal and stop supplying power to other circuits;
and transmitting the power supply signal to the signal sampling processing circuit, the main processor and the control circuit through the second isolation circuit to supply power to the signal sampling processing circuit, the main processor and the control circuit.
7. The self-destruct circuit of claim 6, wherein the first isolation circuit comprises a first MOS transistor, a first resistor and a second resistor;
the drain electrode of the first MOS tube is electrically connected with the power supply, and the source electrode of the first MOS tube is respectively and electrically connected with the signal sampling processing circuit, the main processor, the control circuit and the switch control circuit; the grid electrode of the first MOS tube is electrically connected with the output end of the first power supply conversion circuit through the first resistor, one end of the second resistor is electrically connected with the grid electrode of the first MOS tube, and the other end of the second resistor is grounded.
8. The self-destruction circuit of claim 6, wherein the switch control circuit comprises a second MOS transistor, a first triode, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a first capacitor;
the source electrode of the second MOS tube is electrically connected with the first isolation circuit; one end of the first capacitor is electrically connected with the source electrode of the second MOS tube, and the other end of the first capacitor is grounded; the drain electrode of the second MOS tube is electrically connected with the other circuit; the grid electrode of the second MOS tube is electrically connected with the collector electrode of the first triode through the third resistor; one end of the fourth resistor is electrically connected with the source electrode of the second MOS tube, and the other end of the fourth resistor is electrically connected with the grid electrode of the second MOS tube;
the base electrode of the first triode is electrically connected to the control circuit through the fifth resistor; one end of the sixth resistor is electrically connected with the control circuit, and the other end of the sixth resistor is grounded; and the emitter of the first triode is grounded.
9. The self-destruct circuit of claim 3, wherein the switching circuit comprises a relay, a second capacitor, a seventh resistor, an eighth resistor, and a ninth resistor;
a first end of a coil of the relay is electrically connected to the control circuit through the seventh resistor, and a second end of the coil of the relay is grounded through the eighth resistor; one end of the ninth resistor is electrically connected with the control circuit, and the other end of the ninth resistor is grounded; one contact of the relay is electrically connected with the signal interface, and the other contact of the relay is electrically connected with the circuit to be destroyed and the main processor.
10. An electronic device, characterized in that the electronic device comprises a self-destruct circuit according to any one of claims 1-9.
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| CN202110062347.9A CN112711779B (en) | 2021-01-18 | 2021-01-18 | Self-destruction circuit and electronic equipment |
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| CN202110062347.9A CN112711779B (en) | 2021-01-18 | 2021-01-18 | Self-destruction circuit and electronic equipment |
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| CN112711779B CN112711779B (en) | 2024-03-29 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080284561A1 (en) * | 2007-05-14 | 2008-11-20 | Inventec Corporation | Method for protecting data |
| CN102324003A (en) * | 2011-05-20 | 2012-01-18 | 哈尔滨工业大学 | Multi-strategy self-destruction method for high-trust embedded computer |
| US8812875B1 (en) * | 2010-04-12 | 2014-08-19 | Stephen Melvin | Virtual self-destruction of stored information |
| CN204719761U (en) * | 2015-06-04 | 2015-10-21 | 鸿秦（北京）科技有限公司 | A kind of intelligence destroys solid state hard disc |
| CN206258877U (en) * | 2016-11-04 | 2017-06-16 | 上海控易电子科技有限公司 | A kind of data protection destruct system |
| CN107563227A (en) * | 2017-08-31 | 2018-01-09 | 中国人民解放军海军医学研究所 | The terminal device that anti-data are stolen secret information |
| CN109583243A (en) * | 2018-12-10 | 2019-04-05 | 中国运载火箭技术研究院 | A kind of data safety guard system based on instruction |
| CN111143903A (en) * | 2020-01-14 | 2020-05-12 | 合肥市卓怡恒通信息安全有限公司 | Data destruction circuit |
-
2021
- 2021-01-18 CN CN202110062347.9A patent/CN112711779B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080284561A1 (en) * | 2007-05-14 | 2008-11-20 | Inventec Corporation | Method for protecting data |
| US8812875B1 (en) * | 2010-04-12 | 2014-08-19 | Stephen Melvin | Virtual self-destruction of stored information |
| CN102324003A (en) * | 2011-05-20 | 2012-01-18 | 哈尔滨工业大学 | Multi-strategy self-destruction method for high-trust embedded computer |
| CN204719761U (en) * | 2015-06-04 | 2015-10-21 | 鸿秦（北京）科技有限公司 | A kind of intelligence destroys solid state hard disc |
| CN206258877U (en) * | 2016-11-04 | 2017-06-16 | 上海控易电子科技有限公司 | A kind of data protection destruct system |
| CN107563227A (en) * | 2017-08-31 | 2018-01-09 | 中国人民解放军海军医学研究所 | The terminal device that anti-data are stolen secret information |
| CN109583243A (en) * | 2018-12-10 | 2019-04-05 | 中国运载火箭技术研究院 | A kind of data safety guard system based on instruction |
| CN111143903A (en) * | 2020-01-14 | 2020-05-12 | 合肥市卓怡恒通信息安全有限公司 | Data destruction circuit |
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|---|---|
| CN112711779B (en) | 2024-03-29 |
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