CN111952239B - Semiconductor substrate with cavity structure and preparation method thereof - Google Patents

Abstract

The present invention provides a semiconductor substrate with a cavity structure and a preparation method thereof, the preparation method comprising: providing a first substrate and a second substrate, performing ion implantation in the first substrate to form a preset peeling layer, a preset distance between the preset peeling layer and the cavity structure to be formed, the preset distance being greater than 1/8 of the cavity characteristic size of the cavity structure, bonding the first substrate and the second substrate, and peeling along the preset peeling layer to obtain a semiconductor substrate with a cavity structure. The present invention prefabricates a preset peeling layer according to the cavity structure to be formed when performing ion implantation to form a peeling interface, the preset distance between the preset peeling layer and the cavity structure to be formed being greater than 1/8 of the cavity characteristic size of the cavity structure, thereby ensuring that the material layer above the cavity structure is not damaged during the process of preparing the semiconductor substrate with the cavity structure, thereby improving the device yield and performance.

Description

Semiconductor substrate with cavity structure and preparation method thereof

Technical Field

The invention belongs to the technical field of semiconductor device structure design and manufacturing, and in particular relates to a semiconductor substrate with a cavity structure and a preparation method thereof.

Background technique

A cavity is prepared inside the semiconductor substrate, which can play an insulating role. Semiconductor functional devices can be prepared on the cavity, which can maintain good subthreshold characteristics of the device. In order to improve the performance and performance-price ratio of integrated circuit chips, reducing the device feature size and thus improving the integration is a major way. However, as the size of the device decreases, power consumption and leakage current become the most concerned issues. The silicon-on-insulator SOI (Silicon-On-Insulator) structure has become the preferred structure for deep submicron MOS devices because it can well suppress the short channel effect and improve the ability of the device to be scaled down. With the continuous development of SOI technology, researchers have developed a new transistor structure SON (Silicon on nothing) transistor. SON forms a localized silicon-on-insulator under the channel through a "hole" structure. SON technology is a method to reduce the short channel effect of SOI devices. Compared with SO1 devices, SON devices remove the buried oxide layer under the channel, reduce the interface state at the bottom of the top silicon, reduce the influence of the body charge in the buried oxide layer on the conductive characteristics of the channel, reduce the parasitic capacitance between the channel and the substrate, and make the device have good total dose radiation resistance. Compared with SOI devices, SON devices have a certain degree of enhanced ability to suppress short channel effects because the back charge and capacitance effects are eliminated.

However, in the existing process of preparing semiconductor substrates with cavities, it is often necessary to perform smart-cut along the stripping layer. For example, when preparing a SON substrate, it is necessary to perform smart-cut on the top silicon. For example, taking the injection of hydrogen ions to form a stripping layer as an example, during the smart stripping process, hydrogen bubbles are generated at the stripping interface, and the hydrogen bubbles exert a large pressure on the stripping layer, thereby causing the final stripping layer to be damaged. When part of the top silicon in the SON substrate is damaged, the substrate cannot meet the application requirements of integrated circuits, micro-electromechanical systems, etc. In the existing process, if the cavity size is large, the material layer above the cavity (such as the top silicon) is prone to damage. As shown in FIG26, the damage of the top silicon above the cavity for cavity structures of different sizes in the prior art is shown. As the cavity size increases, the probability of damage to the top silicon above the cavity increases rapidly, and cracks appear at the edges of some cavities that are not completely damaged. This seriously affects the yield and performance of the device.

Therefore, it is necessary to provide a semiconductor substrate with a cavity structure and a preparation method thereof to solve the above technical problems in the prior art.

Summary of the invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor substrate with a cavity structure and a preparation method thereof, so as to solve the problem that the material layer above the cavity is easily damaged when preparing a substrate with a cavity in the prior art.

To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor substrate having a cavity structure, the preparation method comprising the steps of:

Providing a first substrate and a second substrate;

Performing ion implantation on the first substrate to form a preset peeling layer in the first substrate, wherein a preset distance exists between the preset peeling layer and the cavity structure to be formed, and the preset distance is set according to the cavity structure, wherein the setting method includes that the preset distance is greater than 1/8 of the cavity characteristic size of the cavity structure;

The method for defining the characteristic size of the cavity includes: defining a two-dimensional plane above the cavity structure and parallel to the surface of the cavity structure; in the two-dimensional plane, there are a plurality of selected points above the cavity structure; for each of the selected points, there are a plurality of straight lines passing through the selected point; each of the straight lines has at least two contact points with the edge of the cavity structure, a first contact point and a second contact point adjacent to the selected point in two directions of the straight line passing through the selected point are selected, and the distance between the first contact point and the second contact point is defined as the cavity size; the minimum cavity size is obtained based on the plurality of straight lines passing through each of the selected points; based on the plurality of selected points above the cavity structure, the maximum value of all the cavity sizes is selected to obtain the characteristic size of the cavity;

Bonding the side of the first substrate subjected to the ion implantation and the second substrate to obtain an initial bonding structure, wherein the initial bonding structure comprises a patterned dielectric layer having the cavity structure, and a gap exists between the patterned dielectric layer and the preset peeling layer; and

The first substrate is peeled off along the preset peeling layer, so that a portion of the first substrate is transferred to the patterned dielectric layer to form a transfer substrate film layer on the patterned dielectric layer, thereby obtaining a semiconductor substrate with a cavity structure.

Optionally, the first substrate includes a first semiconductor substrate, the preset peeling layer is formed in the first semiconductor substrate, the second substrate includes a second semiconductor substrate and the patterned dielectric layer formed on the second semiconductor substrate, and the side of the first substrate where the ion implantation is performed is bonded to the patterned dielectric layer of the second substrate.

Optionally, before performing the ion implantation, the method further includes the steps of: forming a sacrificial dielectric layer on the surface of the first semiconductor substrate, performing the ion implantation from the side where the sacrificial dielectric layer is formed, and removing the sacrificial dielectric layer after completing the ion implantation.

Optionally, an isolation layer is formed between the second semiconductor substrate and the patterned dielectric layer, and the cavity structure exposes the isolation layer.

Optionally, the first substrate includes a first semiconductor substrate and the patterned dielectric layer formed on the first semiconductor substrate, the preset peeling layer is formed in the first semiconductor substrate, and the second substrate includes a second semiconductor substrate, wherein the patterned dielectric layer of the first substrate is bonded to the second substrate.

Optionally, the step of forming the first base includes: providing the first semiconductor substrate; forming a sacrificial dielectric layer on the first semiconductor substrate; performing the ion implantation on the first semiconductor substrate from the side where the sacrificial dielectric layer is formed; and patterning the sacrificial dielectric layer to obtain the patterned dielectric layer having the cavity structure.

Optionally, the second substrate further includes an isolation layer formed on the second semiconductor substrate, the isolation layer is bonded to the patterned dielectric layer of the first substrate, and the cavity structure in the patterned dielectric layer exposes the isolation layer.

Optionally, the step of performing the ion implantation to form the preset stripping layer includes: performing a first ion implantation on the first substrate to form an initial stripping layer in the first substrate; performing a second ion implantation at the position of the initial stripping layer to form the preset stripping layer, wherein the implanted particles of the first ion implantation include B-containing impurities, and the implanted particles of the second ion implantation include at least one of H ions and He ions.

Optionally, the implantation dose of the first ion implantation is smaller than the implantation dose of the second ion implantation; wherein the implantation dose of the first ion implantation is between 1e11 and 1e13/cm ² , and the implantation dose of the second ion implantation is between 1e16 and 1e17/cm ² .

Optionally, after peeling off the first base along the preset peeling layer, the method includes the step of: performing a reinforcement treatment on the semiconductor substrate with the cavity structure, wherein the reinforcement treatment includes heating the semiconductor substrate with the cavity structure.

Optionally, the heating treatment is performed under a preset atmosphere, which includes an oxygen atmosphere to form a surface oxide layer on the surface of the transfer substrate film layer, and the surface oxide layer is removed after the heating treatment is completed to thin the transfer substrate film layer.

Optionally, the cavity structure further extends into a material layer below the patterned dielectric layer.

Optionally, the preset distance between the preset peeling layer and the cavity structure is between 2 nm and 10 μm.

Optionally, the method for setting the ratio of the preset distance to the characteristic size of the cavity structure includes: defining the pressure on the upper surface of the cavity structure during the peeling process as p, defining the length of the cavity structure in the pointing plane as infinite, defining the worst case as the center position of the transfer substrate film layer above the cavity with only the patterned dielectric layer as support points on both sides, and obtaining the maximum stress Mmax∝pL2 and the maximum stress σmax∝qL2/h2 in the transfer substrate film layer, wherein h is the preset distance, and L is the characteristic size of the cavity structure, and based on the maximum stress that the transfer substrate film layer can withstand, the ratio of the preset distance to the characteristic size of the cavity structure is obtained by experimental design.

Optionally, after obtaining the semiconductor substrate with a cavity structure, the method further includes the step of thinning the transferred film layer structure, wherein the thinning process includes a first thinning process using a chemical mechanical polishing process and a second thinning process using an oxidation thinning process.

Optionally, after the thinning treatment, the step of: repairing the surface after the thinning treatment to make the surface after the thinning treatment atomically flat, the repairing treatment includes annealing the semiconductor substrate with a cavity structure in a hydrogen atmosphere, and the annealing temperature is between 800°C and 1300°C.

The present invention further provides a semiconductor substrate structure with a cavity structure, wherein the semiconductor substrate with a cavity structure is preferably prepared by the method for preparing a semiconductor substrate with a cavity structure of the present invention, and of course, it can also be prepared by other methods. The semiconductor substrate structure includes:

The first substrate comprises a cavity upper film layer, wherein the cavity upper film layer is obtained by thinning the transfer substrate film layer;

A second substrate bonded to the first substrate, wherein the second substrate comprises a second semiconductor substrate;

A patterned dielectric layer having a cavity structure is formed between the second semiconductor substrate and the cavity upper film layer, the transfer substrate film layer has a first surface close to the cavity structure and a second surface opposite to the first surface, and the distance between the second surface and the cavity structure is greater than 1/8 of the cavity characteristic size of the cavity structure.

Optionally, an isolation layer is formed between the second semiconductor substrate and the patterned dielectric layer, and the cavity structure exposes the isolation layer.

Optionally, the cavity structure penetrates the patterned dielectric layer and further extends into at least one of the second semiconductor substrate and the transfer substrate film layer.

As described above, in the semiconductor substrate with a cavity structure and the preparation method thereof of the present invention, a preset peeling layer is prefabricated according to the cavity structure to be formed when ion implantation is performed to form a peeling interface, and the preset distance between the preset peeling layer and the cavity structure to be formed is greater than 1/8 of the cavity characteristic size of the cavity structure, thereby ensuring that the material layer above the cavity structure is not damaged during the process of preparing the semiconductor substrate with a cavity structure, thereby improving the device yield and performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a method for preparing a semiconductor substrate with a cavity structure provided in an embodiment of the present invention.

2-21 are schematic diagrams showing the structures obtained in each step of the preparation process of a semiconductor substrate with a cavity structure provided in an embodiment of the present invention.

FIG. 22 illustrates the cavity feature size of a cavity structure having a rectangular shape during the formation of a preset peeling layer.

FIG. 23 is a three-dimensional diagram of a SON structure prepared based on the solution of the present invention.

FIG. 24( a ) and FIG. 24( b ) are schematic diagrams showing that at least one end of the support structure is in contact with the side wall of the cavity structure in an embodiment of the present invention.

Figures 25(a) and 25(b) are schematic diagrams showing a support structure located within a cavity structure in an embodiment of the present invention.

FIG. 26 shows the damage of the top silicon layer on cavities of different sizes in the prior art.

FIG. 27 shows that when the top silicon peeling thickness (top silicon thickness is 1 μm) is less than or equal to 1/8 of the cavity feature size, the top silicon above the cavity is damaged to varying degrees.

FIG. 28 shows the damage of the top silicon layer on cavities of different sizes when the preset peeling layer is formed using the solution of the present invention.

FIG. 29 shows a SON substrate having a large-area, high-density closed cavity structure prepared using the solution of the present invention.

FIG30 is a schematic diagram showing the force on the material layer above the cavity structure during the smart peeling process.

FIG31 shows that at the midline position of the peeling layer corresponding to the cavity, the upper and lower edges are subjected to the maximum compressive stress and tensile stress, and the lower edge is prone to damage.

Component number description

100 First Base

101 first semiconductor substrate

101a Pre-set peeling layer

102 Sacrificial dielectric layer

103 Patterned dielectric layer

103a Cavity structure

104 Transfer substrate film layer

105 Surface oxide layer

106 Structure after thinning

107 Cavity upper membrane layer

200 Second Base

201 second semiconductor substrate

202 Isolation Layer

203 Patterned dielectric layer

203a Cavity structure

Steps S1 to S4

Detailed ways

The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

As shown in FIG. 1 , the present invention provides a method for preparing a semiconductor substrate having a cavity structure, comprising the steps of:

S1: providing a first substrate and a second substrate;

S2: performing ion implantation on the first substrate to form a preset peeling layer in the first substrate, wherein a preset distance exists between the preset peeling layer and the cavity structure to be formed, and the preset distance is set according to the cavity structure, wherein the setting method includes that the preset distance is greater than 1/8 of the cavity characteristic size of the cavity structure;

S3: bonding the side of the first substrate subjected to the ion implantation to the second substrate to obtain an initial bonding structure, wherein the initial bonding structure comprises a patterned dielectric layer having the cavity structure, and a gap exists between the patterned dielectric layer and the preset peeling layer; and

S4: peeling off the first substrate along the preset peeling layer, so that a portion of the first substrate is transferred to the patterned dielectric layer to form a transfer substrate film layer on the patterned dielectric layer, and obtaining a semiconductor substrate with a cavity structure.

The following will describe in detail the method for preparing a semiconductor substrate with a cavity structure of the present invention in conjunction with the accompanying drawings. It should be noted that the above sequence does not strictly represent the preparation sequence of the method for preparing a semiconductor substrate with a cavity structure protected by the present invention. Those skilled in the art can change the sequence of steps according to the actual process. For example, providing the second substrate can be provided after the step of ion implanting the first substrate to form a preset peeling layer. FIG1 only shows the preparation steps of the method for preparing a semiconductor substrate with a cavity structure in an example of the present invention.

Embodiment 1:

This embodiment 1 provides a specific method for preparing a semiconductor substrate with a cavity structure. First, as shown in S1 in Figure 1 and Figures 2 and 5-7, step S1 is performed to provide a first substrate 100 and a second substrate 200. The first substrate 100 and the second substrate 200 are used to prepare the semiconductor substrate with a cavity structure of the present invention, and the two can be provided according to the actual process method. Among them, the first substrate 100 can be a substrate composed of a single layer of material layer, or a substrate composed of a stacked material layer structure. Similarly, the first substrate 200 can be a substrate composed of a single layer of material layer, or a substrate composed of a stacked material layer structure.

As an example, as shown in FIG2 , the first base 100 includes a first semiconductor substrate 101, and a preset peeling layer formed by subsequent ion implantation is formed in the first semiconductor substrate 101. The first semiconductor substrate 101 may be a material layer of Si, Ge, GaN, SiC, GaAs, AlGaN, Ga ₂ O ₃ , InP, or a combination of two or more of the above material layers. Of course, it may also be other crystalline semiconductors, and is not limited thereto.

In a further optional example, the first base 100 further includes a sacrificial dielectric layer 102 formed on the first semiconductor substrate 101, and the sacrificial dielectric layer 102 may be a SiO ₂ , silicon nitride, silicon oxynitride, aluminum oxide material layer, or a combination of two or more of the above material layers. Of course, it may also be other insulating sacrificial dielectric layers, but is not limited thereto. The sacrificial dielectric layer 102 may be formed on the first semiconductor substrate 101 by, but is not limited to, thermal oxidation. The sacrificial dielectric layer 102 may protect the surface of the first semiconductor substrate 101 in subsequent processes such as ion implantation, and may also be used for the preparation of a device functional layer, and may be selected for use according to the actual preparation requirements of the device.

As an example, as shown in FIGS. 5-7 , the second base 200 includes a second semiconductor substrate 201 and the patterned dielectric layer 203 formed on the second semiconductor substrate 201 , as shown in FIG. 6 . The second semiconductor substrate 201 may be a material layer of Si, Ge, GaN, SiC, GaAs, AlGaN, Ga ₂ O ₃ , InP, or a combination of two or more of the above material layers. Of course, it may also be other crystalline semiconductors, but is not limited thereto. In addition, a cavity structure 203a is formed in the patterned dielectric layer 203 to be used as the cavity structure in the semiconductor substrate with a cavity structure obtained later. The patterned dielectric layer 203 may be a material layer of SiO ₂ , silicon nitride, silicon oxynitride, aluminum oxide, or a combination of two or more of the above material layers. Of course, it may also be other insulating sacrificial dielectric layers, but is not limited thereto. In addition, the number and arrangement of the cavity structures 203a may be set according to actual needs, such as being arranged in a periodic array.

In a further optional example, as shown in FIG5 , an isolation layer 202 is further formed between the second semiconductor substrate 201 and the patterned dielectric layer 203, and the cavity structure 203a exposes the isolation layer 202. The isolation layer 202 can be used to isolate the cavity structure 203a from the second semiconductor substrate 201, so as to facilitate the adjustment of device performance based on the structural layer. The isolation layer 202 can be a layer of SiO ₂ , silicon nitride, silicon oxynitride, or aluminum oxide, or a combination of two or more of the above material layers. Of course, it can also be other insulating sacrificial dielectric layers, but is not limited thereto. In one example, the material of the isolation layer 202 is different from that of the patterned dielectric layer 203, so as to facilitate the preparation of the patterned dielectric layer 203 and to improve the device performance based on the isolation layer 202. The isolation layer and the patterned dielectric layer support layer can be the same material or different materials. When they are different materials, there is a certain selective etching ratio between the two structural layers, which is convenient for defining the device structure in the subsequent device preparation process.

As an example, as shown in FIG7 , the cavity structure 203a in the patterned dielectric layer 203 also extends to the material layer below the patterned dielectric layer 203, and the extension of the cavity structure 203a can be achieved by controlling the etching conditions when the cavity structure 203a is formed. For example, the cavity structure 203a also extends to the second semiconductor substrate 201, so as to facilitate adjusting the size of the cavity structure according to the device performance requirements. Of course, when the isolation layer 202 is also present, the cavity structure 203 can also extend through the isolation layer 202 to the second semiconductor substrate 201. In one example, the second semiconductor substrate layer 201 of the second substrate 200 serves as the bottom silicon of the SON structure formed subsequently, the patterned dielectric layer 203 serves as the intermediate insulating layer, and the first semiconductor substrate layer 101 in the first substrate 100 in this embodiment serves as the material layer for forming the top silicon. In this example, the cavity structure 203a extends to the bottom silicon of the SON.

Next, as shown in S2 in FIG. 1 and FIGS. 3-4 and 22, step S2 is performed to perform ion implantation on the first substrate 100 to form a preset peeling layer 101a in the first substrate 100, and a preset distance is provided between the preset peeling layer 101a and the cavity structure to be formed (such as the cavity structure 203a), as shown in d in FIG. 8. The preset distance d in the present invention is set according to the cavity structure 203a, and the setting method is that the preset distance d is greater than 1/8 of the cavity characteristic size D of the cavity structure 203a. In another optional example, the preset distance is set between 2nm-10μm, which can be less than 1.8μm, and can be selected as: 5nm, 10nm, 50nm, 1μm, 5μm, 8μm, which is conducive to obtaining a uniform material layer surface. In this step, the preset peeling layer 101a for subsequent substrate peeling is formed by ion implantation. The position of the preset peeling layer 101a is set according to the cavity structure 203a to be formed, which can be beneficial to protect the material layer above the cavity structure 203a in the subsequent process, and avoid the material layer above the cavity from being damaged, for example, during the grinding process. Ensure that the material layer above the cavity has a probability of nearly 100% not being damaged. Simplify the process and save costs. In addition, the preset peeling layer 101a can of course be set with reference to the actual required thickness. For example, when the required subsequent thickness is less than 1/8 of the cavity characteristic size D of the cavity structure 203a, it can also be achieved based on the subsequent thinning process.

In this embodiment, the preset distance d is greater than 1/8 of the cavity characteristic size D of the cavity structure 203a, wherein the cavity characteristic size D may be defined as follows: in a two-dimensional plane above the cavity (i.e., the cavity structure 203), the two-dimensional plane may be a two-dimensional plane where the top opening of the cavity structure 203a is located. Since the cavity is a closed structure, for any point A above the cavity, any straight line is drawn through the point, and the straight line has more than two contact points with the edge of the cavity. The two points A' and A", which are adjacent to point A in two directions extending from the straight line of point A, are the first contact point and the second contact point. As shown in FIG. 22, the distance between points A' and A", is a section of the cavity size. By changing the direction of the straight line through point A, the smallest section of the cavity size can be found. For all points above the cavity, there is a corresponding minimum cavity size. Among all the minimum cavity sizes, the largest size is selected and defined as the cavity characteristic size. For example, as shown in FIG. 22, for the cavity structure having a rectangular shape in the top view, the size of its cavity characteristic size D is the length of the short side of the rectangle.

As an example, the step of performing the ion implantation to form the preset peeling layer 101a includes: performing a first ion implantation on the first substrate 100 to form an initial peeling layer (not shown in the figure) in the first substrate 100, wherein the implanted particles of the first ion implantation include B-containing impurities; performing a second ion implantation at the position of the initial peeling layer to form the preset peeling layer 101a, wherein the implanted particles of the second ion implantation include at least one of H ions and He ions. In the above manner, in the process of defining the peeling interface, B+, BF2 and other ions are pre-implanted at the peeling interface, so that a clear distribution profile of the implanted particles can be defined at a lower dose, and the subsequent ion implantation dose can be reduced. The implanted ions of the second ion implantation are enriched at the first implanted particles, thereby accurately defining the peeling interface, reducing peeling damage, and reducing the peeling surface roughness. In one example, the implantation dose of the first ion implantation is less than the implantation dose of the second ion implantation. Optionally, the implantation dose of the first ion implantation is between 1e ¹¹ and 1e ¹³ /cm ² , such as 1e ¹² /cm ² ; based on the first particle implantation, the second ion implantation is performed, that is, hydrogen ions are then implanted with an implantation dose of 1e ¹⁶ to 1e ¹⁷ /cm ² , such as 6e ¹⁶ /cm ^2. Of course, He ions or other ions can also be used, so that the hydrogen ions are enriched near the B+ ions, thereby accurately defining the peeling interface, reducing peeling damage, and reducing the peeling surface roughness.

As an example, as shown in FIG4 , in this example, before performing the ion implantation, the steps are also included: forming a sacrificial dielectric layer 102 on the surface of the first semiconductor substrate 101, performing the ion implantation from the side where the sacrificial dielectric layer 102 is formed, as shown in FIG2-3 , and removing the sacrificial dielectric layer 102 after completing the ion implantation, that is, using the first semiconductor substrate 101 after removing the sacrificial dielectric layer 102 for subsequent bonding.

As an example, the method for setting the ratio of the preset distance to the characteristic size of the cavity structure includes: defining the pressure on the upper surface of the cavity structure during the peeling process as p, defining the length of the cavity structure in the pointing plane as infinite, defining the worst case as the center position of the transfer substrate film layer above the cavity with only the patterned dielectric layer as support points on both sides, and obtaining the maximum stress Mmax∝pL2 and the maximum stress σmax∝qL2/h2 in the transfer substrate film layer, wherein h is the preset distance, and L is the characteristic size of the cavity structure, and based on the maximum stress that the transfer substrate film layer can withstand, the ratio of the preset distance to the characteristic size of the cavity structure is obtained by experimental design.

Specifically, as shown in Figures 30 and 31, during the intelligent stripping process, hydrogen bubbles peel the stripping layer from the original substrate. Due to the limited thickness of the stripping layer, it is subjected to the greatest stress. In the worst case, the area where the hydrogen bubbles exert pressure on the stripping layer covers the entire pressure above the cavity, which is p. When defining the characteristic size of the cavity, it is assumed that the stripping layer located at this size position is subjected to equal pressure from hydrogen bubbles everywhere, and the stripping layer is supported only by the buried oxide layers on the left and right sides. At this time, the stress condition of the stripping layer is the worst. Through simple stress analysis, it can be seen that the maximum internal stress is located at the center of the stripping layer. Assuming that the length of the cavity in the z direction (pointing inwardly) is long, when performing stress analysis on it, it can be approximated to be infinitely long, and the stripping layer is supported only by the buried oxide layers on the left and right sides. At this time, the stress borne by the stripping layer is the worst. Then the maximum stress of the peeling layer is Mmax∝pL ² , (∝ means proportional to), the maximum stress in the peeling layer is σmax∝pL ² /h ² , that is, σmax∝(L/h) ² , that is, the ratio of the cavity width L to the peeling layer thickness h defines the maximum stress borne by the peeling layer. Considering that the upper limit of the maximum stress that the peeling layer can withstand is a constant, it is determined by the material properties. The ratio of the cavity width L to the peeling layer thickness h when the peeling layer withstands the maximum stress upper limit can be found through experiments.

Next, as shown in S3 in FIG. 1 and FIGS. 8-9 , step S3 is performed to bond the side of the first substrate 100 subjected to the ion implantation to the second substrate 200 to obtain an initial bonding structure, wherein the initial bonding structure includes a patterned dielectric layer 203 having the cavity structure 203a, and a gap is provided between the patterned dielectric layer 203 and the preset peeling layer 101a. The bonding method can be selected according to actual needs, such as direct bonding. The number and arrangement of the cavity structures 203a can be selected according to actual needs.

In this embodiment, the side of the first substrate 100 where the ion implantation is performed is bonded to the patterned dielectric layer 203 of the second substrate 200, wherein the spacing between the preset peeling layer 101a and the patterned dielectric layer 203 means that, in the plane where the patterned dielectric layer 203 and the preset peeling layer 101a are arranged, the patterned dielectric layer 203 has two opposite sides, one side is the side close to the preset peeling layer 101a, and the other side is the side away from the preset peeling layer 101a, and the spacing refers to the distance between the side of the patterned dielectric layer 203 close to the preset peeling layer 101a and the preset peeling layer 101a. When the cavity structure 203a penetrates the patterned dielectric layer 203, this spacing is also the distance between the cavity structure 203 and the preset peeling layer 101a. In this embodiment, the spacing described here is equal to the preset distance d set in the previous step when the ion implantation is performed according to the cavity structure 203a.

As shown in FIG8 , during the bonding process, the surface of the first semiconductor substrate 101 after the sacrificial dielectric layer 102 is removed according to the scheme in FIG4 is bonded to the patterned dielectric layer 203 of the second base 200, thereby obtaining the closed cavity structure 203a, that is, obtaining the initial bonding structure of the semiconductor substrate with the cavity structure. In addition, as shown in FIG9 , the initial bonding structure after bonding with the first base 100 when the cavity structure 203a extends into the second semiconductor substrate 201 is further shown.

As an example, the cavity structure 203a also has a support structure 203b, the top surface of the support structure 203b is flush with the upper surface of the patterned dielectric layer 203, the support structure 203b is located in the cavity structure 203a or at least one end of the support structure 203b is in contact with the side wall of the cavity structure 203a. Optionally, the support structure 203b can be formed simultaneously when the cavity structure 203a is etched. The existence of the support structure 203b can obtain a larger cavity area in a certain area when the peeling interface has been determined. This scheme designs an island cavity with a semi-enclosed and fully enclosed structure to reduce the characteristic size of the cavity and avoid damage to the top silicon. Among them, the shape of the cavity structure 203a includes but is not limited to a triangle, a quadrilateral, a polygon, a circle, and other patterns with a closed boundary. The island-shaped support structure 203b can be connected or disconnected with the cavity around, and the shape of the island-shaped support structure is not limited, and can be a quadrilateral or a triangle. In addition, as shown in Figures 24(a) and (b) and 25(a) and (b), the morphology of the SON substrate using the cavity structure including the support structure is shown. Figures 24(a) and (b) show that at least one end of the support structure 203b is in contact with the side wall of the cavity structure 203a, and Figures 25(a) and (b) show that the support structure 203b is located in the cavity structure 203a. By using the cavity containing the patterned support structure, a SON substrate with a larger area and no top silicon damage can be prepared. By using the design of the present invention, a SON substrate containing a large area and high density closed cavity structure can be prepared, and the proportion of the cavity area to the total area of the substrate exceeds 12%, which is suitable for preparing integrated circuits.

In addition, in one example, the design of the support structure can be based on the following method: for any cavity structure, all points on the cavity plane can be used, for example, point 1, point 2, point 3, ... point n as an example; first find the minimum cavity size corresponding to each point, for example: size 1, size 2, size 3, ..., size n, where the definition of the cavity size can refer to the description of the characteristic size definition in the specification of the present invention; then, from 1 to n minimum cavity sizes, the maximum size D can be found, which is defined as the cavity characteristic size, which is consistent with the definition of the cavity characteristic size described above; then, suppose that among 1 to n points, there are m (m < n) points with the minimum cavity size equal to the cavity characteristic size D; finally, after adding a peninsula/island support structure to the cavity, the structure simultaneously reduces the minimum cavity sizes corresponding to the above m points, and the support structure can reduce the characteristic size of the cavity. In one example, for all support structures in the cavity structure, their projections on each side wall of the cavity structure cover the side wall, and there is no exposed side wall. Therefore, the characteristic size of the cavity structure is reduced based on the support structure.

Finally, as shown in S4 in Figure 1 and Figures 17-21, step S4 is performed to peel off the first substrate 100 along the preset peeling layer 101a, so that a portion of the first substrate 100 is transferred to the patterned dielectric layer 203 to form a transfer substrate film layer 104 on the patterned dielectric layer 203, and a semiconductor substrate with a cavity structure is obtained, as shown in Figure 17.

Specifically, the first substrate 100 can be peeled off from the position of the preset peeling layer 101a by heating annealing. For example, the initial bonding structure can be annealed at a temperature between 400°C and 700°C. Of course, other peeling methods well known in the art can also be used. At this time, due to the setting of the position of the preset peeling layer 101a in the present invention, the thickness of the transfer substrate film layer 104 is the preset distance d, and the thickness of the transfer substrate film layer 104 is greater than 1/8 of the cavity feature size of the cavity structure 203a.

As an example, after peeling off the first substrate along the preset peeling layer 101a, the method further includes: performing a reinforcement treatment on the semiconductor substrate with a cavity structure, wherein the reinforcement treatment includes heating the semiconductor substrate with a cavity structure, such as high-temperature heating treatment, for example, at 1000° C. to 1300° C. Of course, other reinforcement methods may also be used.

In a further optional example, the heating treatment is performed under a preset atmosphere, and the preset atmosphere includes an oxygen atmosphere, so as to oxidize the surface of the transfer substrate film layer 104 to form a surface oxide layer 105, as shown in FIG18, and the surface oxide layer 105 is removed after the heating treatment, as shown in FIG19, so as to thin the transfer substrate film layer 104. In this way, the transfer substrate film layer 104 can be thinned by oxidation during the process of reinforcing the composite substrate structure of the semiconductor substrate with a cavity structure. In one example, the surface oxide layer 105 is etched with hydrofluoric acid to thin the transfer substrate film layer 104.

As an example, after obtaining the semiconductor substrate with a cavity structure, the following steps are further included: thinning the transfer substrate film layer 104, wherein the thinning process includes first mechanical thinning by chemical mechanical polishing process and second thinning by oxidation thinning process, to obtain the thinned structure 106. That is, the transfer substrate film layer 104 is thinned by two-step thinning, wherein the first step of thinning can be rough polishing, for example, it can be performed by CPM, and the time for the first thinning can be selected based on actual experience. Then, on this basis, the second thinning is performed, and an oxidation thinning process can be used, that is, the surface of the transfer substrate film layer after the first thinning is oxidized to form an oxide layer, and then the oxide layer is removed to further achieve thinning, so as to accurately define the thickness of the transfer substrate film layer remaining after thinning.

In one example, it is preferred that the first thinning and the second thinning processes in this example are performed after the heating curing treatment in the oxygen atmosphere and the removal of the surface oxide layer 105 in the above example are completed to obtain the thinned structure 106, as shown in Figure 20. After the oxidation thinning in the above example is completed, that is, after the surface oxide layer 105 is removed, the thickness of the transfer substrate film layer 107 (such as the top silicon) is reduced, and the pressure that the transfer substrate film layer above the cavity structure 203a can withstand is reduced. At this time, if the CMP process is used to further thin and polish the transfer substrate film layer, it is easy to cause damage to the top silicon. Therefore, in this example, CMP can be used for rough thinning first and then the oxidation thinning process can be used to continue secondary oxidation thinning, which is conducive to accurately defining the thickness.

As an example, after the thinning process is performed, the step of repairing the surface after the thinning process is also included, so that the surface after the thinning process is flat at the atomic level, and the cavity upper film layer 107 is obtained, as shown in FIG21. In one example, the repair process includes annealing the semiconductor substrate with the cavity structure in a hydrogen atmosphere, and the annealing temperature is between 800°C and 1300°C, for example, it can be 1000°C. In addition, FIG23 shows the semiconductor substrate structure (SON substrate) obtained after the above steps of this embodiment, and the cavity upper film layer 107 with excellent performance and almost no damage can be obtained. The second semiconductor substrate 201 is used as the bottom silicon layer, the patterned dielectric layer 203 is used as the middle buried oxide layer in the SON, the cavity structure 203a is used as the substrate cavity, and the cavity upper film layer 107 is used as the top silicon layer.

To further illustrate the effect of the present invention, see Figures 27-28. Figure 27 shows that when the top silicon peeling thickness (top silicon thickness is 1 μm) is less than or equal to 1/8 of the cavity feature size, the top silicon above the cavity is damaged to varying degrees; as shown in the experiment in Figure 27, the top silicon thickness is 1 μm, and when the cavity feature size is 8 μm, the top silicon is damaged. As shown in Figure 27, the top silicon thickness should be at least greater than 1/8 of the cavity feature size to ensure the integrity of the top silicon. Of course, other thickness values of the top silicon such as 2 μm, 3 μm, 5 μm, etc. can be further selected to ensure the integrity of the top silicon when other thicknesses are obtained. Figure 28 shows the damage of the top silicon above the cavity structure in the semiconductor substrate with a cavity structure formed by the formation method of the preset peeling layer of the present invention. It can be seen that the top silicon above the cavity structure of the present invention is basically not damaged. Figure 29 shows a SON substrate containing a large-area, high-density closed cavity structure prepared by the present invention. In the figure, the top silicon is translucent and contains a 0.5 μm*3 μm cavity below. By adopting the patented optimization technology (setting the initial peeling thickness by feature size), a SON substrate with a large-area cavity and 100% undamaged top silicon can be prepared, which can be used in high-density integrated circuits. By adopting the design of the present invention, a SON substrate with a large-area, high-density closed cavity structure can be prepared, and the cavity area accounts for more than 12% of the total substrate area, which is suitable for preparing integrated circuits.

Embodiment 2:

This embodiment 2 provides another method for preparing a semiconductor substrate with a cavity structure. The difference between this embodiment 2 and embodiment 1 is that the process of forming the initial bonding structure is different, see Figures 2, 3, 10-16 for details. In this embodiment 2: the first base 100 includes a first semiconductor substrate 101 and the patterned dielectric layer 103 formed on the first semiconductor substrate 101, as shown in Figure 10, and the preset peeling layer 101a is formed in the first semiconductor substrate 101.

Among them, the formation process of the patterned dielectric layer 103 is: the sacrificial dielectric layer 102 is formed on the first semiconductor substrate 101, and then the ion implantation is performed from the side where the sacrificial dielectric layer is formed to form the preset stripping layer 101a, and the sacrificial dielectric layer 102 is patterned to obtain the patterned dielectric layer 103, and the patterned dielectric layer 103 has the cavity structure 103a, see Figures 2, 3 and 10.

In one example, the cavity structure 103a extends into the material layer below the patterned dielectric layer 103 and into the first semiconductor substrate 101, as shown in FIG11. When the cavity structure 103a needs to extend into the first semiconductor substrate 101, the preset distance d, i.e., the distance between the bottom of the cavity structure 103a extending into the first semiconductor substrate 101 and the preset peeling layer 101a, is set according to the method in Example 1 during ion implantation, and is defined by the energy of the implanted ions, etc. In one example, after bonding to obtain an initial bonding structure, the first substrate 100 serves as the top silicon of the SON substrate, i.e., the cavity structure 103a extends into the top silicon.

In addition, in this embodiment 2, the second substrate 200 includes a second semiconductor substrate 201, as shown in FIG13, wherein the patterned dielectric layer 103 of the first substrate 100 is bonded to the second substrate 200. In an optional example, the second substrate 200 also includes an isolation layer 202 formed on the second semiconductor substrate 201, as shown in FIG12, the isolation layer 202 is bonded to the patterned dielectric layer 103 of the first substrate 100, and the cavity structure 103a in the patterned dielectric layer 103 exposes the isolation layer 202, so as to facilitate the isolation of the device cavity.

In this embodiment 2, the initial bonding structure obtained by bonding the first substrate and the second substrate is shown in three examples of Figures 14-16. Among them, Figure 14 shows that in the initial bonding structure, the second substrate 200 has an isolation layer 202; Figure 15 shows that in the initial bonding structure, the cavity structure 103a in the patterned dielectric layer 103 of the first substrate 100 extends into the first semiconductor substrate 101, and the second substrate 200 has an isolation layer 202; Figure 16 shows that in the initial bonding structure, the cavity structure 103a in the patterned dielectric layer 103 of the first substrate 100 extends into the first semiconductor substrate 101, and the second substrate 200 does not have an isolation layer 202. Of course, other initial bonding structures can also be formed according to the description of the first substrate and the second substrate.

Embodiment 3:

As shown in Figures 17 and 23, referring to Figures 1-16, this embodiment 3 provides a semiconductor substrate structure with a cavity structure, wherein the semiconductor substrate with a cavity structure is preferably prepared by the method for preparing a semiconductor substrate with a cavity structure provided in Embodiment 1 or Embodiment 2 of the present invention, and of course, it can also be prepared by other methods. The features of each structural layer in the semiconductor substrate with a cavity structure in this embodiment can be referred to the description in Embodiment 1 and Embodiment 2, and will not be repeated here.

The semiconductor substrate structure comprises: a first substrate 100, comprising a cavity upper film layer 107, wherein the cavity upper film layer 107 is obtained by peeling off the first semiconductor substrate 101 and further thinning the transferred substrate film layer 104; and a second substrate 200, bonded to the first substrate 100, wherein the second substrate 200 comprises a second semiconductor substrate 201; the semiconductor substrate further comprises a patterned dielectric layer 203 or 103 having a cavity structure 203a or 103a, wherein the patterned dielectric layer 203 or 103 is formed on the second semiconductor substrate 2 01 and the cavity upper film layer 107, wherein the transfer substrate film layer 104 has a first surface close to the cavity structure 203a or 103a and a second surface opposite to the first surface, and the distance between the second surface and the cavity structure 203a or 103a is greater than 1/8 of the cavity feature size. Here, the surface of the transfer substrate film layer 104 close to the patterned dielectric layer is the surface of the cavity upper film layer 107 close to the patterned dielectric layer, and the upper surface of the cavity upper film layer 107 is obtained by thinning the second surface. In another example, the distance between the second surface and the cavity structure 203a or 103a is less than 2μm. In this embodiment 3, the first substrate 100 and the second substrate 200 are described in accordance with the same description as in embodiment 1 and embodiment 2, and the patterned dielectric layer 203 or 103 is described separately from embodiment 1 and embodiment 2, and is described independently of the first substrate 100 and the second substrate 200, which can be understood by those skilled in the art.

As an example, the cavity structure 203a or 103a has a support structure 300, the top surface of the support structure 300 is flush with the upper surface of the patterned dielectric layer 203 or 103, the support structure 300 is located in the cavity structure 203a or 103a, or at least one end of the support structure 300 is in contact with the side wall of the cavity structure 203. The cavity structure is designed as a cavity structure with a support structure, that is, a semi-enclosed or fully-enclosed island cavity is formed. When the stripping interface has been determined, a larger cavity area can be obtained in a certain area. The island cavity with a semi-enclosed or fully-enclosed structure can reduce the characteristic size of the cavity and avoid damage to the top silicon.

As an example, an isolation layer 202 is further formed between the second semiconductor substrate 200 and the patterned dielectric layer 203 or 103 , and the cavity structure 203 a or 103 a exposes the isolation layer 202 .

As an example, the cavity structure 203 a or 103 a penetrates the patterned dielectric layer 203 or 103 and extends into at least one of the second semiconductor substrate 201 and the transfer substrate film layer 107 .

In summary, in the semiconductor substrate with a cavity structure and the preparation method thereof of the present invention, a preset peeling layer is prefabricated according to the cavity structure to be formed when ion implantation is performed to form a peeling interface, and the preset distance between the preset peeling layer and the cavity structure to be formed is greater than 1/8 of the cavity characteristic size of the cavity structure, thereby ensuring that the material layer above the cavity structure is not damaged during the process of preparing the semiconductor substrate with a cavity structure, thereby improving the device yield and performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims (19)

1. A method for preparing a semiconductor substrate having a cavity structure, characterized in that the preparation method comprises the steps of: Providing a first substrate and a second substrate; Performing ion implantation on the first substrate to form a preset peeling layer in the first substrate, wherein a preset distance exists between the preset peeling layer and the cavity structure to be formed, and the preset distance is set according to the cavity structure, wherein the setting method includes that the preset distance is greater than 1/8 of the cavity characteristic size of the cavity structure; The method for defining the characteristic size of the cavity includes: defining a two-dimensional plane above the cavity structure and parallel to the surface of the cavity structure; in the two-dimensional plane, there are a plurality of selected points above the cavity structure; for each of the selected points, there are a plurality of straight lines passing through the selected point; each of the straight lines has at least two contact points with the edge of the cavity structure, a first contact point and a second contact point are selected that are adjacent to the selected point in two directions of extension of the straight line passing through the selected point, and the distance between the first contact point and the second contact point is defined as the cavity size; the minimum cavity size is obtained based on the plurality of straight lines passing through each of the selected points; based on the plurality of selected points above the cavity structure, the maximum value of all the cavity sizes is selected to obtain the characteristic size of the cavity; bonding the side of the first substrate subjected to the ion implantation and the second substrate to obtain an initial bonding structure, the initial bonding structure comprising a patterned dielectric layer having the cavity structure, and a spacing between the patterned dielectric layer and the preset peeling layer; and The first substrate is peeled off along the preset peeling layer, so that a portion of the first substrate is transferred to the patterned dielectric layer to form a transfer substrate film layer on the patterned dielectric layer, thereby obtaining a semiconductor substrate with a cavity structure. 2. The method for preparing a semiconductor substrate with a cavity structure according to claim 1 is characterized in that the first base includes a first semiconductor substrate, the preset peeling layer is formed in the first semiconductor substrate, the second base includes a second semiconductor substrate and the patterned dielectric layer formed on the second semiconductor substrate, wherein the side of the first substrate where the ion implantation is performed is bonded to the patterned dielectric layer of the second substrate. 3. The method for preparing a semiconductor substrate with a cavity structure according to claim 2 is characterized in that before performing the ion implantation, it also includes the steps of: forming a sacrificial dielectric layer on the surface of the first semiconductor substrate, performing the ion implantation from the side where the sacrificial dielectric layer is formed, and removing the sacrificial dielectric layer after completing the ion implantation. 4 . The method for preparing a semiconductor substrate with a cavity structure according to claim 2 , wherein an isolation layer is formed between the second semiconductor substrate and the patterned dielectric layer, and the cavity structure exposes the isolation layer. 5. The method for preparing a semiconductor substrate with a cavity structure according to claim 1 is characterized in that the first substrate includes a first semiconductor substrate and the patterned dielectric layer formed on the first semiconductor substrate, the preset peeling layer is formed in the first semiconductor substrate, and the second substrate includes a second semiconductor substrate, wherein the patterned dielectric layer of the first substrate is bonded to the second substrate. 6. The method for preparing a semiconductor substrate with a cavity structure according to claim 5 is characterized in that the step of forming the first base comprises: providing the first semiconductor substrate; forming a sacrificial dielectric layer on the first semiconductor substrate; performing the ion implantation on the first semiconductor substrate from the side where the sacrificial dielectric layer is formed; and patterning the sacrificial dielectric layer to obtain the patterned dielectric layer with the cavity structure. 7. The method for preparing a semiconductor substrate with a cavity structure according to claim 5 is characterized in that the second substrate also includes an isolation layer formed on the second semiconductor substrate, the isolation layer is bonded to the patterned dielectric layer of the first substrate, and the cavity structure in the patterned dielectric layer exposes the isolation layer. 8. The method for preparing a semiconductor substrate with a cavity structure according to claim 1 is characterized in that the step of performing the ion implantation to form the preset stripping layer comprises: performing a first ion implantation on the first substrate to form an initial stripping layer in the first substrate; performing a second ion implantation at the position of the initial stripping layer to form the preset stripping layer, wherein the implanted particles of the first ion implantation include B-containing impurities, and the implanted particles of the second ion implantation include at least one of H ions and He ions. 9. The method for preparing a semiconductor substrate with a cavity structure according to claim 8 is characterized in that the implantation dose of the first ion implantation is less than the implantation dose of the second ion implantation; wherein the implantation dose of the first ion implantation is between 1e11 and 1e13/ ^cm2 , and the implantation dose of the second ion implantation is between 1e16 and 1e17/ ^cm2 . 10. The method for preparing a semiconductor substrate with a cavity structure according to claim 1 is characterized in that after peeling off the first base along the preset peeling layer, it also includes the step of: reinforcing the semiconductor substrate with a cavity structure, and the reinforcement treatment includes heating the semiconductor substrate with a cavity structure. 11. The method for preparing a semiconductor substrate with a cavity structure according to claim 10 is characterized in that the heat treatment is carried out under a preset atmosphere, and the preset atmosphere includes an oxygen atmosphere to form a surface oxide layer on the surface of the transfer substrate film layer, and after completing the heat treatment, the surface oxide layer is removed to thin the transfer substrate film layer. 12 . The method for preparing a semiconductor substrate with a cavity structure according to claim 1 , wherein the cavity structure in the patterned dielectric layer also extends into a material layer below the patterned dielectric layer. 13 . The method for preparing a semiconductor substrate with a cavity structure according to claim 1 , wherein the preset distance between the preset peeling layer and the cavity structure is between 2 nm and 10 μm. 14. The method for preparing a semiconductor substrate with a cavity structure according to claim 1 is characterized in that the setting method of the ratio of the preset distance to the characteristic size of the cavity structure includes: defining the pressure on the upper surface of the cavity structure during the peeling process as p, defining the length of the cavity structure in the pointing plane as infinite, defining the worst case as the center position of the transfer substrate film layer above the cavity with only the patterned dielectric layer as support points on both sides, and obtaining the maximum stress Mmax∝pL2 and the maximum stress σmax∝qL2/h2 in the transfer substrate film layer, wherein h is the preset distance, L is the characteristic size of the cavity structure, and based on the maximum stress that the transfer substrate film layer can withstand, the ratio of the preset distance to the characteristic size of the cavity structure is obtained by experimental design. 15. The method for preparing a semiconductor substrate with a cavity structure according to any one of claims 1 to 14, characterized in that after obtaining the semiconductor substrate with a cavity structure, it also includes the step of: thinning the transfer substrate film layer structure, the thinning treatment including a first thinning by chemical mechanical polishing and a second thinning by oxidation thinning. 16. The method for preparing a semiconductor substrate with a cavity structure according to claim 15 is characterized in that after the thinning treatment, it also includes the step of: repairing the surface after the thinning treatment to make the surface after the thinning treatment atomic-level flat, and the repair treatment process includes annealing the semiconductor substrate with a cavity structure after the thinning treatment in a hydrogen atmosphere, and the annealing temperature is between 800°C and 1300°C. 17. A semiconductor substrate structure with a cavity structure, characterized in that the semiconductor substrate structure comprises: The first substrate comprises a cavity upper film layer, wherein the cavity upper film layer is obtained by thinning the transfer substrate film layer; A second substrate bonded to the first substrate, wherein the second substrate comprises a second semiconductor substrate; A patterned dielectric layer having a cavity structure is formed between the second semiconductor substrate and the cavity upper film layer, the transfer substrate film layer having a first surface close to the cavity structure and a second surface opposite to the first surface, and a distance between the second surface and the cavity structure is greater than 1/8 of a cavity feature size of the cavity structure; Among them, the definition method of the cavity characteristic size includes: defining a two-dimensional plane above the cavity structure and parallel to the surface of the cavity structure; in the two-dimensional plane, there are several selected points above the cavity structure; for each of the selected points, there are several straight lines passing through the selected point; each of the straight lines has at least two contact points with the edge of the cavity structure, and a first contact point and a second contact point that are adjacent to the selected point in two directions of extension of the straight line passing through the selected point are selected, and the distance between the first contact point and the second contact point is defined as the cavity size; based on the several straight lines passing through each of the selected points, the minimum cavity size is obtained; based on the several selected points above the cavity structure, the maximum value of all the cavity sizes is selected to obtain the cavity characteristic size. 18 . The semiconductor substrate with a cavity structure according to claim 17 , wherein an isolation layer is formed between the second semiconductor substrate and the patterned dielectric layer, and the cavity structure exposes the isolation layer. 19. The semiconductor substrate with a cavity structure according to any one of claims 17-18, characterized in that the cavity structure penetrates the patterned dielectric layer and the cavity structure also extends into at least one of the second semiconductor substrate and the transfer substrate film layer.