CN102201405B - Imaging-based silicon-on-insulator-electro-static discharge (SOI-ESD) protective device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a pattern-based SOI-ESD protection device and a manufacturing method thereof. The ESD device structure includes: an underlying substrate; an insulating buried layer on the underlying substrate; an active region located on the insulating buried layer; and connecting the active region and the underlying layer through the insulating buried layer A conduction plug of the substrate; wherein, the active region includes a P well region and an N well region, and a lateral PN junction is formed between the P well region and the N well region; the conduction plug is located at the PN junction Below; a field oxygen region is set above the PN junction; a cathode contact terminal is set above the P well region; an anode contact terminal is set above the N well region. This device opens a window on the buried oxide layer. On the one hand, this window can well release the heat generated by ESD high current, and on the other hand, it can well improve the anti-ESD ability of the device. It can realize the anti-ESD voltage above 2KV in the HBM (Human Body Model), reaching the current industrial standard of the Human Body Model.

Description

A pattern-based SOI-ESD protection device and its manufacturing method

technical field

The invention relates to a semiconductor device, in particular to a pattern-based silicon-on-insulator (SOI) ESD protection device and a manufacturing method thereof, belonging to the technical field of semiconductor manufacturing.

Background technique

Silicon-on-insulator (SOI) is the silicon integrated circuit technology of the twenty-first century. The SOI material market expands about 40% every year, and it is expected that by 2010, its size will exceed 1 billion US dollars, far higher than the annual growth rate of 7.7% for silicon materials. The large-scale commercial use of SOI began in the late 1990s. In 1998, IBM used SOI technology to achieve breakthroughs in high-speed, low-power, high-reliability mainstream microelectronic products. IBM carried out large-scale production of SOI logic devices in 1999, and reached the yield of bulk silicon devices. In 2002, IBM launched the new 5AS/400 server series with SOI technology, which is almost 4 times faster than the current high-end models. In addition, IBM announced the largest investment in its history in October 2000, spending $5 billion on large-scale production of advanced chip technologies, one of which is SOI technology. With the success of IBM, other companies have followed suit. From 2001 to 2002, several companies leading the development of semiconductors in the world, such as AMD, SONY, TOSHIBA, etc., also entered the SOI field, making the future SOI market more optimistic. SOI Technology really enters the industrial field.

In China, the Institute of Microelectronics of the Chinese Academy of Sciences, the Shanghai Institute of Microsystems of the Chinese Academy of Sciences, the Institute of Semiconductors of the Chinese Academy of Sciences, Peking University, Chengdu University of Electronic Science and Technology, the 58th Institute of China Electronics Technology Group Corporation, and the Aerospace Times are working on the development of SOI devices and circuits in China. Group No. 771 Research Institute, Wuxi China Resources Shanghua Semiconductor Co., Ltd., etc. The development of SOI integrated circuit technology with independent intellectual property rights will help shorten the gap between the domestic integrated circuit industry and the international level, and promote the localization of chip core technology.

For SOI circuits, electrostatic discharge (ESD) protection faces new challenges. First of all, the difference in structure between SOI devices and bulk silicon devices leads to great differences in ESD protection capability and protection circuit design: due to the limitation of thin silicon film thickness and the absence of substrate/drain PN junction, the same surface The area of the PN junction of the SOI device is much smaller than that of the bulk silicon device. In this way, the drain-body junction of the SOI MOSFET and the cb junction of the triode will withstand a higher ESD current density during the ESD process, making the power density higher and easier to damage during the ESD process; secondly, due to the SiO of the SOl buried oxide layer The thermal conductivity of ₂ is only 1/100 of that of Si, and the devices are completely isolated by SiO ₂ . When an ampere-level current flows through the ESD device, the device will be rapidly heated to the melting point of the silicon crystal, resulting in a permanent SOI-based ESD device. Thermal failure.

In view of this, we intend to carry out research on SOI ESD protection devices, especially for the design and optimization of the structure and process of SOI ESD protection devices. Compared with bulk silicon technology ESD protection devices, SOI ESD has its particularity and difficulties, mainly because the existence of _SiO2 insulating layer in SOI technology not only reduces the heat dissipation capability of the device, but also blocks the formation of vertical pn junction, This leads to an increase in the local unloading current density, making the device more susceptible to thermal failure. Therefore, SOI ESD device structure design and process design are different from bulk silicon technology.

Under the impetus of the national VLSI project, the domestic development of SOI technology is in a stage of vigorous development. However, most domestic semiconductor process lines still use bulk silicon ESD protection technology. The root cause is the lack of SOI ESD protection solutions with independent intellectual property rights. Therefore, research on ESD protection devices based on SOI technology is imminent and imperative. The research results will provide a theoretical and practical basis for domestic SOI ESD protection circuit design.

Contents of the invention

The technical problem to be solved in the present invention is to provide a pattern-based SOI ESD protection device and a manufacturing method thereof, which can effectively improve the anti-ESD capability of the SOI circuit.

In order to solve the above technical problems, the present invention adopts the following technical solutions:

A pattern-based SOI ESD protection device comprising:

underlying substrate;

an insulating buried layer on the underlying substrate;

an active region on the insulating buried layer;

and a via plug connecting the active region and the underlying substrate through the insulating buried layer;

Wherein, the active region includes a P well region and an N well region, and a lateral PN junction is formed between the P well region and the N well region; the conduction plug is located below the PN junction; A field oxygen region is arranged on it; a cathode contact terminal is arranged on the P well region; an anode contact terminal is arranged on the N well region.

Preferably, the cathode contact terminal includes a first N+ region and a first P+ region located on the P well region, and a first isolation structure is provided between the first N+ region and the first P+ region to isolate them. open.

Preferably, the anode contact end includes a second N+ region and a second P+ region located on the N well region, and a second isolation structure is provided between the second N+ region and the second P+ region to isolate them. open.

Preferably, the field oxygen region has a thickness of 1.2-1.3 μm.

Preferably, the field oxygen region is a field oxide layer grown by thermal oxidation on the surface of the P well region and the N well region.

In addition, the present invention also provides a kind of fabrication method based on patterning SOI ESD protection device, comprises the following steps:

Step 1. Provide a piece of SOI substrate, the SOI substrate includes a first conductivity type underlying substrate, an insulating buried layer on the underlying substrate, and a top layer of silicon located on the insulating buried layer, and then etch Remove the top layer silicon of the SOI substrate, and open a window on the insulating buried layer of the SOI substrate, exposing part of the underlying substrate;

Step 2, epitaxial semiconductor material on the part of the underlying substrate exposed in the window, so that the epitaxial semiconductor material extends out of the window and covers the buried insulating layer, forming an epitaxial top layer of the first conductivity type;

Step 3: Form a well region of the second conductivity type on the epitaxial top layer of the first conductivity type through a doping process, so that a lateral gap is formed between the formed well region of the second conductivity type and the remaining epitaxial top layer of the first conductivity type. PN junction;

Step 4, forming a field oxygen region above the PN junction by thermal oxidation, and at the same time diffusing the formed well region of the second conductivity type to above the window, so that the PN junction is moved to a middle position above the window;

Step 5, making the second electrode contact end and the first electrode contact end on the well region of the second conductivity type and the epitaxial top layer of the first conductivity type respectively.

Preferably, the first conductivity type is P type and the second conductivity type is N type; or the first conductivity type is N type and the second conductivity type is P type. Wherein, the anode contact end is made in the N well region, and the cathode contact end is made in the P well region.

Preferably, in step 3, the first sacrificial layer is formed by oxidation on the surface of the epitaxial top layer of the first conductivity type, and the well implantation of the second conductivity type is performed on the epitaxial top layer of the first conductivity type by ion implantation, and the implantation is completed The first sacrificial layer on the rear surface is peeled off, and then annealed to form the well region of the second conductivity type. Step 3 The annealing temperature is 1000-1200 degrees Celsius; the annealing time is 50-70 minutes. The thickness of the first sacrificial layer is 25-35nm.

Preferably, in step 4, the surface of the well region of the second conductivity type and the epitaxial top layer of the first conductivity type is first oxidized to form an oxide layer, and then a mask is deposited on the oxide layer and the PN junction above the PN junction is etched away. part of the mask to expose part of the oxide layer, and then use thermal oxidation to continue to grow the exposed part of the oxide layer to form a field oxygen region, and at the same time diffuse the second conductivity type well region above the window to move the PN junction to the center above the above window. The thickness of the oxide layer is 25-35nm. The thermal oxidation temperature of the thermal oxidation method is 900-1100 degrees centigrade; the time is 380-390 minutes.

Preferably, in step five, first remove the mask remaining in step four, and then use ion implantation to perform N well implantation in the second conductivity type well region and the first conductivity type epitaxial top layer where the surface is not covered by the field oxygen region and P well implantation, and then perform annealing to form a first N+ region and a first P+ region in the epitaxial top layer of the first conductivity type, and form a second N+ region and a second P+ region in the second conductivity type well region; and then Making the first groove and the second groove, respectively separating the first N+ region and the first P+ region, and separating the second N+ region and the second P+ region, and separating the first and second grooves filled with insulating material. Connecting and leading out the first N+ region and the first P+ region with a wire can be used as a first electrode contact end, and connecting and leading out the second N+ region and the second P+ region can be used as a second electrode contact end. Wherein, when the first conductivity type is P type and the second conductivity type is N type, the first electrode contact end is the cathode contact end, and the second electrode contact end is the anode contact end; when the first conductivity type is N type, the second electrode contact end is the anode contact end; When the second conductivity type is P type, the first electrode contact end is an anode contact end, and the second electrode contact end is a cathode contact end. Step 5: The annealing temperature is 700-900 degrees Celsius; the annealing time is 35-45 minutes.

Preferably, in step five, the surface is oxidized to form a second sacrificial layer before N-well implantation and P-well implantation, and the thickness of the second sacrificial layer is 25-35 nm.

The beneficial effects of the present invention are:

One of the most critical problems in SOI ESD protection is that the heat generated when ESD high current flows cannot be released in time. The present invention can dissipate the generated heat in time without reducing the ESD resistance of the device. This device opens a window on the buried oxide layer. On the one hand, this window can well release the heat generated by ESD high current, and on the other hand, it can well improve the anti-ESD ability of the device. The trigger voltage and maintenance voltage of the device can be adjusted by adjusting the device parameters, so that it can be used for circuit protection of different internal voltages and avoid local concentration of power. It can realize the anti-ESD voltage above 2KV in the HBM (Human Body Model), reaching the current industrial standard of the Human Body Model.

Description of drawings

Fig. 1 is the structural representation based on patterned SOI ESD protection device in the embodiment;

2-6 are schematic diagrams of the manufacturing process of the ESD protection device in the embodiment.

Detailed ways

The graphic-based SOI ESD protection device and manufacturing method provided by the present invention are further described below in conjunction with the accompanying drawings, and the accompanying drawings are not drawn to scale for the convenience of illustration.

The graphic-based SOI ESD protection device provided in this embodiment, as shown in Figure 1, includes:

The underlying substrate 1, the insulating buried layer 2 (which may be a buried oxide layer BOX with a thickness of 3 μm) on the underlying substrate 1, the active region (usually 1.5 μm thick) located on the insulating buried layer 2, And a via plug 1 ′ connecting the active region and the underlying substrate 1 through the insulating buried layer 2 .

Wherein, the active region includes a P well region 5 and an N well region 4, and a lateral PN junction is formed between the P well region 5 and the N well region 4, that is, the interface between the P and N well regions and the plane where the substrate is located substantially vertical; the conduction plug 1' is located below the PN junction; a field oxygen region 3 is provided above the PN junction; a cathode contact terminal is provided above the P well region 5; An anode contact terminal is provided on the well region 4 .

The field oxygen region 3 is preferably a field oxide layer grown by thermal oxidation on the surface of the P well region 5 and the N well region 4, and its thickness is preferably 1.2-1.3 μm, which is 1.27 μm in this embodiment. The cathode contact terminal includes a first N+ region 9 and a first P+ region 10 located on the P well region 5, and a first isolation structure 61 is provided between the first N+ region 9 and the first P+ region 10 They are separated; the anode contact terminal includes a second N+ region 7 and a second P+ region 8 on the N well region 4, and a second N+ region 7 and a second P+ region 8 are provided between The second isolation structure 62 separates them.

The manufacturing method of the above SOI-based ESD protection device, as shown in Figure 2-6, includes the following steps:

Step 1. Provide a piece of SOI substrate, the SOI substrate includes a first conductivity type underlying substrate 11, an insulating buried layer 12 located on the underlying substrate 11, and a top silicon layer located on the insulating buried layer 12 , and then etch away the top layer silicon of the SOI substrate, and open windows on the insulating buried layer 12 of the SOI substrate by coating, photolithography, wet anisotropic etching and other processes to expose part of the underlying substrate Bottom 11, as shown in Figure 2. The first conductivity type here is relative to the second conductivity type, which can be P type or N type. When the first conductivity type is P type, the second conductivity type is N type. When the first conductivity type If it is N type, the second conductivity type is P type, and in this embodiment, the first conductivity type is P type.

Step 2, as shown in FIG. 3 , epitaxial semiconductor material on the part of the underlying substrate 11 exposed in the window, so that the epitaxial semiconductor material extends out of the window and covers the insulating buried layer 12 to form the first conductivity type (P-type) epitaxial top layer 13 . The thickness of the epitaxial top layer 13 covering the insulating buried layer 12 should reach 1.5 μm.

Step 3: Form a second conductivity type well region (N well region) 14 by a doping process on the P-type epitaxial top layer 13, so that the formed N well region 14 and the remaining part of the P-type epitaxial top layer 13 are doped. Lateral PN junction. Preferably, as shown in FIG. 4 , the first sacrificial layer 15 is formed on the surface of the P-type epitaxial top layer 13 by oxidation, and then ion implantation is used to form a layer on the P-type epitaxial top layer N-well implantation is performed on 13, and after the implantation is completed, the first sacrificial layer 15 on the surface is peeled off, and then annealing is performed to form the N-well region 14. Wherein, the high temperature annealing temperature is 1000-1200 degrees Celsius, preferably 1100 degrees Celsius in this embodiment; the annealing time is 50-70 minutes, preferably 60 minutes in this embodiment. The thickness of the first sacrificial layer 15 is 25-35 nm, preferably 30 nm in this embodiment.

Step 4, as shown in FIG. 5 , oxidize the surface of the N well region 14 and the P-type epitaxial top layer 13 to form an oxide layer, and then deposit a mask on the oxide layer, and the mask can pass through the surface isotropy It is formed by growing silicon nitride, and through processes such as glue coating and photolithography, etch away part of the mask located above the PN junction to expose part of the oxide layer, and then use thermal oxidation to continue to grow the exposed part of the oxide layer to form a field Oxygen region 16, and at the same time diffuse the formed N well region 14 above the window, move the PN junction to the middle position above the window, and remove the silicon nitride on the surface. The thickness of the oxide layer is 25-35nm, preferably 30nm in this embodiment. The thermal oxidation temperature is 900-1100 degrees Celsius, preferably 1000 degrees Celsius in this embodiment; the growth time is 380-390 minutes, preferably 385 minutes in this embodiment.

Step 5, as shown in FIG. 6 , make an anode contact terminal and a cathode contact terminal on the N well region 14 and the P-type epitaxial top layer 13 respectively.

Wherein, surface oxidation can be carried out to form a second sacrificial layer, i.e. silicon dioxide, the thickness of the second sacrificial layer is 25-35nm, the present embodiment is preferably 30nm; N-well implantation and P-well implantation are performed on the surface of the epitaxial top layer 13 not covered by the field oxygen region 16, followed by annealing at high temperature to push the well, thereby forming the first N+ region 17 and the first P+ in the P-type epitaxial top layer 13. region 18, forming a second N+ region 19 and a second P+ region 20 in the N well region 14; making the first trench and the second trench to separate the first N+ region 17 and the first P+ region 18 respectively , the second N+ region 19 and the second P+ region 20 are spaced apart, and the etching groove first needs to etch the silicon dioxide on the surface, and then etch away the silicon with a predetermined depth, and then in the first and second grooves Fill the insulating material, such as silicon dioxide, etc., and then remove the glue and clean to complete the fabrication of the first isolation structure 21 and the second isolation structure 22 .

Finally, wires can be used to connect and lead out the first N+ region 17 and the first P+ region 18 as a cathode contact end, and wires can be used to connect and lead out the second N+ region 19 and the second P+ region 20 as an anode contact end. When performing annealing and high-temperature push well, the annealing temperature is 700-900 degrees Celsius, preferably 800 degrees Celsius in this embodiment; the annealing time is 35-45 minutes, preferably 40 minutes in this embodiment.

The inventors of the present invention found that in the SOI circuit, due to the existence of the buried oxide layer, there is no vertical large-area low-resistance PN junction in the device, which greatly limits the leakage capacity of the device and easily causes an increase in local current density. Too fast, resulting in power concentration. The thermal conductivity of silicon dioxide is only 1% of that of silicon. Therefore, when the heat generated during the increase of ESD current cannot be dissipated in time, it will also cause premature failure or even burnout of the device. Therefore, aiming at this situation, the present invention proposes a patterned SOI technology, which can not only release the heat generated during the ESD process in time, but also greatly improve the anti-ESD capability of the device. The present invention is realized by opening a window of a suitable size at the corresponding position of the buried oxide layer. First, the top layer silicon is etched away, and then the position to be opened is exposed by steps such as glue coating and photolithography at the position where the window is to be opened, and then Carry out wet anisotropic etching, stay on the substrate silicon surface, then carry out P-type silicon growth, and stop when the top layer silicon reaches 1.5 μm. Then proceed to normal device fabrication. After N-well implantation, due to the growth of a thick oxide layer on the surface, the device needs to undergo a long-term high-temperature oxidation, so that the N-well concentration is fully diffused, occupying nearly half of the window, and after ESD comes, then As the voltage gradually increases, the PN junction formed by the N well and the P region in the window will undergo avalanche breakdown, and the generated ESD current will flow to the substrate, avoiding concentration inside the device, and will not cause local overheating. When the ESD voltage continues When rising, the PN junction formed by the N well and the P epitaxial layer will undergo avalanche breakdown. At this time, part of the current flows to the substrate and part of the current flows to the cathode, which greatly alleviates the current density concentration encountered in conventional SOI devices. At this time The heat generated inside the device can also be released through the substrate in time to avoid premature secondary breakdown.

Other technologies involved in the present invention belong to the category familiar to those skilled in the art, and will not be repeated here. The above embodiments are only used to illustrate but not limit the technical solution of the present invention. Any technical solutions that do not deviate from the spirit and scope of the present invention shall be included in the patent application scope of the present invention.

Claims (7)

1. one kind based on patterned SOI esd protection device, it is characterized in that, comprising:

At the bottom of the back lining;

Insulating buried layer on being positioned at the bottom of the described back lining;

Be positioned at the active area on the described insulating buried layer;

And pass conducting bolt at the bottom of described insulating buried layer connects described active area and back lining;

Wherein, described active area comprises P well region and N well region, forms horizontal PN junction between described P well region and the N well region; Described conducting bolt is positioned at described PN junction below; On described PN junction, be provided with an oxygen district; On described P well region, be provided with the negative electrode contact jaw; On described N well region, be provided with the anode contact jaw;

Described negative electrode contact jaw comprises a N+ district and a P+ district that is positioned on the described P well region, is provided with the first isolation structure between a described N+ district and a P+ district they are separated;

Described anode contact jaw comprises the 2nd N+ district and the 2nd P+ district that is positioned on the described N well region, is provided with the second isolation structure between described the 2nd N+ district and the 2nd P+ district they are separated.

2. described based on patterned SOI esd protection device according to claim 1, it is characterized in that: described oxygen district thickness is 1.2-1.3 μ m.

3. described based on patterned SOI esd protection device according to claim 1, it is characterized in that: the field oxide of described oxygen district for forming in described P well region and N well region Film by Thermal Oxidation.

4. one kind such as each described manufacture method based on patterned SOI esd protection device of claim 1-3, it is characterized in that, may further comprise the steps:

Step 1, provide a slice SOI substrate, insulating buried layer at the bottom of described SOI substrate comprises the back lining of the first conductivity type, on being positioned at the bottom of the described back lining and be positioned at top layer silicon on the insulating buried layer, then etch away the top layer silicon of described SOI substrate, and offer window at the insulating buried layer of described SOI substrate, at the bottom of the exposed portions serve back lining;

Epitaxial semiconductor material at the bottom of step 2, the part back lining that exposes in described window makes the semi-conducting material of extension extend described window and cover described insulating buried layer, forms the extension top layer of the first conductivity type;

Step 3, on the extension top layer of described the first conductivity type, form the second conductivity type well region by doping process, make between the extension top layer of the second conductivity type well region of formation and remaining the first conductivity type and form horizontal PN junction;

Step 4, above PN junction, adopt thermal oxidation method to form an oxygen district, make simultaneously the second conductivity type well region of formation diffuse to described window top, make PN junction move to the centre position of described window top;

Step 5, make the second electrode tips and the first electrode tips at the extension top layer of the second conductivity type well region and the first conductivity type respectively;

In described step 5, adopt the method for Implantation not carried out the injection of N trap and the injection of P trap by the position of field oxygen district covering surfaces at the extension top layer of the second conductivity type well region and the first conductivity type, then anneal, thereby in the extension top layer of the first conductivity type, form a N+ district and a P+ district, in the second conductivity type well region, form the 2nd N+ district and the 2nd P+ district; Make again the first groove and the second groove, make respectively between a N+ district and the P+ district to separate, separate between the 2nd N+ district and the 2nd P+ district, and in described the first and second grooves fill insulant.

5. described manufacture method based on patterned SOI esd protection device according to claim 4, it is characterized in that: described the first conductivity type is the P type, the second conductivity type is N-type; Perhaps described the first conductivity type is N-type, and the second conductivity type is the P type.

6. described manufacture method based on patterned SOI esd protection device according to claim 4, it is characterized in that: in the step 3, the first extension topsheet surface oxidation at the first conductivity type forms the first sacrifice layer, adopt the method for Implantation to carry out the injection of the second conductive type well at the extension top layer of described the first conductivity type, the first sacrifice layer that the rear surface is finished in injection peels off, and then anneals, thereby forms described the second conductivity type well region, wherein, annealing temperature is 1000-1200 degree centigrade; Annealing time is 50-70 minute, and the thickness of described the first sacrifice layer is 25-35nm.

7. described manufacture method based on patterned SOI esd protection device according to claim 4, it is characterized in that: in the step 4, elder generation carries out oxidation on the surface of the extension top layer of the second conductivity type well region and the first conductivity type and forms oxide layer, again in deposition mask on the described oxide layer and etch away the part mask that is positioned at above the PN junction, the described oxide layer of exposed portions serve, then the partial oxidation floor continued growth of adopting thermal oxidation method to make to expose forms an oxygen district, make simultaneously the second conductivity type well region diffuse to described window top, make PN junction move to the centre position of described window top; The thickness of described oxide layer is 25-35nm; The oxidate temperature of described thermal oxidation method is 900-1100 degree centigrade; Time is 380-390 minute.

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