CN1118875C - Memory unit and manufacture thereof - Google Patents

Abstract

A memory cell device includes transistors arranged three-dimensionally. The vertical MOS transistors are arranged here on the side walls of the semiconductor web, a plurality of transistors being arranged one above the other on each side wall. The transistors arranged one above the other on the side walls are connected in series.

Description

Memory cell device and manufacturing method thereof

Memory cells are used in a wide variety of process technologies. These memory units can involve both a read-only memory called ROM (Read Only Memory) and a programmable memory called PROM (Programmable ROM).

Various memory cell devices on semiconductor substrates are characterized in that they allow freely selective access to information stored therein. These memory cell devices contain a large number of transistors. During readout it is determined whether current is flowing or not flowing through a transistor. In this case, the respective logic state 1 or 0 is assigned to the current flow through the transistor or to the blocking of the transistor. Information is usually stored by using MOS (Metal Oxide Semiconductor) transistors whose channel regions have a doping corresponding to the desired blocking behavior.

In DE-OS 195 10 042 a memory cell arrangement with MOS transistors arranged in rows is proposed. These MOS transistors are connected in series in each row. To increase the storage density, adjacent rows are alternately arranged on the bottom of the strip-shaped longitudinal grooves and between adjacent strip-shaped longitudinal grooves on the substrate surface. The interconnected source/drain regions are formed as associated doped regions. The memory cell arrangement can be read out by a row-wise control.

This memory cell arrangement is characterized in that the area requirement required for the memory cell has been reduced from ^4F2 to ^2F2 , where F is the minimum structure width for the photolithographic process employed for fabrication. The disadvantage is that it is not possible to further increase the amount of memory per area unit.

US-RS 5 409 852 discloses the arrangement of MOS transistors one above the other to increase the storage density. Covering doped layers are used for contacting such transistors, which layers are correspondingly structured and connected by metal contacts.

The task of the present invention is to avoid these disadvantages of the state of the art. In particular, a memory cell arrangement should be created on which the largest possible number of memory cells can be arranged in the smallest possible space.

This object is achieved by a memory cell arrangement according to claim 1 and a method for its production according to claim 14 . Further developments of the invention arise from the remaining claims.

Straps protruding beyond the main surface of the semiconductor substrate are arranged on the main surface of the semiconductor substrate. The webs each have a doping layer, in which the layers adjacent to one another are each doped with the opposite conductivity type. Every three adjacent doped layers form two source/drain regions and one channel region of the field effect control transistor. At least one sidewall of the stack is each provided with a gate dielectric layer. Word lines each bounding against the gate dielectric layer within the stacked sidewalls extend across the tabs. These doped layers, which function as source/drain regions, simultaneously function as the bit lines of the memory cell device. In the memory, so many doped layers are arranged that at least two transistors arranged one above the other are realized by these doped layers, which are connected in series via a common doped layer which acts as a common source/drain region.

In this memory cell device, intersections between one of the word lines and a doped layer functioning as a channel region and two adjacent doped layers functioning as source/drain regions each define a transistor. Each adjacent transistor connected in series has a common source/drain region. The current in these transistors is distributed parallel to the sidewalls of the stack.

In particular, so many doped layers are arranged in the stack that 4 to 32 transistors are each arranged one above the other in the webs, each of which is doped jointly via a common source/drain region. layered in series. A high storage density is thereby achieved.

The webs have a strip-shaped cross section parallel to the main substrate surface. Adjacent webs are in particular arranged parallel to one another.

A plurality of word lines spaced apart from each other extend across each of the tabs. In this way a large number of transistors which are controllable via the respective word line are arranged side by side along the longitudinal dimension of the webs.

The present invention therefore contemplates creating a memory cell arrangement on which all three dimensions of space are utilized for storing and/or transferring information. This is achieved by arranging N number of transistors on top of each other. In this case, the required area requirement per memory is reduced from 4F ² to 4F ² /N. This reduction in area is achieved by three-dimensional integration in which N transistors are stacked on top of each other.

The reduction in area according to the invention is achieved by the stacking of the transistors shown. These other measures simplify the manufacturability of the memory cell arrangement and lead to a switching speed as high as possible. This therefore does not depend on a single feature of the features shown. These concepts are employed herein in their broadest sense.

Especially the term gate dielectric layer is by no means meant to be restrictive. The concept includes both a conventional dielectric layer and also dielectric layers with enhanced carrier-trapping cross-sections, such as those containing Si ₃ N ₄ , Ta ₂ O ₅ , Al ₂ O ₃ or TiO ₂ . However, it may also be a composite gate dielectric layer, for example with the structure of an ONO (oxide/nitride/oxide) sequence with a first _SiO2 layer , a Si ₃ N ₄ layer and a second SiO ₂ layer. It is thus possible to form both a memory cell arrangement which is programmable during the manufacturing process and a memory cell arrangement which is reprogrammable during its operation.

These transistors have different doping concentrations in the channel region, so that, according to a development of the invention, logic quantities 0 and 1 are stored. Each transistor having one of the logic values stored therein has a first dopant material concentration value in the channel region and each transistor having a second logic value stored therein has a dopant material concentration value different from the first dopant material concentration value Second dopant concentration value. These different dopant concentrations in the channel region result in different starting voltages of the transistor and thus allow the different logic values to be distinguished.

The individual concentrations of the individual dopants in the channel region differ from one another by a factor of 2 to 10, whereby a reliable readout of the stored information is achieved.

One of the dopant concentration values is reasonably in the range between 0.5×10 ¹⁸ cm ^-3 and 2×10 ¹⁸ cm ^-3 , while the other is between 0.5×10 ¹⁹ cm ^-3 and 2 ×10 ¹⁹ cm ^-3 range.

According to a further development of the invention the gate dielectric layer is realized from a material with charge carrier traps. In particular, the gate dielectric layer is formed from a multilayer system, on which one of the layers has an increased carrier-trapping cross section than the adjacent layers. Carriers trapped in the gate dielectric affect the transistor's onset voltage. In this development of memory cell arrangements, logical information is stored by a targeted supply of charge carriers.

According to a further development of the invention, the webs each contain two layers separated by an insulating region. Here too, the insulating region can be formed in the form of a strip and two strip-shaped stacks can be defined. In this development the transistors are implemented on opposite sidewalls of the tabs. In this way the storage density is further increased.

It is within the scope of the invention to connect in each case two stacks arranged in adjacent webs via a doped region arranged in the semiconductor substrate and bordering on the main surface. Furthermore, individual stacks contained in a web can be connected in series via a common conductive layer arranged above the stacks and the insulating region. Increase the number of levels by cascading each adjacent stack.

The memory cell arrangement according to the invention is not limited to a specific layout technique of its constituent parts. The spatial arrangement shown here is however particularly advantageous. The other circuit elements can have any desired arrangement, while the active regions of the transistors lie one above the other. The other components of each transistor may also be arranged differently. The gate dielectric layer is arranged perpendicularly to a main surface of the semiconductor substrate, however a particularly good space utilization can be achieved in this way. Such an arrangement can be rationally realized with the gate dielectric layer on one side wall of the tab.

The contacting of the bit lines which are arranged one above the other in each of the individual stacks can be realized in different ways. In particular, the stack can be structured in each case such that each of the bit lines is exposed at the edge of the cell group. In this case, at the edge of the cell group, the stack has a stepped cross-section in which the bit lines arranged farther down in the stack protrude laterally beyond the bit lines arranged above it.

Alternatively, it is within the scope of the invention to control the bit lines arranged one above the other via a decoder. In particular the decoder is implemented in a stack. For this purpose, other selection lines crossing the stack are arranged. At the intersection between one of the selection lines and the stack, one transistor of the decoder is thus implemented in each case. The construction of the transistors of the decoder is thus similar to the construction of the transistors in the memory cell group. Each of the decoder transistors is connected between two adjacent bit lines. As many decoder transistors are arranged on top of each other as transistors are arranged on top of each other in the memory cell group and are connected in series with each other. The respective different starting voltages of the individual decoder transistors are achieved by means of different dopant concentrations in the channel regions of the individual decoder transistors. When necessary, a plurality of decoders between which the respective transistors of the memory cell arrangement are arranged can be realized in one wafer. Excessive voltage drops across the bit lines are avoided in this way.

In order to produce the memory cell arrangement, doped layers are deposited on the main surface of the semiconductor substrate, in which case adjacent doped layers are each doped with the opposite conductivity type. The webs are formed by structuring the doped layers. At least one side wall of each tab is provided with a gate dielectric layer. Bit lines are formed extending across each tab and each bounded to the gate dielectric layer within the extent of the sidewalls of each tab.

These doped layers are applied in particular by epitaxy. Especially in situ doping for processing. If various information is to be realized in the form of different dopings in the channel region, the dopant concentration for the individual MOS transistors is adjusted by implantation after growth of the respective doped layer containing the channel region.

Further advantages, features and possible developments of the invention emerge from the subclaims and from the following representation of preferred embodiments with the figures.

1 is a side view of a cross section of a memory cell device shown in these figures, FIG. 2 is an enlarged cross section of the memory cell device shown in FIG. 1, and FIG. The circuit arrangement of the bit lines.

On the memory cell arrangement shown in FIG. 1, tabs 10, 20 forming two rows of memory cells are shown. The webs 10 and 20 are situated on a surface of a semiconductor substrate 30 which is preferably made of monocrystalline silicon. The semiconductor substrate 30 is doped with a dopant concentration p of approximately 10 ¹⁷ cm ⁻³ at least in the region of the unit groups. The n-doped regions 90 a are arranged in the semiconductor substrate 30 . These regions have a depth of approximately 200 nm and a dopant concentration of 4×19 ¹⁹ cm ⁻³ . Two n-doped regions 90 a are arranged below each web 10 , 20 .

Word lines 40 are arranged on these tabs 10 and 20 . The word lines 40 are made of an electrically conductive material, for example a highly doped semiconductor material, for example polysilicon. Word lines 40 made of silicon may additionally be silicided. However, it is also possible for the word lines 40 to consist of a metal. The word lines 40 run essentially parallel to the surface of the semiconductor substrate 30 and here perpendicular to the longitudinal dimensions of the respective webs 10 and 20 .

The exact configuration of the web 20 is shown in FIG. 2 . The tabs 10 and 20 each contain laminations 50 and 60 separated from each other by an insulating region 70 . This insulating region 70 has SiO ₂ . Each of these stacks 50 and 60 contains a plurality of layers arranged one above the other. One of the stacks 50 here contains layers 90 , 93 , 100 , 103 , 110 , 113 , 120 , 123 , 130 , 133 , 140 , 143 , 150 , 153 , 160 , 163 and 170 . Another stack 60 contains layers 90 , 95 , 100 , 105 , 110 , 115 , 120 , 125 , 130 , 135 , 140 , 145 , 150 , 155 , 160 , 165 and 170 . These layers 90 , 100 , 110 , 120 , 130 , 140 , 150 , 160 and 170 have as high an n-type doping as possible. Since these n-doped layers 90 , 100 , 110 , 120 , 130 , 140 , 150 , 160 and 170 are used as bit lines in the memory cell, they have as high a concentration of phosphorus-like dopant material as possible. In order to keep the series resistance as small as possible, the concentration of dopant material in each bit line is preferably greater than 5×10 ¹⁹ cm ⁻³ . These n-doped layers 90, 100, 110, 120, 130, 140, 150 and 160 have a thickness of 50 nm each, and the n-doped layer 170 has a thickness of 400 nm.

One of the stacks 50 has p-doped layers 93, 103, 113, 123, 133, 143 between n-doped layers 90, 100, 110, 120, 130, 140, 150, 160 and 170, 153 and 163, these P-doped layers have a thickness of 100 nm each. The individual layers 93, 113, 123 and 163 are here highly doped. The other individual p-doped layers 103 , 133 , 143 and 153 are in contrast lowly doped. The stack 60 likewise has individual layers 95 , 105 , 115 , 125 , 135 , 145 , 155 and 165 doped with a P-type dopant material, which layers each have a thickness of 100 nm. These layers 105, 135, 145 and 165 are highly doped here. The other p-doped layers 95 , 115 , 125 and 155 are in contrast lightly doped. This low doping is especially on the order of 1×10 ¹⁸ cm ⁻³ , and the higher doping is especially on the order of 1×10 ¹⁹ cm ⁻³ . This low and higher doping has different onset voltages and thus allows a distinction between stored logic states 0 or 1 . The doping of the bit lines doped with n-type dopant is in particular at least 4×10 ¹⁹ cm ⁻³ , preferably 1×10 ²⁰ cm ⁻³ or more. These bit lines have a specific resistance of about 2 mΩcm at a dopant concentration of 4×10 ¹⁹ cm ⁻³ .

Eight stacked and at the transistor. The stacked layers 90, 93, 100, 103, 110, 113, 120, 123, 130, 133, 140, 143, 150, 153, 160, 163, 170 of the stack 50 also form eight stacked layers. at the transistor. On the sides of these stacks 50 and 60 are located insulating regions 175 and 185 containing SiO ₂ in the edge regions of the respective webs 10 , 20 . These insulating layers 175 and 185 serve as gate dielectric layers for the respective transistors formed from the respective stacks 50 and 60 . Each insulating layer 175 and 185 serving as a gate dielectric layer has a thickness of about 10 nm.

In order to realize the programmability of each memory cell, the gate dielectric layer is desirably made of a material with an improved carrier trapping cross-section. This can be achieved, for example, by using suitable nitrides such as Si ₃ N ₄ or oxides such as Ta ₂ O ₅ , Al ₂ O ₃ or TiO ₂ .

The rows of memory cells are constructed in such a way that the specific resistance of the so-called thin bit lines 100 to 160, the specific resistance of the so-called thick bit lines 90, 90a and 170 and their lengths result between a selected The effective resistance of the bit line between the memory transistor and the peripheral. The layer 90 and the bordering n-doped region 90 a together function here as a thick bit line. When the bit line length is 2000F, when the length and thickness of each bit line are the minimum structure width F and when the specific resistance is 1mΩcm (this corresponds to a doping of 1× ¹⁰²⁰ cm ^-3 ) and when the minimum structure width F = 0.5 μm yields a resistance of each thick bit line of 40 kΩ. A resistance of up to 20 k[Omega] for each thin bit line is desirable. The capacitance between two bit lines with these dimensions is 0.6pF over a length of 1000 cells. In the most unfavorable case, this results in an access time of at most on the order of 2×(20+20) kΩ×0.6 pF≈50 ns.

The distance between the centers of adjacent word lines is, for example, 2F, where F is the smallest manufacturable structure dimension and is, for example, between 0.1 μm and 0.5 μm.

These webs 10 and 20 have side walls. Word lines 40 continue through these side walls. The intersections between the bit lines 90, 100, 110, 120, 130, 140, 150, 160 and 170 and the word lines 40 are located on these side walls. This cross region is defined as a memory cell. This results in an area requirement of 4F ² /N. When N=8 bit lines are arranged on top of each other, the area requirement of each memory cell is 0.5F ² , that is, 0.125 μm ² when F=0.5 μm.

The range in which each word line 40 crosses the bit lines 90, 100, 110, 120, 130, 140, 150, 160 and 170 corresponds to a memory cell group of the memory cell device. In addition to this memory cell group, selection switches not shown are arranged. These selection switches have bit selection lines. A plurality of superimposed bit lines can be combined at one node by means of a metallization (not shown). Between this node and the other doped layers are arranged as many bit selection lines as the bit lines are grouped in the node.

A particularly advantageous connection of the bit lines results from the integration of the decoder into the cell group. This integration takes place initially three-dimensionally, in particular with the same structure of the individual webs 10 and 20 . For reading out the memory cell device at least one 1 from 8 (1 aus 8) decoder is arranged. This decoder has six consecutive word lines A, A, B, B, C, C (see FIG. 3), these word lines allow conductively connecting each two stacked bit lines (100 to 160) with respective thick bit lines (90, 170), (eg 150 with 170 and 140 with 90) . A core layer is thus selected from a stack of eight stacked transistors. These MOS transistors have different starting voltages. A MOS transistor with a higher start voltage and a MOS transistor with a lower start voltage are respectively arranged alternately on top of each other in a first web of the 1-slave-8 decoder. Two MOS transistors with a higher start voltage and two MOS transistors with a lower start voltage are respectively arranged alternately on top of each other in a first web of the 1-slave-8 decoder. Four MOS transistors with a higher start voltage and four MOS transistors with a lower start voltage are each arranged one above the other in a third web of the 1-slave-8 decoder. In this case, two word lines are arranged along respective opposite side walls of the first web, the second web or the third web. The MOS transistors bordered on opposite side walls of the same tab in the same core layer are here complementary to each other. Only these thick bit lines 90, 170 are brought out from the cell group. The individual thin bit lines 100, 110, 120, 130, 140, 150, 160 arranged in between are selected by controlling the decoder accordingly.

On the 1 from N decoder, the network of each bit line entering the peripheral device from the cell group is 2F. Trellis raised to 4F on 1 from 2N decoder. On a 1 from 4N decoder the grid is even 8F.

The memory cell device shown in Figure 1 can be fabricated as follows:

In a substrate 30 made of, for example, P-doped single crystal silicon with a basic dopant concentration of 2×10 ¹⁵ cm ⁻³ , a dopant concentration of, for example, 1×10 ¹⁷ cm ⁻³ is formed by implantation. The P-doped well. The depth of this P-doped well is preferably about 1 μm.

These n-doped regions 90a are made as diffusion regions through a photomask by implanting phosphorus atoms at a dose of approximately 5×10 ¹⁵ atoms/cm ² and at a low implant energy of, for example, 100 keV. These n-doped regions 90a can thus be used as source or drain in the finished memory cell. Subsequent n-doped and low-p-doped layers are formed by epitaxial growth and in-situ doping.

Each n-doped layer 90, 100, 110, 120, 130, 140, 150, 160 and 170 and each weakly p-doped layer 95, 103, 115, 125, 133, 143, 153 and 155 are in the order of 5= Growth was performed at various temperatures of 1000°C and various pressures on the order of 100 Torr, ie 133 mbar. n _- doping is performed in a gas mixture consisting of _H2 , _SiH4 and _A3H3 . The p _- doping is performed in a gas mixture consisting of _H2 , _SiH4 and _B2H6 .

The respective higher p-doped layers are produced by implantation after epitaxial deposition of the respective layers. A photomask is used for this implantation. This implantation is performed, for example, with boron with a dose of about 3×10 ¹² cm ⁻² and an energy of the order of 25 keV.

The lowermost n-doped layer 90 and n-doped region 90 a has a greater layer thickness than the individual other n-doped layers 100 , 110 , 120 , 130 , 140 , 150 and 160 located above them. The reason for the greater thickness of this layer 90 , 90 a is that this layer is partially located within the predominantly monocrystalline semiconductor substrate 30 . Especially when the semiconductor substrate 30 consists of monocrystalline silicon, it is advisable to reduce the resistance of the layer 90 by bordering the n-doped region 90a adjoining it. The uppermost n-doped layer 170 has a lower resistance than the layers 100 , 110 , 120 , 130 , 140 , 150 and 160 . This can be achieved, for example, by forming this uppermost n-doped layer 170 from silicide or metal.

The trench structure is then produced by etching such that a trench 195 is formed between the respective webs 10 and 20 . The width of these trenches and stacks is F, and the depth of each trench is of the order of N*(100nm+50nm), where N lies mainly between 4 and 32.

Wordlines 40 are deposited after trenches 195 are etched. This is achieved, for example, by first depositing a layer conformally from the polysilicon semiconductor material or from a metal using one of the known layer-forming methods, for example CVD (Chemical Vapor Deposition). This layer is then structured using conventional photolithographic process steps in such a way that individual word lines 40 are formed. The spacing between these individual word lines 40 is chosen to be as small as possible. The lower limit of the spacing between the two centers of the bit lines is determined by the photolithographic process employed. The spacing between the centers of two adjacent word lines 40 is therefore F.

The trenches between the tabs 10 and 20 may be filled with a suitable insulating material after the wordlines 40 are placed. Such an arrangement of the insulating material is particularly advisable when, on top of the webs 10 and 20 , further planes containing conductive lines are to be placed.

In a variant of this exemplary embodiment, the stacks of transistors arranged one above the other of the webs are connected in series by interconnecting the associated bit lines 170 . In addition, individual layer stacks arranged in different webs can be connected in series by interconnecting the associated n-doped regions. This is achieved in particular as a common doped region or as a common layer. The number of levels can thus be increased.

The circuit arrangement for controlling the individual word lines and bit lines, shown below with FIG. 3, is particularly advantageous.

A 1-to-8 decoder is involved in the circuit arrangement shown in FIG. 3 . This 1 from 8 decoder is constructed as described above. In FIG. 3 the conventional circuit symbols are used for the n-channel MOS transistors and for the complementary p-channel MOS transistors. Decoders are various networks of circuits with a plurality of data inputs which are controlled in such a way that the binary information present in the inputs is in turn present at a common output.

In a 1-by-8 decoder constructed as described above and shown in FIG. 3, a selection is made from two arbitrarily adjacent bit lines arranged in a web. Transistors located between two bit lines are thus read out. The two bit lines are electrically connected by correspondingly controlling the decoder with the bit lines of each layer 90 and 170 . These bitlines 90 and 170 are thicker and therefore of lower resistance than the bitlines of the layers 100-160. Layers 90 and 170 are connected to evaluation electronics (not shown). Make this selection for this entire unit group. The 1-from-N decoder consists of LoG ₂ (N)*2 word lines, that is, for example, when N=16, it consists of 8 word lines, and when N=32, it consists of 10 word lines. The 1-slave-N decoder is designed like a cell group of individual memory modules, that is, it is more integrated than the rest of the peripherals, especially planar. The main thing is to determine the information within the scope of the selection circuit. It makes sense to repeat this decoder frequently, eg typically every 200 word lines in the cell group, to reduce the effective resistance of the bit lines.

One such decoder can be integrated into a cell set without disrupting the cell set.

The effective resistance can be further reduced by connecting the bit lines.

The invention is not limited to these shown examples. In particular, the respective conductivity types n and p can be swapped.

It is also within the scope of the invention to create a programmable memory cell device (PROM). This can be achieved in a particularly advantageous manner by forming the gate dielectric layer from a material with electrical charge carrier traps. In particular this material is replaced by an ONO dielectric layer (oxide/nitride/oxide ₎ containing a first _SiO2 layer, a _Si3N4 layer and a second _SiO2 layer.

Programming of the memory cell device is then accomplished by filling the trapping wells with electron injection. This increases the starting voltage at which a conductive channel forms below the respective word line which functions as a gate electrode. The respective starting voltage boost values can be adjusted by the time and magnitude of voltage application during programming.

On the ONO dielectric layer (oxide/nitride/oxide) the implant in the cell group can be eliminated so that only the implant in the decoder is required. When using an ONO dielectric layer, charge storage and thus programming of the memory cell arrangement can be carried out, for example by Fowler-Nordheim tunneling of electrons and also by hot electron injection.

In order to write information through the Fowler-Nordheim tunnel, the memory cell to be programmed is selected via the associated word line and the associated bit line. The bit line of the memory cell is brought to a low potential, for example to 0 volts. Conversely, the associated word line is brought to a high potential, for example to 12 volts. The other bit lines are raised to a potential so measured that it is significantly below the programming voltage. The other word lines are raised to a potential higher than the sum of the potentials of the other bit lines and the threshold voltage.

This threshold voltage is concerned with the required voltage such that a significant increase in the threshold voltage of the MOSFET is achieved in a limited time by means of Fowler-Nordheim tunneling.

Since all other bit lines intersecting the selected word line are at a higher potential during programming, other memory cells connected to the selected word line are not programmed. These memory cells are first coupled in a NAND (not-AND) configuration. The memory cells can thus be connected in such a way that a drain current flows through them. This has the advantage that the entire programming process takes place with low power consumption.

The energy required for programming a cell is about E≈5×10 ^-12 carriers/cm ^-2 ×e×10V×(0.5 μm×0.1 μm)=4×10 ^-15 J.

It can likewise be programmed by hot electron injection. A decoder selects a layer in which to write all cells whose respective word lines are at high potential. Word lines which are not at high potential are not programmed here. For programming, a saturation voltage must be applied to the MOS transistor to be programmed. For this purpose, the bit line associated with the memory cell is placed between a low potential, in particular ground potential, and a high potential, typically approximately 6 volts. The word line associated with the memory cell is brought to a potential at which the MOS transistor is in saturated operation. The voltage on this word line is less than the applied saturation voltage and is typically about 4 volts. The other word lines are brought to a higher potential, for example on the order of 7 volts. Depending on the thickness of the gate dielectric layer, this voltage is chosen such that Fowler-Nordheim tunneling does not yet occur. All other bit lines are brought to the same potential at both ends, for example half the saturation voltage.

It is important during programming that the core layers not selected for the programming process are at low potential.

This prevents the programming and current flow of individual memory cells located on other bit lines along the selected word line. Energetic electrons, also called hot electrons, are generated in the channel operation of the MOS transistor of the selected memory cell by the saturation movement at high voltages. These electrons are partially injected into the gate dielectric layer. These electrons are retained by traps in the gate dielectric layer, and these electrons raise the threshold voltage of the MOS transistor. Depending on the information to be stored in the respective memory cell, the threshold voltage of the respective MOS transistor is specifically changed in this way.

Fowler-Nordheim programming should be preferred due to shorter programming time and less programming power.

Claims (15)

1. Memory cell arrangement, - wherein, on a main surface of the semiconductor substrate, the webs protruding from the main surface of the semiconductor substrate are arranged, - wherein the webs each have a stack of doped layers, here The layers adjacent to each other in the stack are each doped with the opposite conductivity type,—wherein every three adjacent doped layers form two source/drain regions and a channel region of the transistor,—wherein each layer of the stack At least one side wall is provided with a gate dielectric layer, - wherein the word lines bounded against the gate dielectric layer in the region of the side walls of the stacks extend transversely to the tabs, - wherein , the doped layers acting as source/drain regions function as bit lines, - where so many doped layers are arranged in the stack that at least two transistors arranged one above the other are realized via these doped layers, these Transistors are connected in series via a common doped layer that acts as a common source/drain region. 2. The memory cell arrangement as claimed in claim 1, wherein the doped layers are arranged in such a multiplicity of layers that 4 to 32 transistors are arranged one above the other in the webs, each of which is arranged via a Commonly doped layers that function as source/drain regions are connected in series. 3. The memory cell arrangement as claimed in claim 1 or 2, wherein a plurality of mutually spaced word lines each extend transversely to the webs. 4. The memory cell arrangement according to one of claims 1 to 2, wherein each doped layer acting as a channel region has a concentration corresponding to two different dopant materials in the crossing range with one of the word lines The dopant material concentration of one of the values. 5. The memory cell arrangement as claimed in claim 4, wherein the two different dopant concentration values differ from each other by a factor of 2 to 10. 6. The memory cell arrangement according to claim 4, wherein one of the two different dopant concentration values lies between 0.5×10 ¹⁸ cm ⁻³ and 2×10 ¹⁸ cm ⁻³ , wherein the two Another value for different dopant concentrations lies between 0.5×10 ¹⁹ cm ⁻³ and 2×10 ¹⁹ cm ⁻³ . 7. The memory cell arrangement as claimed in claim 1, wherein the gate dielectric layer contains a carrier-trapping material. 8. The memory cell arrangement as claimed in one of claims 1 to 2, wherein the gate dielectric layer comprises a multilayer system. 9. The memory cell arrangement as claimed in one of claims 1 to 2, wherein the webs each contain two stacks separated by an insulating region. 10. The memory cell arrangement as claimed in claim 9, wherein in each case two stacks arranged in adjacent webs are connected in series via a doped region arranged in the semiconductor substrate and adjoining the main surface. 11. The memory cell arrangement of claim 9, wherein the stacks contained in a tab are connected in series via a common conductive layer disposed over the stacks and the insulating region. 12. The memory cell arrangement as claimed in one of claims 1 to 2, wherein a decoder is arranged for controlling the bit lines, the decoder having MOS transistors connected between each two bit lines. 13. The memory cell arrangement as claimed in claim 12, wherein the decoder comprises MOS transistors arranged in series on top of each other in webs. 14. A method for producing a memory cell arrangement, wherein doped layers are placed on a main face of a semiconductor substrate, wherein adjacent doped layers are each doped by the opposite conductivity type, - wherein the tabs are formed by structuring the doped layers, - wherein at least one side wall of the tabs is provided with a gate dielectric layer, - wherein the word lines are formed transverse to the The tabs extend and the word lines are each bordered against the gate dielectric layer in the extent of the sidewalls. 15. The method as claimed in claim 14, wherein the doped layers are deposited on the method by epitaxy.

Images