CN111812902B - Array substrate, display panel and display device - Google Patents

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate includes a display area and a non-display area surrounding the display area; the display area includes a plurality of gate lines; the non-display area includes a shift register group and at least one stage of virtual shift register cascaded with at least one end of the shift register group unit, the shift register group includes a plurality of cascaded shift register units, the number of transistors in each virtual shift register unit and each shift register unit, the number of capacitors, and the electrical connection relationship between each component are the same ; The channel width-to-length ratio of the first output drive transistor in the virtual shift register unit is less than the channel width-to-length ratio of the second output drive transistor in the shift register unit, so that the light transmittance of the virtual shift register unit is greater than the shift The light transmittance of the register cell. According to the embodiment of the present application, a narrow frame can be realized without affecting the curing effect of the sealant.

Description

Array substrate, display panel and display device

technical field

The present application relates to the field of display technology, in particular to an array substrate, a display panel and a display device.

Background technique

With the continuous development of electronic technology, various displays emerge as the times require, and correspondingly, display technology is also undergoing rapid changes. Among many display technologies, the narrow bezel of the display panel has become one of the mainstream display effects that people are pursuing nowadays. The display panel with narrow bezel can not only provide better display effect, but also provide a better visual experience, and has become a major trend in the display field. research hotspot.

The display panel can include straight line segment edges and arc-shaped edges. The virtual shift register in the gate drive circuit is usually adjacent to the arc-shaped edge of the display panel, but the existing virtual shift register cannot be directly placed on the display panel circle. The bottom of the frame glue at the curved edge is not conducive to realizing the narrow frame of the display panel.

application content

Embodiments of the present application provide an array substrate, a display panel, and a display device.

In the first aspect, an embodiment of the present application provides an array substrate, which includes: a display area and a non-display area surrounding the display area; the display area includes a plurality of gate lines; the non-display area includes a shift register group and a shift register At least one level of virtual shift register units cascaded at least one end of the group, the shift register group includes a plurality of cascaded shift register units, and the output terminals of each shift register unit are electrically connected to their corresponding gate lines; The virtual shift register unit and each shift register unit include multiple transistors and multiple capacitors, and each virtual shift register unit and the number of transistors in each shift register unit, the number of capacitors, and the The electrical connection relationship is the same; the virtual shift register unit includes a first output drive transistor, the shift register unit includes a second output drive transistor with the same connection relationship as the first output drive transistor, and the channel width-to-length ratio of the first output drive transistor is smaller than the channel width-to-length ratio of the second output driving transistor, so that the light transmittance of the virtual shift register unit is greater than the light transmittance of the shift register unit.

In a second aspect, the present application provides a display panel, which includes the array substrate as described in the embodiment of the first aspect.

In a third aspect, the present application provides a display device, which includes the display panel as described in the embodiment of the second aspect.

According to the array substrate, display panel and display device provided by the embodiments of the present application, in order to improve the light transmittance of the virtual shift register unit, the channel width-to-length ratio of the first output driving transistor in the virtual shift register unit is adjusted. Specifically, the channel width-to-length ratio of the first output driving transistor in the virtual shift register unit is set to be smaller than the channel width-to-length ratio of the second output driving transistor in the shift register unit, so that the transparency of the virtual shift register unit The light rate is greater than the light transmittance of the shift register unit. Since the light transmittance of the virtual shift register unit is relatively large, the virtual shift register unit can be placed directly under the frame glue, which can achieve a narrow frame without affecting the curing effect of the frame glue.

Description of drawings

Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals represent the same or similar features, appended Figures are not drawn to scale.

FIG. 1 shows a schematic structural diagram of an array substrate provided according to an embodiment of the present application;

FIG. 2 shows a schematic structural diagram of an array substrate provided according to another embodiment of the present application;

FIG. 3 shows a schematic diagram of a circuit structure of a shift register unit provided according to an embodiment of the present application;

FIG. 4 shows a schematic structural diagram of a transistor provided according to an embodiment of the present application;

FIG. 5 shows a schematic structural diagram of a shift register unit provided according to an embodiment of the present application;

FIG. 6 shows a schematic structural diagram of a virtual shift register unit provided according to an embodiment of the present application;

FIG. 7 shows a schematic structural diagram of a virtual shift register unit provided according to another embodiment of the present application;

FIG. 8 shows a schematic diagram of cascading a shift register unit and a virtual shift register unit according to an embodiment of the present application;

FIG. 9 shows a schematic diagram of cascading a shift register unit and a virtual shift register unit according to another embodiment of the present application;

FIG. 10 shows a schematic structural diagram of a display panel provided according to an embodiment of the present application;

Fig. 11 shows a schematic structural diagram of a display panel provided according to another embodiment of the present application;

Fig. 12 shows a schematic structural diagram of a display device provided according to an embodiment of the present application.

Detailed ways

The characteristics and exemplary embodiments of various aspects of the application will be described in detail below. In order to make the purpose, technical solution and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only configured to explain the application, not to limit the application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the statement "comprising..." does not exclude the presence of additional same elements in the process, method, article or device comprising said element.

It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the part is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.

It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The embodiments will be described in detail below in conjunction with the accompanying drawings.

An embodiment of the present application provides an array substrate. The array substrate in the embodiment of the present invention can be presented in various forms, some examples of which will be described below.

Fig. 1 shows a schematic structural diagram of an array substrate provided according to an embodiment of the present application. As shown in FIG. 1 , the array substrate 100 includes a display area AA and a non-display area NA surrounding the display area AA. The display area AA includes a plurality of gate lines 10 extending along a first direction X and a plurality of data lines 20 extending along a second direction Y. The second direction Y intersects the first direction X. For example, the second direction Y may be perpendicular to the first direction X, the first direction X may be a row direction, and the second direction Y may be a column direction.

The shape of the array substrate 100 may not be rectangular. For example, the array substrate 100 may include at least one section of the special-shaped edge A1, and the extending direction of the special-shaped edge A1 intersects both the first direction X and the second direction Y. Exemplarily, the special-shaped edge A1 may be an arc-shaped edge. The dummy shift register unit 41 in the array substrate 100 may be arranged adjacent to the edge of the irregular shape.

The non-display area NA includes a shift register group 30 and at least one stage of virtual shift register unit 41 cascaded with at least one end of the shift register group 30 . The shift register group 30 includes a plurality of cascaded shift register units 31 , and the output terminals of each shift register unit 31 are electrically connected to the respective corresponding gate lines 10 . The number of shift register units 31 may be the same as the number of gate lines 10 , and one shift register unit 31 is electrically connected to one gate line 10 . Each shift register unit 31 provides a scan signal to each corresponding gate line 10 through an output terminal.

In this application, the cascading manner of the shift register units 31 in the shift register group 30 and the cascading manner of the virtual shift register units 41 and the shift register units 31 are not limited. In Fig. 1 and Fig. 2, the cascade relation of the shift register unit 31 in the shift register group 30 and the cascade relation of the virtual shift register unit 41 and the shift register unit 31 are not shown, for this, hereinafter Some specific examples will be provided in the description of FIGS. 8 and 9 .

Exemplarily, the shift register group includes M cascaded shift register units, and M is greater than or equal to 2. During forward scanning, the shift register unit of the Mth stage is the last stage of shift register unit. When scanning in the opposite direction, the shift register unit of the first stage is the shift register unit of the last stage. If the pull down signal is not provided to the last-stage shift register unit, it will cause the last-stage shift register unit to be unstable, for example, it will cause the last-stage shift register unit to repeatedly send to its corresponding gate line Output scan signal.

In some embodiments, the pull-down signal can be provided to the shift register unit of the last stage through the driver chip, but this will increase the number of output ports of the driver chip. In some other embodiments, a virtual shift register unit cascaded with the last stage shift register unit can be set, so that, without increasing the output port of the driver chip, the The first-stage shift register unit provides a pull-down signal to ensure the stability of the last-stage shift register unit and prevent the last-stage shift register unit from repeatedly outputting scanning signals to its corresponding gate lines.

Each virtual shift register unit 41 and each shift register unit 31 include a plurality of transistors and a plurality of capacitors, and the number of transistors in each virtual shift register unit 41 and each shift register unit 31, the number of capacitors, and The electrical connection relationship between the various components is the same. That is, the circuit structures of each virtual shift register unit 41 and each shift register unit 31 are the same.

The virtual shift register unit 41 includes a first output drive transistor, the shift register unit 31 includes a second output drive transistor having the same connection relationship as the first output drive transistor, and the channel width-to-length ratio of the first output drive transistor is smaller than that of the second output drive transistor. The channel width-to-length ratio of the driving transistor, that is, the layout area occupied by the first output driving transistor is smaller than the layout area occupied by the second output driving transistor, so that the virtual shift register unit has more light-transmitting areas, so that the virtual shift register The light transmittance of the bit register unit is greater than the light transmittance of the shift register unit.

In the embodiment of the present application, there is no specific limitation on the number of transistors and the number of capacitors in the virtual shift register unit 41 and the shift register unit 31, and the relationship between the components in the virtual shift register unit 41 and the shift register unit 31 The electrical connection relationship between them is not specifically limited.

Exemplarily, among the multiple transistors of the virtual shift register unit 41, the first pole of one of the transistors is electrically connected to the clock signal terminal, and the second pole is electrically connected to the output terminal of the virtual shift register unit 41, then the transistor can be is the first output drive transistor of the dummy shift register cell 41 . Similarly, among the plurality of transistors in the shift register unit 31, if the first pole of one of the transistors is electrically connected to the clock signal terminal, and the second pole is electrically connected to the output terminal of the shift register unit 31, then the transistor can be a shift register unit 31. The second output of the bit register cell 31 drives a transistor.

In order to clearly illustrate the technical solutions of the embodiments of the present application, the present application exemplarily provides a specific circuit structure of a shift register unit. FIG. 3 shows a circuit structure diagram of a 9T2C shift register unit.

The 9T2C shift register circuit shown in Figure 3 includes 9 transistors (T) and 2 capacitive elements (C). The nine transistors are respectively transistor T0 to transistor T8, and the two capacitive elements are respectively capacitive element C1 and capacitive element C2. Each transistor includes a gate terminal, a first pole and a second pole. Each capacitor includes a first pole plate and a second pole plate.

The gate terminal of the transistor T0 is electrically connected to the initialization signal terminal SET, the first pole of the transistor T0 is electrically connected to the high potential signal terminal DIR1, and the second pole of the transistor T0 is electrically connected to the node P.

The gate terminal of the transistor T1 is electrically connected to the gate signal terminal Gn+1, the first pole of the transistor T1 is electrically connected to the node P, and the second pole of the transistor T1 is electrically connected to the low potential signal line DIR2.

There is a capacitive element C1 between the transistor T2 and the clock signal terminal CKB, wherein the first plate of the capacitive element C1 is electrically connected to the clock signal terminal CKB, and the second plate of the capacitive element C1 is electrically connected to the gate terminal of the transistor T2; the transistor T2 The first electrode of the transistor T2 is electrically connected to the node P, and the second electrode of the transistor T2 is electrically connected to the low potential signal terminal VGL.

The gate terminal of the transistor T3 is electrically connected to the node P, and there is a capacitive element C1 between the first electrode of the transistor T3 and the clock signal terminal CKB, wherein the first plate of the capacitive element C1 is electrically connected to the clock signal terminal CKB, and the capacitive element C1 The second plate of the transistor T3 is electrically connected to the first electrode of the transistor T3, and the second electrode of the transistor T3 is electrically connected to the low potential signal line VGL.

The gate terminal of the transistor T4 is electrically connected to the node P, the first pole of the transistor T4 is electrically connected to the clock signal terminal CKB, and the second pole of the transistor T4 is connected to the gate signal output terminal GOUT; between the gate terminal of the transistor T4 and the second pole There is a capacitive element C2, wherein a first plate of the capacitive element C2 is electrically connected to the gate terminal of the transistor T4, and a second plate of the capacitive element C2 is electrically connected to the second electrode of the transistor T4.

The gate terminal of the transistor T5 is electrically connected to the first terminal of the transistor T3, the first terminal of the transistor T5 is electrically connected to the gate signal output terminal GOUT, and the second terminal of the transistor T5 is electrically connected to the low potential signal terminal VGL.

The gate terminal of the transistor T6 is electrically connected to the clock signal terminal CK, the first pole of the transistor T6 is electrically connected to the gate signal output terminal GOUT, and the second pole of the transistor T6 is electrically connected to the low potential signal terminal VGL.

The gate terminal of the transistor T7 is electrically connected to the reset signal terminal RESET, the first pole of the transistor T7 is electrically connected to the node P, and the second pole of the transistor T7 is electrically connected to the low potential signal terminal VGL.

The gate terminal of the transistor T8 is electrically connected to the reset signal terminal RESET, the first pole of the transistor T8 is electrically connected to the gate signal output terminal GOUT, and the second pole of the transistor T8 is electrically connected to the low potential signal terminal VGL.

Take the 9T2C circuit shown in FIG. 3 as an example in which both the virtual shift register unit 41 and the shift register unit 31 have circuit structures, wherein the gate signal output terminal GOUT is the virtual shift register unit 41 and the shift register unit 31 output terminal. The first pole of the transistor T4 shown in FIG. 3 is electrically connected to the clock signal terminal CKB, and the second pole of the transistor T4 is electrically connected to the gate signal output terminal GOUT. The transistor T4 is the first output driver of the virtual shift register unit 41. The transistor and the second output of the shift register unit 31 drive the transistor.

Changes in the channel width-to-length ratio of the transistor will affect the working performance of the shift register unit, and the shift register unit 31 will provide an effective driving signal to the display area AA, so the second output in the shift register unit 31 can be maintained The channel width-to-length ratio of the driving transistor is unchanged, and only the channel width-to-length ratio of the first output driving transistor in the virtual shift register unit 41 is changed, so that the channel width-to-length ratio of the first output driving transistor is smaller than that of the second output The channel width-to-length ratio of the drive transistor.

Exemplarily, as shown in FIG. 4 , the transistor includes a gate G, a semiconductor portion B, a source S and a drain D. As shown in FIG. Wherein, the distance between the source S and the drain D is the channel length L of the transistor, and the direction perpendicular to L is the channel width W of the transistor. Exemplarily, the gate G can be formed of metal.

It should be noted that there are various specific structures of the transistor, and the transistor shown in FIG. 4 is a "comb" transistor. Exemplarily, each transistor structure in the virtual shift register unit 41 and the shift register unit 31 may be a “comb” transistor as shown in FIG. 4 . The transistors in the virtual shift register unit 41 and the shift register unit 31 can also be transistors of other structures, and the present application will not list them one by one here. For the virtual shift register unit 41 and the shift register unit 31, the present application The specific structure of each transistor is not limited.

Be the 9T2C circuit shown in Fig. 3 with the circuit structure of virtual shift register unit 41 and shift register unit 31, and each transistor in virtual shift register unit 41 and shift register unit 31 is all shown in Fig. 4 A "comb" transistor is taken as an example. FIG. 5 shows a schematic structural diagram of a shift register unit, and FIG. 6 shows a schematic structural diagram of a virtual shift register unit. FIG. 5 and FIG. 6 only illustrate the distribution structure of each element, and do not show the connection relationship of each element.

The distribution structure of the transistors T0 to T8 and the capacitive elements C1 and C2 in the shift register unit 31 is shown in FIG. 5 , wherein the transistor T4 is the second output driving transistor 311 of the shift register unit 31 . The applicant of the present application found that the channel width-to-length ratio of a transistor will affect the drive capability of the transistor. Generally, the larger the channel width-to-length ratio of a transistor, the stronger its drive capability will be. The drive capability of transistors with different functions will change, corresponding to The impact on the operational performance of the shift register cells is different. Wherein, the driving capability of the output driving transistor has relatively great influence on the working performance of the shift register unit. In order to ensure the working performance of the shift register unit 31 , as shown in FIG. 5 , the channel width-to-length ratio of the second output driving transistor 311 (transistor T4 ) in the shift register unit 31 can be set relatively large.

Exemplarily, the structures of the transistors T0 to T8 may all be “comb” transistors as shown in FIG. 4 , the channel lengths of the transistors T0 to T8 may be the same, and the channel widths of the transistors T0 to T8 may be different. Wherein, the channel width of the transistor T4 may be the largest, that is, the layout area occupied by the transistor T4 is the largest compared to other transistors.

The distribution structure of the transistors T0 to T8 and the capacitive elements C1 and C2 in the virtual shift register unit 41 is shown in FIG. 6 , wherein the transistor T4 is the first output driving transistor 411 of the virtual shift register unit 41 . The difference between FIG. 6 and FIG. 5 may be that the channel width-to-length ratio of the first output driving transistor 411 in FIG. 6 is smaller than the channel width-to-length ratio of the second output driving transistor 311 in FIG. The layout area occupied by the output driving transistor 411 is smaller than the layout area occupied by the second output driving transistor 311 in FIG. 5 . Compared with FIG. 5, the virtual shift register unit 41 shown in FIG. 6 has a larger light-transmitting area. It can be understood that, before the channel width-to-length ratio of the first output driving transistor 411 is reduced, the first output driving transistor 411 The channel width-to-length ratio of 411 is the same as the channel width-to-length ratio of the second output driving transistor 311, and after the channel width-to-length ratio of the first output driving transistor 411 is reduced, the reduced area constitutes a virtual shift register The light transmission area 412 of the unit 41 increases the light transmittance of the virtual shift register unit 41 so that the light transmittance of the virtual shift register unit 41 is greater than the light transmittance of the shift register unit 31 .

A display panel generally includes the array substrate 100 as described in the embodiment of the present application and an opposite substrate disposed opposite to the array substrate 100 , and the array substrate and the opposite substrate are bonded together by sealant. During the curing process of the frame glue, it is necessary to use ultraviolet light (Ultraviolet, UV) to cure the frame glue. Typically, the gate in a transistor is formed from a block of metal through which ultraviolet light cannot pass. And the dummy shift register unit 41 is usually adjacent to the special-shaped edge A1 of the array substrate 100, if the dummy shift register unit 41 is directly arranged under the sealant without increasing the light transmittance of the dummy shift register unit 41, It is not conducive to the curing of the frame glue; and the space of the non-display area at the special-shaped edge A1 is relatively tight, if the light transmittance of the virtual shift register unit 41 is not increased and the virtual shift register unit 41 is not arranged under the frame glue, then Narrow bezels are not exploited.

In the embodiment of the present application, the channel width-to-length ratio of the first output driving transistor 411 in the virtual shift register unit 41 is set to be smaller than the channel width-to-length ratio of the second output driving transistor 311 in the shift register unit 31, that is, the virtual shift The light transmission area of the bit register unit 41 is larger, so that the light transmittance of the virtual shift register unit 41 is greater than the light transmittance of the shift register unit 31 . Since the light transmittance of the virtual shift register unit 41 is relatively large, the virtual shift register unit 41 can be placed directly under the sealant, so that a narrow frame can be realized without affecting the curing effect of the sealant.

In some embodiments, the channel length of the first output driving transistor 411 in FIG. 6 and the channel length of the second output driving transistor 311 in FIG. 5 may be the same, and the channel width of the first output driving transistor 411 in FIG. 6 is smaller than The channel width of the second output driving transistor 311 in FIG. 5 .

In some embodiments, please refer to FIG. 1 , the array substrate 100 may further include dummy gate lines 11 , and the dummy gate lines 11 are located in the non-display area of the array substrate 100 . The number of dummy gate lines 11 may be the same as the number of dummy shift register units 41 . One dummy gate line 11 is electrically connected to the output terminal of one dummy shift register unit 41 . That is, the output end of the dummy shift register unit 41 is not only electrically connected to the dummy gate line 11 , but also electrically connected to the cascaded end of the shift register unit 31 cascaded therewith. Wherein, the cascaded end of the shift register unit 31 can be understood as the input end of the shift register unit 31 that receives the initialization signal and the gate signal. For example, the circuit structure of the shift register unit 31 is shown in Figure 3, the gate of the transistor T0 in the shift register unit 31 is electrically connected to the initialization signal terminal SET, and the gate of the transistor T1 is electrically connected to the gate signal terminal Gn+1 , that is, the gates of the transistors T0 and T1 in the shift register unit 31 may be the cascaded terminals of the shift register unit 31 . Similarly, the gates of the transistors T0 and T1 in the virtual shift register unit 41 may be cascaded terminals of the virtual shift register unit 41 .

In some other embodiments, please refer to FIG. 2 . The difference between FIG. 2 and FIG. 1 is that the array substrate 100 is not provided with a dummy gate line 11 , that is, the output terminal of the dummy shift register unit 41 is only connected to the shift register unit 41 cascaded with it. The cascaded ends of the bit register units 31 are electrically connected. Usually, the line width of the dummy gate line 11 is about 50 um. If the dummy gate line 11 is provided, it needs to occupy a width of about 50 um in the non-display area NA, which is not conducive to realizing a narrow border. However, in the present application, the dummy gate lines 11 are no longer provided, which is beneficial to the realization of narrow borders.

In addition, the inventors of the present application found that the output load of the dummy shift register unit 41 is smaller than the output load of the shift register unit 31 when the dummy gate line 11 is not provided. The load size will cause the signal output delay of the output terminal to be different. Generally, the greater the load, the greater the delay, that is, the output signal output delay of the virtual shift register unit 41 is smaller than the output signal output delay of the shift register unit 31, which affects the display. Effect. In this application, the channel width-to-length ratio of the first output driving transistor in the virtual shift register unit 41 is smaller than the channel width-to-length ratio of the second output driving transistor in the shift register unit 31, that is, the driving capability of the virtual shift register unit 41 The driving capability of the shift register unit 31 is smaller than that of the shift register unit 31, so that the problem that the output signal output delay of the virtual shift register unit 41 is inconsistent with the output signal output delay of the shift register unit 31 can be improved, thereby improving the display effect.

In some optional embodiments, the light-transmitting region 412 of the virtual shift register unit 41 is a continuous light-transmitting region. Exemplarily, as shown in FIG. 6 , the first output driving transistor 411 in the virtual shift register unit 41 may be arranged close to the edge of the virtual shift register unit 41 . For example, the first output driving transistor 411 is arranged close to the upper edge of the virtual shift register unit 41 , so that the area under the first output driving transistor 411 can form a continuous light-transmitting region 412 . The continuous light-transmitting region 412 is more likely to transmit ultraviolet light, which is more conducive to improving the curing effect of the frame glue.

Still taking the circuit structure of virtual shift register unit 41 and shift register unit 31 as the 9T2C circuit shown in FIG. 3 as an example, wherein transistor T4 is the first output driving transistor of virtual shift register unit 41 and the shift The second output of the register unit 31 drives the transistor, and the capacitive element C2 is electrically connected to the gate of the transistor T4, that is, the capacitive element C2 is the first capacitor 413 of the virtual shift register unit 41 and the second capacitor 312 of the shift register unit 31 .

Exemplarily, the array substrate 100 may include a clock signal line CKB, and the first electrode of the first output driving transistor (transistor T4 ) is electrically connected to the clock signal terminal CKB through the clock signal line CKB. The clock signal line CKB will cause coupling to the gate potential of the first output driving transistor through the parasitic capacitance on the gate of the first output driving transistor, causing the leakage current of the first output driving transistor to increase, so that the first output driving transistor drives Ability is unstable. The inventors of the present application have found that increasing the capacitance of the capacitive element electrically connected to the gate of the first output drive transistor in the virtual shift register unit 41 is to set the capacitance of the first capacitor 413 of the virtual shift register unit 41 To be larger than the capacitance of the second capacitor 312 of the shift register unit 31, the influence caused by the above coupling can be reduced.

Exemplarily, the channel width-to-length ratio of the first output driving transistor 411 is recorded as a first value, and the channel width-to-length ratio of the second output driving transistor 311 is recorded as a second value. The inventors of the present application found through a large amount of experimental data that when the ratio of the first value to the second value is less than or equal to 0.2, the light transmittance of the virtual shift register unit 41 can be better than the light transmittance of the shift register unit 31 rate, so that when the virtual shift register unit 41 is placed directly under the sealant, the curing effect on the sealant can be better ensured.

In addition, as shown in FIG. 2, in the case where the output end of the virtual shift register unit 41 is only electrically connected to the cascaded end of the shift register unit 31 cascaded with it, the inventor of the present application found through a large amount of experimental data that Setting the ratio of the first value to the second value to be less than or equal to 0.2 can better improve the problem that the output signal output delay of the virtual shift register unit 41 is inconsistent with the output signal output delay of the shift register unit 31 .

Exemplarily, the channel width and length of the second output driving transistor 311 can be kept unchanged, and the channel width and length ratio of the first output driving transistor 411 can be reduced. For example, the channel width of the first output driving transistor 411 may be reduced. That is, the ratio of the channel width of the first output driving transistor 411 to the channel width of the second output driving transistor 311 may be set to be less than or equal to 0.2.

The inventors of the present application also found through a large amount of experimental data that when the ratio of the capacitance of the first capacitor 413 to the capacitance of the second capacitor 312 is greater than or equal to 2, the above-mentioned influence caused by the coupling can be better reduced.

The capacitance of the capacitor is proportional to the area of the plates of the capacitor, and the capacitance of the capacitor is inversely proportional to the distance between the plates. Exemplarily, both the first capacitor 413 and the second capacitor 312 include two opposite plates. For example, the capacity of the first capacitor 413 can be increased by increasing the plate area of the first capacitor 413 . For another example, the capacitance of the first capacitor 413 can be increased by reducing the distance between two plates of the first capacitor 413 . However, by increasing the area of the plates of the first capacitor 413 , it is relatively easy to realize in terms of technology.

Fig. 7 shows a schematic structural diagram of a virtual shift register unit provided according to another embodiment of the present application. The difference between FIG. 7 and FIG. 5 may be that the channel width-to-length ratio of the first output driving transistor 411 in FIG. 7 is smaller than the channel width-to-length ratio of the second output driving transistor 311 in FIG. The layout area occupied by the output drive transistor 411 is smaller than the layout area occupied by the second output drive transistor 311 in FIG. 5; the plate area of the first capacitor 413 in FIG. 7 is larger than the plate area of the second capacitor 312 in FIG. The layout area occupied by the plates of the first capacitor 413 is larger than the layout area occupied by the plates of the second capacitor 312 in FIG. 5 . Exemplarily, the layout area occupied by the first output driving transistor 411 and the first capacitor 413 in FIG. 7 may be approximately equal to the layout area occupied by the second output driving transistor 311 and the second capacitor 312 in FIG. It is not necessary to increase the overall layout area occupied by the virtual shift register unit 41 .

Please continue to refer to FIG. 7 , at least partial areas of the two plates of the first capacitor 413 may be hollow structures. The orthographic projections of the hollowed-out areas 4130 of the two plates of the first capacitor 413 on the array substrate overlap, and the hollowed-out areas 4130 are strip-shaped areas, and the hollowed-out areas 4130 constitute the light-transmitting area 412 of the array substrate 100 . The two pole plates of the first capacitor 413 are set as a hollow structure, which can transmit ultraviolet light while increasing the capacitance of the first capacitor 413, and the strip-shaped hollow area 4130 is more likely to transmit ultraviolet light, thereby making it easier to It is beneficial to improve the curing effect of the frame glue.

Exemplarily, the two plates of the first capacitor 413 may be non-transparent conductive structures. The plates of the first capacitor 413 are hollow structures, which can be understood as each plate of the first capacitor 413 is formed by connecting multiple conductive blocks. In some embodiments, as shown in FIG. 7 , each plate of the first capacitor 413 includes three conductive blocks 4132 , and the width d of each conductive block 4132 may be less than or equal to 40 μm. The hollow area 4130 may be located between two adjacent conductive blocks 4132 .

In some optional embodiments, as shown in FIG. 1 or FIG. 2 , the non-display area NA may include a sealant area NA1 , and the sealant area NA1 is arranged around the display area AA. Sealant may be coated in the sealant area NA1 to bond the array substrate 100 and the opposite substrate. At least the first capacitor 413 in the virtual shift register unit 41 is located in the sealant area NA1. As shown in FIG. 7 , the first capacitor 413 is a hollow structure, and the first capacitor 413 is arranged in the sealant area NA1 , which can achieve a narrow frame without affecting the curing effect of the sealant.

It should be noted that, in order to clearly illustrate the technical solution of the embodiment of the present application, in FIG. 1 and FIG. 2 , the sealant area NA1 is not provided with a filling pattern, but is only shown in a wireframe.

In some optional embodiments, as shown in FIG. 8 , the shift register group 30 may include N stages of shift register units 31 , where N is a positive integer greater than or equal to 4. In all the odd-numbered shift register units from the first stage shift register unit to the Nth stage shift register unit, adjacent two stages of shift register units are cascaded with each other, for example, the first stage shift register unit and the third stage The shift register units are cascaded, the third-stage shift registers are single-cascaded and the fifth-stage shift register units are cascaded; and all even-numbered-stage shift register units are cascaded between adjacent two-stage shift register units, For example, the shift register units of the second stage are cascaded with the shift register units of the fourth stage, and the shift register units of the fourth stage are cascaded with the shift register units of the sixth stage.

The array substrate 100 may include at least two dummy shift register units 41 . For example, the array substrate 100 includes two dummy shift register units 41, which are respectively a first dummy shift register unit and a second dummy stage shift register unit. The first virtual stage shift register unit is cascaded with the N-1th stage shift register unit, and the second virtual stage shift register unit is cascaded with the Nth stage shift register unit.

The cascading between the first virtual stage shift register unit and the N-1th stage shift register unit refers to the cascade connection between the output terminal OUT of the first virtual stage shift register unit and the N-1th stage shift register unit The output terminal OUT of the N-1th stage shift register unit is connected to the cascade terminal of the first virtual stage shift register unit. The cascading between the second virtual stage shift register unit and the Nth stage shift register unit means that the output terminal OUT of the second virtual stage shift register unit is connected to the cascaded end of the Nth stage shift register unit, and the first stage The output terminal OUT of the N-stage shift register unit is connected to the cascaded end of the second dummy-stage shift register unit.

Still taking the circuit structure of virtual shift register unit 41 and shift register unit 31 as the 9T2C circuit shown in FIG. 3 as an example, the gate of transistor T0 in shift register unit 31 can be understood as the initialization of shift register unit 31 The signal input terminal Set, the gate of the transistor T1 can be understood as the gate signal input terminal Gn+1 of the shift register unit 31; similarly, the gate of the transistor T0 in the virtual shift register unit 41 can be understood as a virtual shift register The initialization signal input terminal Set of the unit 41 and the gate of the transistor T1 can be understood as the gate signal input terminal Gn+1 of the virtual shift register unit 41 . As shown in Figure 8, specifically, the output terminal OUT of the shift register unit of the first virtual stage can be connected to the gate signal input terminal Gn+1 of the shift register unit of the N-1 stage, and the shift register unit of the N-1 stage The output terminal OUT of the register unit is connected to the initialization signal input terminal Set of the first virtual stage shift register unit; the output terminal OUT of the second virtual stage shift register unit is connected to the gate signal input terminal Gn of the Nth stage shift register unit +1 connection, the output terminal OUT of the shift register unit of the Nth stage is connected to the initialization signal input terminal Set of the shift register unit of the second dummy stage.

When scanning in the forward direction, the shift register unit of the N-1 stage provides an initialization signal to the shift register unit of the first virtual stage, and the shift register unit of the Nth stage provides an initialization signal to the shift register unit of the second virtual stage; When scanning, the shift register unit of the first virtual stage provides a gate signal to the shift register unit of the N-1th stage, and the shift register unit of the second virtual stage provides a gate signal to the shift register unit of the Nth stage.

In other optional embodiments, as shown in FIG. 9 , the array substrate 100 includes four virtual shift register units 41, which are respectively the first virtual shift register unit, the second virtual stage shift register unit, the third A dummy shift register unit and a fourth dummy stage shift register unit. The difference between Fig. 9 and Fig. 8 is that the shift register unit of the third virtual stage is cascaded with the shift register unit of the first stage, and the shift register unit of the fourth virtual stage is connected with the shift register unit of the second stage. cascade.

Still taking the circuit structure of the virtual shift register unit 41 and the shift register unit 31 as the 9T2C circuit shown in Figure 3 as an example, the cascading between the third virtual stage shift register unit and the first stage shift register unit is specific It may be that the output terminal OUT of the third virtual stage shift register unit is connected to the initialization signal input terminal Set of the first stage shift register unit, and the output terminal OUT of the first stage shift register unit is connected to the third virtual stage shift register unit The gate signal input terminal Gn+1 is connected. The cascade connection between the shift register unit of the fourth virtual stage and the shift register unit of the second stage may specifically be that the output terminal OUT of the shift register unit of the fourth virtual stage is connected with the initialization signal input terminal Set of the shift register unit of the second stage The output terminal OUT of the shift register unit of the second stage is connected to the gate signal input terminal Gn+1 of the shift register unit of the fourth virtual stage.

During forward scanning, the third virtual stage shift register unit provides an initialization signal to the first stage shift register unit, and the fourth virtual stage shift register unit provides an initialization signal to the second stage shift register unit; , the shift register unit of the first stage provides a gate signal to the shift register unit of the third virtual stage, and the shift register unit of the second stage provides a gate signal to the shift register unit of the fourth virtual stage.

Optionally, as shown in FIGS. 8 and 9 , the array substrate may further include clock signal lines CK1 / CK2 / CKB1 / CKB2 and a reset signal line RESET. The virtual shift register unit and elements in the shift register unit are connected to corresponding signal terminals through clock signal lines CK1/CK2/CKB1/CKB2 and reset signal line RESET.

The present application also provides a display panel. Fig. 10 shows a schematic structural diagram of a display panel provided according to an embodiment of the present application. As shown in FIG. 10 , the display panel 1000 provided by the embodiment of the present application may include an array substrate 100 , an opposite substrate 200 and a liquid crystal layer 300 disposed between the array substrate 100 and the opposite substrate 200 . Wherein, the array substrate 100 is the array substrate described in any one of the above-mentioned embodiments. The opposite substrate 200 may be a color filter substrate.

Fig. 11 shows a schematic structural diagram of a display panel provided according to another embodiment of the present application. As shown in FIG. 11 , the display panel 1000 provided by the embodiment of the present application may include an array substrate 100 and a counter substrate 200 . Wherein, the array substrate 100 is the array substrate described in any one of the above-mentioned embodiments. The opposing substrate 200 may be a protective cover, such as a glass cover. The display panel shown in FIG. 11 may be an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panel.

Those skilled in the art should understand that in other implementations of the present application, the display panel can also be a micro light-emitting diode (Micro LED) display panel, a quantum dot display panel, and the like.

The display panel provided in the embodiment of the present application has the beneficial effects of the array substrate provided in the embodiment of the present application. For details, reference may be made to the specific descriptions of the array substrate in the above embodiments, and details will not be repeated here in this embodiment.

The present application also provides a display device, including the display panel provided in the present application. Please refer to FIG. 12 , which is a schematic structural diagram of a display device provided by an embodiment of the present application. The display device 2000 provided in FIG. 12 includes the display panel 1000 provided in any one of the above-mentioned embodiments of the present application. The embodiment in FIG. 12 only takes a mobile phone as an example to illustrate the display device 2000. It can be understood that the display device provided in the embodiment of the present application may be a computer, a television, a vehicle-mounted display device, and other display devices with display functions. The application is not specifically limited to this. The display device provided by the embodiment of the present application has the beneficial effects of the display panel provided by the embodiment of the present application. For details, reference may be made to the specific descriptions of the display panel in the above embodiments, and details will not be repeated in this embodiment.

In accordance with the embodiments of the present application as described above, these embodiments do not describe all details in detail, nor do they limit the application to only the specific embodiments described. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. This application is to be limited only by the claims, along with their full scope and equivalents.

Claims (11)

1. An array substrate, comprising:

a display area and a non-display area surrounding the display area;

the display area comprises a plurality of gate lines;

the non-display area comprises a shift register group and at least one stage of virtual shift register unit cascaded with at least one end part of the shift register group, the shift register group comprises a plurality of cascaded shift register units, and the output end of each shift register unit is electrically connected with a corresponding gate line;

each virtual shift register unit and each shift register unit respectively comprise a plurality of transistors and a plurality of capacitors, and the number of the transistors, the number of the capacitors and the electrical connection relationship among the components in each virtual shift register unit and each shift register unit are the same;

the virtual shift register unit comprises a first output driving transistor, the shift register unit comprises a second output driving transistor which is connected with the first output driving transistor in the same relation, and the channel width-length ratio of the first output driving transistor is smaller than that of the second output driving transistor, so that the light transmittance of the virtual shift register unit is larger than that of the shift register unit;

the array substrate comprises at least one section of non-parallel edge, and the virtual shift register unit is adjacent to the non-parallel edge.

2. The array substrate of claim 1, wherein the dummy shift register cells comprise light transmissive regions, the light transmissive regions being continuous light transmissive regions.

3. The array substrate of claim 2, wherein the dummy shift register unit further comprises a first capacitor electrically connected to the gate of the first output driving transistor, the shift register unit comprises a second capacitor connected to the first capacitor in the same relationship, and the capacitance of the first capacitor is greater than the capacitance of the second capacitor.

4. The array substrate of any one of claims 1 to 3, wherein the channel width and length of the first output driving transistor is a first value, the channel width and length ratio of the second output driving transistor is a second value, and the ratio of the first value to the second value is less than or equal to 0.2.

5. The array substrate of claim 3, wherein a ratio of a capacitance of the first capacitor to a capacitance of the second capacitor is greater than or equal to 2.

6. The array substrate of claim 3, wherein the first capacitor and the second capacitor each comprise two opposite plates, and the plate area of the first capacitor is larger than the plate area of the second capacitor.

7. The array substrate of claim 6, wherein at least some regions of the two plates of the first capacitor are both hollow structures, orthogonal projections of the hollow regions of the two plates of the first capacitor on the array substrate overlap, the hollow regions are bar-shaped regions, and the hollow regions constitute the light-transmitting regions.

8. The array substrate of claim 7, wherein the non-display area comprises a frame glue area, the frame glue area is disposed around the display area, and at least the first capacitor in the dummy shift register unit is located in the frame glue area.

9. The array substrate of claim 1, wherein the array substrate comprises at least a first dummy shift register unit and a second dummy shift register unit;

the first virtual shift register unit and the N-1 stage shift register unit are cascaded, the second virtual shift register unit and the N stage shift register unit are cascaded, adjacent two stages of shift register units in all odd-numbered stage shift register units from the first stage shift register unit to the N stage shift register unit are cascaded mutually, and adjacent two stages of shift register units in all even-numbered stage shift register units are cascaded mutually; n is a positive integer greater than or equal to 4.

10. A display panel comprising the array substrate according to any one of claims 1 to 9.

11. A display device characterized by comprising the display panel according to claim 10.

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