CN108803172B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN108803172B CN108803172B CN201810698770.6A CN201810698770A CN108803172B CN 108803172 B CN108803172 B CN 108803172B CN 201810698770 A CN201810698770 A CN 201810698770A CN 108803172 B CN108803172 B CN 108803172B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
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- Theoretical Computer Science (AREA)
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Abstract
本发明公开了一种阵列基板、显示面板及显示装置，该阵列基板包括：显示区域和围绕所述显示区域的非显示区域，所述显示区域包括至少一段外凸异形显示边界，所述非显示区域包括异形子非显示区域，所述外凸异形显示边界位于所述异形子非显示区域和所述显示区域之间；多条栅线，所述异形子非显示区域包括栅极驱动电路，所述栅极驱动电路与位于所述显示区域的所述多条栅线电连接；栅极驱动信号总线，所述栅极驱动信号总线与所述栅极驱动电路电连接，通过将栅极驱动信号总线设置在所述栅极驱动电路靠近所述显示区域的一侧的方式，减少栅极驱动信号总线占据非显示区域的面积，以实现显示面板的窄边框设计。
The invention discloses an array substrate, a display panel and a display device. The array substrate includes: a display area and a non-display area surrounding the display area, the display area includes at least a section of a convex profiled display boundary, the non-display area The area includes a special-shaped sub-non-display area, and the convex special-shaped display boundary is located between the special-shaped sub-non-display area and the display area; a plurality of gate lines, the special-shaped sub-non-display area includes a gate drive circuit, so The gate driving circuit is electrically connected to the plurality of gate lines located in the display area; the gate driving signal bus is electrically connected to the gate driving circuit, and the gate driving signal is electrically connected to the gate driving circuit. The way that the bus lines are arranged on the side of the gate driving circuit close to the display area reduces the area of the non-display area occupied by the gate drive signal bus lines, so as to realize the narrow frame design of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
With the development of display technology, people have higher and higher requirements on functionality and attractiveness of display panels, and in order to meet the requirements, people pay more and more attention to the design of special-shaped display panels.
As shown in fig. 1, a special-shaped display panel in the prior art includes a display area I and a non-display area II, at least one convex special-shaped display boundary III located between the display area I and the non-display area II, a gate driving circuit 10 formed by cascading a plurality of shift registers SR and located adjacent to the display area I, and a gate driving signal bus 20 connected to the gate driving circuit 10 and located on a side of the gate driving circuit 10 away from the display area I. The gate driving signal bus 20 includes a plurality of signal lines, the sum of the areas of the signal lines occupies about half of the area of the gate driving signal bus 20, and the non-line changing regions (the spacing regions between the signal lines) in the gate driving signal bus 20 occupy a large amount of area of the non-display region, which is not favorable for the narrow frame design of the display panel.
Therefore, how to implement the narrow frame design of the display panel is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a display panel and a display device, which are used for solving the problem that the area of a gate drive signal bus in the prior art occupies a large non-display area and is not beneficial to the narrow-frame design of the display panel.
An embodiment of the present invention provides an array substrate, including:
the display area comprises at least one convex special-shaped display boundary, the non-display area comprises a special-shaped sub non-display area, and the convex special-shaped display boundary is positioned between the special-shaped sub non-display area and the display area;
the special-shaped sub non-display area comprises a grid driving circuit, and the grid driving circuit is electrically connected with the grid lines in the display area;
and the grid driving signal bus is electrically connected with the grid driving circuit and is positioned on one side of the grid driving circuit close to the display area.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the gate driving circuit includes a plurality of shift registers, and each of the shift registers is cascaded by a cascade trace;
the cascade routing is located between the gate driving signal bus and the gate driving circuit.
In a possible implementation manner, in the display panel provided in an embodiment of the present invention, the shift register includes:
at least two grid line output tubes, wherein, set up in parallel between the grid line output tube.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the display panel further includes: the maximum size of the boundary of any side of the orthographic projection of the grid line output tube on the substrate is less than or equal to 45 micrometers.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the display panel further includes:
the grid line driving circuit comprises a plurality of grid line fan-out wires, a plurality of grid driving circuits and a plurality of grid lines, wherein the grid line fan-out wires are electrically connected with the grid driving circuits respectively;
the display area comprises a special-shaped sub-display area and a rectangular sub-display area, and the special-shaped sub-display area comprises the convex special-shaped display boundary;
the plurality of grid lines comprise a first grid line and a second grid line, the first grid line is positioned in the special-shaped sub-display area, the second grid line is positioned in the rectangular sub-display area, and the load of the first grid line is smaller than that of the second grid line;
the plurality of grid fan-out wires comprise a first grid fan-out wire, and the first grid fan-out wire is electrically connected with the first grid line;
the first gate fan-out trace intersects at least one of the gate drive signal buses non-perpendicularly.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the first gate fan-out trace intersects at least one gate driving signal bus non-perpendicularly, and at the intersection, the first gate fan-out trace has a first line width, and outside the intersection, the first gate fan-out trace has a second line width, where the first line width is greater than the second line width.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the first gate fan-out trace intersects at least one gate driving signal bus non-perpendicularly, and at an intersection, an extending direction of the first gate fan-out trace is the same as an extending direction of the gate driving signal bus.
In a possible implementation manner, in the display panel provided in an embodiment of the present invention, the gate driving signal bus includes:
one or more of a clock signal line, a reference voltage signal line, an initial signal line, and a reset signal line.
On the other hand, based on the same inventive concept, an embodiment of the present invention further provides a display panel, including the array substrate provided in the embodiment of the present invention.
On the other hand, based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel provided by the embodiment of the present invention.
The invention has the following beneficial effects:
the embodiment of the invention provides an array substrate, a display panel and a display device, wherein the array substrate comprises: the display area comprises at least one convex special-shaped display boundary, the non-display area comprises a special-shaped sub non-display area, and the convex special-shaped display boundary is positioned between the special-shaped sub non-display area and the display area; the special-shaped sub non-display area comprises a grid driving circuit, and the grid driving circuit is electrically connected with the grid lines in the display area; the grid driving signal bus is electrically connected with the grid driving circuit, and the area of a non-display area occupied by the grid driving signal bus is reduced in a mode that the grid driving signal bus is arranged on one side, close to the display area, of the grid driving circuit, so that the narrow frame design of the display panel is realized.
Drawings
FIG. 1 is a partially enlarged schematic view of a convex shaped display boundary of a display panel in the related art;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
FIG. 4 is a partially enlarged schematic structural view of a convex shaped display boundary of the array substrate in FIG. 2 or FIG. 3;
FIG. 5 is a partially enlarged schematic structural view of another convex shaped display boundary of the array substrate in FIG. 2 or FIG. 3;
fig. 6 is a schematic diagram of a shift register in the related art;
FIG. 7 is a schematic diagram of a shift register according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a specific structure of a gate output tube according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of another embodiment of a gate output transistor according to the present invention;
FIG. 10 is a schematic diagram illustrating another embodiment of a gate output transistor according to the present invention;
FIG. 11 is a schematic diagram of another embodiment of a gate output transistor according to the present invention;
FIG. 12 is a partially enlarged schematic structural view of the array substrate shown in FIG. 2 or FIG. 3 at a boundary of a convex shaped display;
fig. 13 is a schematic structural diagram of a gate line fan-out trace in an array substrate according to an embodiment of the present invention;
fig. 14 is a schematic cross-sectional view of a transistor, a gate fan-out trace, and a gate driving signal bus according to an embodiment of the invention;
fig. 15 is a schematic structural diagram of a gate line fan-out trace in an array substrate according to an embodiment of the present invention;
fig. 16 is a schematic view of another structure of a gate line fan-out trace in an array substrate according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of a gate driving circuit in an array substrate according to an embodiment of the invention;
fig. 18 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the invention;
fig. 19 is a schematic structural diagram of an electroluminescent display panel according to an embodiment of the present invention;
fig. 20 is a schematic structural diagram of a display device according to an embodiment of the invention;
fig. 21 is another schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
A display panel in the related art, as shown in fig. 1, fig. 1 is a partially enlarged structural schematic view of a convex special-shaped display boundary of the display panel in the related art; in order to drive a gate line (not specifically shown in the figure) located in the display area I, a gate driving circuit 10 formed by cascading a plurality of shift registers SR and a gate driving signal bus 20 connected to the gate driving circuit 10 and located on a side of the gate driving circuit 10 away from the display area I are disposed in the display area I adjacent to the display area I. The gate driving signal bus 20 includes a plurality of signal lines, the sum of the areas of the signal lines occupies about half of the area of the gate driving signal bus 20, and the non-line changing region (the space between the signal lines) in the gate driving signal bus 20 occupies a large area of the non-display region II, which is not favorable for the narrow frame design of the display panel.
The embodiment of the invention provides an array substrate, a display panel and a display device, aiming at the technical problem that a display panel with a convex special-shaped display function is not beneficial to realizing the narrow frame design of the display panel in the related technology. In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a display panel and a display device according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The shapes and sizes of the various elements in the drawings are not to scale and are merely intended to illustrate the invention.
Specifically, an array substrate provided by an embodiment of the present invention is shown in fig. 2, fig. 3 and fig. 4, where fig. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention, fig. 3 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention, and fig. 4 is a partially enlarged schematic structural diagram of a convex irregular-shaped display boundary of the array substrate in fig. 2 or fig. 3; the array substrate includes:
the display area A comprises at least one section of convex special-shaped display boundary C, the non-display area B comprises a special-shaped sub non-display area, and the convex special-shaped display boundary C is positioned between the special-shaped sub non-display area and the display area A;
the special-shaped sub non-display area comprises a grid driving circuit 1, and the grid driving circuit 1 is electrically connected with the grid lines positioned in the display area;
and the gate driving signal bus 2, the gate driving signal bus 2 is electrically connected with the gate driving circuit 1 (the connection relationship is not specifically shown in the figure), and is located on one side of the gate driving circuit 1 close to the display area a.
An array substrate provided in an embodiment of the present invention includes: the display area comprises at least one section of convex special-shaped display boundary, the non-display area comprises a special-shaped sub non-display area, and the convex special-shaped display boundary is positioned between the special-shaped sub non-display area and the display area; the special-shaped sub non-display area comprises a grid driving circuit, and the grid driving circuit is electrically connected with the grid lines positioned in the display area; the grid driving signal bus is arranged on one side of the grid driving circuit close to the display area, so that the area of the non-display area occupied by the grid driving signal bus is reduced, and the narrow frame design of the display panel is realized.
The area of the irregular sub-display region in the array substrate shown in fig. 2 occupying the array substrate is smaller than the area of the irregular sub-display region in the array substrate shown in fig. 3 occupying the array substrate, the array substrate shown in fig. 2 can be applied to a mobile phone, the array substrate shown in fig. 3 can be applied to an electronic watch, and the area of the irregular sub-display region can be adjusted correspondingly according to different application scenarios, which is not limited specifically herein.
Specifically, taking the total width of the gate driving signal bus as X, the gate driving signal bus includes a plurality of signal lines, when the gate driving signal bus is located on the side of the gate driving circuit away from the display area, the arc radius of one signal line in the gate driving signal bus that is close to the display area is Y, and when the gate driving signal bus is located on the side of the gate driving circuit that is close to the display area, the arc radius of one signal line in the gate driving signal bus that is close to the display area is Z for example, and as an example, when the radian of the convex special-shaped display boundary C is 90 °, then:
when the gate driving signal bus is located at the side of the gate driving circuit far away from the display region, the area of the non-display region occupied by the gate driving signal bus is S1Wherein, in the step (A),
when the gate driving signal bus is located at one side of the gate driving circuit close to the display region, the area of the non-display region occupied by the gate driving signal bus is S2Wherein, in the step (A),
the area of the non-display region occupied by the gate driving signal bus when the gate driving signal bus is located at the side of the gate driving circuit close to the display region is smaller than the area of the non-display region occupied by the gate driving signal bus when the gate driving signal bus is located at the side of the gate driving circuit far from the display region, and the area difference is Delta S, wherein,
wherein when X is 316 μm, Y is 7400 μm, and Z is 7060 μm, Δ S is 168680 μm2，S1＝3749674μm2In the array substrate provided by the embodiment of the invention, the gateWhen the gate driving signal bus is arranged on one side of the gate driving circuit close to the display area, the area is reduced by 4.5% relative to the area when the gate driving signal bus is arranged on one side of the gate driving circuit far away from the display area in the related art, and the narrow frame design of the display panel is favorably realized.
In addition, the outer edge of the non-display area of the display panel is also provided with frame sealing glue to seal the display panel, and the gate drive signal bus is arranged on one side of the gate drive circuit close to the display area, so that the area of the non-display area occupied by the gate drive signal bus is reduced, the light transmittance for curing the frame sealing glue is facilitated, and the frame sealing glue is better cured.
Optionally, in the array substrate provided in an embodiment of the present invention, as shown in fig. 5, fig. 5 is a partially enlarged schematic structural diagram of another convex shaped display boundary of the array substrate in fig. 2 or fig. 3; the gate driving circuit 1 comprises a plurality of shift registers SR, and all the shift registers SR are cascaded through a cascade wiring 3;
the cascade trace 3 is located between the gate driving signal bus 2 and the gate driving circuit 1.
Specifically, in the array substrate provided in the embodiment of the present invention, the cascade trace of each shift register of the gate driving circuit is disposed between the gate driving signal bus and the gate driving circuit, so that all the signal lines (including the cascade trace and the gate driving signal bus) are disposed on a side of the gate driving circuit close to the display region, and compared with the case that the cascade signal line is disposed on a side of the gate driving circuit far from the display region, the area of the non-display region occupied by the cascade trace can be reduced.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 7, fig. 7 is a schematic diagram of a shift register provided in the embodiment of the present invention; the shift register includes:
at least two grid line output tubes (M4-1 and M4-2), wherein the grid line output tubes (M4-1 and M4-2) are arranged in parallel.
Specifically, as shown in fig. 6, fig. 6 is a schematic diagram of a shift register in the related art, and includes a gate line output tube M4 connected to the signal output end OUT for providing gate line driving signals to corresponding gate lines; in the above array substrate provided by the embodiment of the invention, as shown in fig. 7, fig. 7 is a schematic diagram of a shift register provided by the embodiment of the invention, and includes two parallel gate output tubes M4-1 and M4-2, wherein the sum of the channel width-to-length ratios of M4-1 and M4-2 is similar to the channel width-to-length ratio of the gate output tube M4 in fig. 6. Because the size of the grid output tube in the shift register is larger than that of other transistors so as to ensure stable output, but the area occupied by the metal wire in the large-size grid output tube is also larger, which is not beneficial to the light transmission when the frame sealing glue is cured and influences the curing effect of the frame sealing glue, in order to solve the problems, the invention adopts two small-size grid output tubes (M4-1 and M4-2) connected in parallel to replace one large-size grid output tube M4, because the gap of the metal wire exists between the two small-size grid output tubes (M4-1 and M4-2) connected in parallel, which is beneficial to the light transmission, of course, three or more small-size grid output tubes connected in parallel can be used to replace one large-size grid output tube, and the specific number of the grid output tubes is selected according to the specific use condition, the area where the sealant is located overlaps the area where the gate line output lines (e.g., M4-1 and M4-2) are located, but is not particularly limited thereto.
The shift registers shown in fig. 6 and 7 have the same structure except for the difference between the gate output terminals, and specifically, the shift registers shown in fig. 6 and 7 further include:
an INPUT tube M0, a gate of the INPUT tube M0 is connected to the signal output terminal INPUT, a first pole of the INPUT tube M0 is connected to the first reference voltage signal terminal VREF1, and a second pole of the INPUT tube M0 is connected to the pull-up node P;
a first transistor M1, a gate of the first transistor M1 being connected to a first RESET signal terminal RESET1, a first pole of the first transistor M1 being connected to a second reference voltage signal terminal VREF2, and a second pole of the first transistor M1 being connected to a pull-up node P;
a second transistor M2, a gate of the second transistor M2 being connected to the pull-down node Q, a first pole of the second transistor M2 being connected to the third reference voltage signal terminal VREF3, a second pole of the second transistor M2 being connected to the pull-up node P;
a third transistor M3, a gate of the third transistor M3 being coupled to the pull-up node P, a first pole of the third transistor M3 being coupled to the third reference voltage signal terminal VREF3, a second pole of the third transistor M3 being coupled to the pull-down node Q;
a fifth transistor M5, a gate of the fifth transistor M5 being connected to the pull-down node Q, a first pole of the fifth transistor M5 being connected to the third reference voltage signal terminal VREF3, and a second pole of the fifth transistor M5 being connected to the signal output terminal OUT;
a sixth transistor M6, a gate of the sixth transistor M6 being connected to the first clock signal terminal CK, a first pole of the sixth transistor M6 being connected to the third reference voltage signal terminal VREF3, and a second pole of the sixth transistor M6 being connected to the signal output terminal OUT;
a seventh transistor M7, a gate of the seventh transistor M7 being connected to the second RESET signal terminal RESET2, a first pole of the seventh transistor M7 being connected to the third reference voltage signal terminal VREF3, and a second pole of the seventh transistor M7 being connected to the pull-up node P;
an eighth transistor M8, a gate of the eighth transistor M8 being connected to the second RESET signal terminal RESET2, a first pole of the eighth transistor M8 being connected to the third reference voltage signal terminal VREF3, and a second pole of the eighth transistor M8 being connected to the signal output terminal OUT;
a first capacitor C1, wherein a first pole of the first capacitor C1 is connected to the second clock signal terminal CKB, and a second pole of the first capacitor C1 is connected to the pull-down node Q;
and a second capacitor C2, a first pole of the second capacitor C2 being connected to the pull-up node P, and a second pole of the second capacitor C2 being connected to the signal output terminal OUT.
It should be noted that the structures and connection relationships of the shift register except for the gate output tubes are not limited to those shown in fig. 6 and 7, and the above embodiments are also applicable to any other structures of the shift register, and the specific structures of the shift register except for the gate output tubes are selected according to actual use conditions, and are not limited specifically here.
It should be noted that the gate line output tube may be located at a side close to the gate driving signal bus, or may be located at a side far from the gate driving signal bus, and the specific position thereof is selected according to the actual use situation, and is not limited herein.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 8 to 11, wherein fig. 8 is a schematic structural diagram of a gate output tube provided in the embodiment of the present invention, fig. 9 is a schematic structural diagram of another gate output tube provided in the embodiment of the present invention, fig. 10 is a schematic structural diagram of another gate output tube provided in the embodiment of the present invention, and fig. 11 is a schematic structural diagram of another gate output tube provided in the embodiment of the present invention; the array substrate further includes: the maximum size of any side boundary of the orthographic projection of the grid line output tube on the substrate is less than or equal to 45 micrometers.
Specifically, in the array substrate provided in the embodiment of the present invention, as shown in fig. 8 to 11, the gate line riser includes the gate electrode G, the source electrode S, the drain electrode D and the active layer B, however, there are various specific structures of the gate line riser, such as an "I" structure shown in fig. 8, a "U" structure shown in fig. 9, a "T" structure shown in fig. 10 and an "L" structure shown in fig. 11; no matter what kind of transistor the grid line output tubes are in, it is necessary to ensure that the maximum dimension (L1/L2) of the orthographic projection of the grid line output tubes on the substrate (i.e. the shading pattern formed by the grid line output tubes on the substrate, the pattern shown in fig. 8-11) on any side boundary is less than or equal to 45 micrometers, so that the gaps existing between two or more grid line output tubes can enable light to better penetrate through, so as to better cure the frame sealing adhesive, wherein the more the number of the grid line output tubes are arranged, the more the gaps existing between the grid line output tubes are, the more the curing of the frame sealing adhesive is facilitated, but the more the grid line output tubes are arranged, the more the wiring of the shift register is complicated, so the number of the grid line output tubes is moderate, the selection is performed according to comprehensive consideration in the actual use process, and no specific limitation is made herein.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 12 and 13, fig. 12 is a partially enlarged schematic structural diagram of a convex irregular-shaped display boundary of the array substrate shown in fig. 2 or 3, and fig. 13 is a schematic structural diagram of a gate line fan-out trace in the array substrate provided in the embodiment of the present invention; the array substrate further includes:
the grid line driving circuit comprises a plurality of grid fan-out wires, a grid driving circuit 1 and a grid line, wherein the grid fan-out wires are respectively electrically connected with the grid driving circuit;
the display area comprises a special-shaped sub-display area A1 and a rectangular sub-display area A2, and the special-shaped sub-display area A1 comprises a convex special-shaped display boundary C;
the plurality of gate lines include a first gate line 41 and a second gate line 42, the first gate line 41 is located in the special-shaped sub display region a1, the second gate line 42 is located in the rectangular sub display region a2, wherein the load of the first gate line 41 is smaller than that of the second gate line 42;
the plurality of gate fan-out traces include a first gate fan-out trace 51, the first gate fan-out trace 51 being electrically connected to the first gate line 41;
the first gate fan-out trace 51 intersects at least one gate drive signal bus 2 non-perpendicularly.
Specifically, in the array substrate provided in the embodiment of the present invention, due to the existence of the convex special-shaped display boundary, the display region includes the special-shaped sub-display region and the rectangular sub-display region, wherein the special-shaped sub-display region is smaller than the rectangular sub-display region in the extending direction of the gate line, so that the number of pixels driven by the gate line located in the special-shaped sub-display region is less than the number of pixels driven by the gate line located in the rectangular sub-display region, that is, the capacitance load connected to the gate line located in the special-shaped sub-display region is less than the capacitance load connected to the gate line located in the rectangular sub-display region, which may cause uneven display The capacitive load of the gate line is compensated by enabling the first gate fan-out routing to be at least vertically intersected with one gate driving signal bus, so that the uniformity of display is ensured.
It should be noted that the inclination degree of the first gate fan-out trace, that is, the degree of load compensation required by the first gate line connected to the first gate fan-out trace and the several gate driving signal buses are determined by the first gate line connected to the first gate fan-out trace, and the larger the load to be compensated is, the larger the inclination degree is, the more the number of lines which are intersected with the gate driving signal buses in a non-perpendicular manner is; the smaller the load to be compensated, the smaller the inclination thereof, and the fewer the number of bars that intersect the gate driving signal bus lines non-perpendicularly.
Specifically, in the array substrate provided in the embodiment of the present invention, as shown in fig. 14, fig. 14 is a schematic cross-sectional structure diagram of a transistor, a gate fan-out trace and a gate driving signal bus provided in the embodiment of the present invention; the first gate fan-out trace 51 and the second gate fan-out trace 52 are disposed in different layers from the gate line driving signal bus 2, wherein the first gate fan-out trace 51 and the second gate fan-out trace 52 may be disposed in the same layer as the source S and the drain D of the transistor in the shift register, and the gate driving signal bus 2 may be disposed in the same layer as the gate G of the transistor in the shift register, wherein the source S and the drain D are both connected to the active layer B in the transistor of the shift register.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 15 and fig. 16, fig. 15 is another schematic structural diagram of a gate line fan-out trace in the array substrate provided in the embodiment of the present invention, and fig. 16 is another schematic structural diagram of the gate line fan-out trace in the array substrate provided in the embodiment of the present invention; the first gate fan-out trace 51 intersects at least one gate driving signal bus 2 non-perpendicularly, and at the intersection, the first gate fan-out trace 51 has a first line width a, and outside the intersection, the first gate fan-out trace 51 has a second line width b, wherein the first line width a is greater than the second line width b.
Specifically, in the array substrate provided in the embodiment of the present invention, when the capacitive load of the first gate line cannot be well compensated in a non-perpendicular intersecting manner of the first gate fan-out trace and the gate driving signal bus, the capacitive load of the first gate line may be increased in a manner of increasing the width of the first gate fan-out trace at a non-perpendicular intersecting position of the first gate fan-out trace and the gate driving signal bus, that is, the capacitive load of the first gate line is compensated by increasing the facing area of the first gate fan-out trace and the gate driving signal bus.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 15 and 16, the first gate fan-out trace 51 intersects at least one gate driving signal bus 2 non-perpendicularly, and at the intersection, an extending direction of the first gate fan-out trace 51 is the same as an extending direction of the gate driving signal bus 2.
Specifically, in the array substrate provided in the embodiment of the present invention, at the non-perpendicular intersection of the first gate fan-out trace and the gate driving signal bus, the extending direction of the first gate fan-out trace is the same as the extending direction of the gate driving signal bus, and compared with the manner in which the first gate fan-out trace directly crosses the gate driving signal bus obliquely, the manner in which the extending direction of the first gate fan-out trace is the same as the extending direction of the gate driving signal bus increases the facing area of the first gate fan-out trace and the gate driving signal bus, and can perform better compensation on the capacitive load of the first gate line.
Specifically, in the array substrate provided in the embodiment of the present invention, as shown in fig. 15 and fig. 16, where the first gate fan-out trace 51 intersects the gate driving signal bus 2 non-perpendicularly, the shape of the first gate fan-out trace 51 may be a rectangle as shown in fig. 15 or a diamond as shown in fig. 16, but may also be any other shape, which is selected according to a specific use situation, and is not limited specifically herein.
Optionally, in the array substrate provided in the embodiment of the present invention, the gate driving signal bus includes:
one or more of a clock signal line, a reference voltage signal line, an initial signal line, and a reset signal line.
Specifically, in the array substrate provided in the embodiment of the present invention, as shown in fig. 17, fig. 17 is a schematic structural diagram of a gate driving circuit composed of a plurality of cascaded shift registers, where the gate driving circuit includes a plurality of cascaded shift registers: SR (1), SR (2) … SR (N) … SR (N-1), SR (N) (N shift registers, N is more than or equal to 1 and less than or equal to N); except for the first stage shift register SR (1), the signal output end output of each stage of shift register SR (n) is respectively connected with the reset signal end reset of the adjacent previous stage shift register SR (n-1); except for the last stage of shift register SR (N), the signal output terminals output of the shift registers SR (n) of each stage are respectively connected to the input signal terminals input of the next stage of shift register SR (n +1) adjacent thereto. The input signal terminal input of the first stage shift register SR (1) is connected to the frame start signal terminal STV, and the reset signal terminal reset of the last stage shift register SR (n) is connected to the frame end signal terminal Res.
As can be seen from fig. 17, the gate driving signal bus connected to the gate driving circuit includes clock signal lines CLK and CLKB, reference voltage signal lines V1-V3, initial signal line STV, reset signal line Res, and may also include other signal lines, such as touch control signal line SW, the first clock signal line CK is connected to the first clock signal terminal clk in each stage of the shift register, the second clock signal line CKB is connected to the second clock signal terminal clkb in each stage of the shift register, the first reference signal line V1 is connected to the first reference voltage signal terminal Vref1 in each stage of the shift register, the second reference signal line V2 is connected to the second reference voltage signal terminal Vref2 in each stage of the shift register, the third reference signal line V3 is connected to the third reference voltage signal terminal Vref3 in each stage of the shift register, and the touch control signal line SW is connected to the touch signal terminal SW in each stage of the shift register.
Based on the same inventive concept, an embodiment of the present invention further provides a display panel, as shown in fig. 18 and fig. 19, where fig. 18 is a schematic structural diagram of a liquid crystal display panel provided in an embodiment of the present invention, and fig. 19 is a schematic structural diagram of an electroluminescent display panel provided in an embodiment of the present invention; the display panel comprises any one of the array substrates provided by the embodiment of the invention.
The display panel may be a liquid crystal display panel as shown in fig. 18, and includes any one of the array substrate SUB1, the opposite substrate SUB2, the pixel electrode layer 61 located on the side of the array substrate SUB1 facing the opposite substrate SUB2, and the liquid crystal layer 62 disposed between the array substrate SUB1 and the opposite substrate SUB2 according to the embodiment of the present invention. Of course, the display panel may also be an organic light emitting display panel as shown in fig. 19, which includes any one of the array substrate SUB1, the opposite substrate SUB2, and the anode layer 71, the light emitting layer 72, and the cathode layer 73 sequentially arranged on the side of the array substrate SUB1 facing the opposite substrate SUB2 according to the embodiment of the present invention.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, as shown in fig. 20 and 21, fig. 20 is a schematic structural diagram of the display device provided in the embodiment of the present invention when the display device is a mobile phone, and fig. 21 is a schematic structural diagram of the display device provided in the embodiment of the present invention when the display device is an electronic watch; the display device comprises the display panel provided by the embodiment of the invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, an electronic watch, and the like. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.
The embodiment of the invention provides an array substrate, a display panel and a display device, wherein the array substrate comprises: the display area comprises at least one convex special-shaped display boundary, the non-display area comprises a special-shaped sub non-display area, and the convex special-shaped display boundary is positioned between the special-shaped sub non-display area and the display area; the special-shaped sub non-display area comprises a grid driving circuit, and the grid driving circuit is electrically connected with the grid lines in the display area; the grid driving signal bus is electrically connected with the grid driving circuit, and the area of a non-display area occupied by the grid driving signal bus is reduced in a mode that the grid driving signal bus is arranged on one side, close to the display area, of the grid driving circuit, so that the narrow frame design of the display panel is realized.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110589811.XA CN113325641B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN201810698770.6A CN108803172B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN202110589540.8A CN113325640B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
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| CN202110589540.8A Active CN113325640B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
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Families Citing this family (11)
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| CN113419368B (en) * | 2019-03-20 | 2022-05-10 | 厦门天马微电子有限公司 | Array substrate and display device |
| CN109856865A (en) * | 2019-04-03 | 2019-06-07 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN110297342B (en) * | 2019-06-28 | 2022-01-07 | 武汉天马微电子有限公司 | Display panel and display device |
| CN112652272B (en) | 2019-10-11 | 2022-04-26 | 合肥京东方卓印科技有限公司 | Array substrate, manufacturing method thereof, and display device |
| US12156442B2 (en) * | 2020-03-31 | 2024-11-26 | Beijing Boe Technology Development Co., Ltd. | Array substrate, display panel and display device |
| CN111583865B (en) | 2020-06-12 | 2021-11-26 | 京东方科技集团股份有限公司 | Display panel, display device and method for determining channel width-length ratio of switching device |
| EP4044163B1 (en) | 2020-06-18 | 2023-10-25 | BOE Technology Group Co., Ltd. | Display panel and display apparatus |
| WO2021253345A1 (en) * | 2020-06-18 | 2021-12-23 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display device |
| CN115731886A (en) * | 2021-08-27 | 2023-03-03 | 京东方科技集团股份有限公司 | Special-shaped display substrate and display device |
| CN115327824B (en) * | 2022-02-22 | 2024-07-30 | 北京京东方光电科技有限公司 | Array substrate, display panel and display device |
| CN115411081B (en) * | 2022-08-31 | 2025-11-21 | 武汉天马微电子有限公司 | Array substrate, display panel and display device |
Citations (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6078365A (en) * | 1996-01-25 | 2000-06-20 | Kabushiki Kaisha Toshiba | Active matrix liquid crystal panel having an active layer and an intervening layer formed of a common semiconductor film |
| KR100403940B1 (en) * | 1996-10-31 | 2003-12-18 | 삼성전자주식회사 | Contact structure of out lead bonding pad and fan out of LOC panel |
| CN1495700A (en) * | 2002-08-07 | 2004-05-12 | ���ǵ�����ʽ���� | Integrated circuits and displays comprising integrated circuits |
| CN1214282C (en) * | 1997-10-31 | 2005-08-10 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| CN101419349A (en) * | 2007-10-23 | 2009-04-29 | 爱普生映像元器件有限公司 | Electro-optical device |
| CN103309107A (en) * | 2013-05-13 | 2013-09-18 | 深圳市华星光电技术有限公司 | Fan-out line structure of array substrate and display panel |
| CN103487962A (en) * | 2007-04-27 | 2014-01-01 | Nlt科技股份有限公司 | Non-rectangular display apparatus |
| CN103913905A (en) * | 2012-12-31 | 2014-07-09 | 三星显示有限公司 | Display device |
| CN105158998A (en) * | 2015-09-14 | 2015-12-16 | 深圳市华星光电技术有限公司 | Liquid crystal display device and display panel thereof |
| CN106647071A (en) * | 2017-02-15 | 2017-05-10 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
| CN106711180A (en) * | 2016-12-29 | 2017-05-24 | 上海天马有机发光显示技术有限公司 | Display panel, display device and display panel manufacture method |
| CN106971696A (en) * | 2017-05-03 | 2017-07-21 | 昆山龙腾光电有限公司 | Display device, drive circuit and preparation method thereof |
| CN106991990A (en) * | 2017-05-27 | 2017-07-28 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN107039464A (en) * | 2016-12-23 | 2017-08-11 | 友达光电股份有限公司 | Wire structure and active element array substrate |
| CN107221536A (en) * | 2017-05-25 | 2017-09-29 | 上海天马微电子有限公司 | Array substrate, special-shaped display and display device |
| CN107479766A (en) * | 2017-09-30 | 2017-12-15 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN107561806A (en) * | 2017-09-29 | 2018-01-09 | 厦门天马微电子有限公司 | Array base palte and display panel |
| CN107564938A (en) * | 2016-07-01 | 2018-01-09 | 三星显示有限公司 | Display device |
| CN107643638A (en) * | 2017-10-18 | 2018-01-30 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN107703688A (en) * | 2017-09-28 | 2018-02-16 | 武汉天马微电子有限公司 | Array substrate and display device |
| CN107919090A (en) * | 2017-11-30 | 2018-04-17 | 武汉天马微电子有限公司 | Display panel and display device |
| US9960194B1 (en) * | 2016-10-31 | 2018-05-01 | Lg Display Co., Ltd. | Display device |
| CN207458545U (en) * | 2017-11-23 | 2018-06-05 | 昆山龙腾光电有限公司 | A kind of display panel and display device |
| CN108182921A (en) * | 2018-01-03 | 2018-06-19 | 上海中航光电子有限公司 | A kind of array substrate, display panel and display device |
Family Cites Families (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3579461B2 (en) * | 1993-10-15 | 2004-10-20 | 株式会社ルネサステクノロジ | Data processing system and data processing device |
| JPH08137443A (en) * | 1994-11-09 | 1996-05-31 | Sharp Corp | Image display device |
| JP4228248B2 (en) * | 1998-09-25 | 2009-02-25 | ソニー株式会社 | Method for manufacturing electro-optical device and method for manufacturing drive substrate for electro-optical device |
| JP2004004541A (en) * | 2002-03-22 | 2004-01-08 | Seiko Epson Corp | Electro-optical device, drive circuit for electro-optical device, and electronic apparatus |
| JP3960237B2 (en) * | 2003-02-24 | 2007-08-15 | 株式会社デンソー | EL display driving device and printer head of optical printer |
| JP3922227B2 (en) * | 2003-08-28 | 2007-05-30 | セイコーエプソン株式会社 | Display device |
| KR101019416B1 (en) * | 2004-06-29 | 2011-03-07 | 엘지디스플레이 주식회사 | Shift register and flat panel display device including the same |
| KR101143004B1 (en) * | 2005-06-13 | 2012-05-11 | 삼성전자주식회사 | Shift register and display device including shifter register |
| CN100565711C (en) * | 2006-02-23 | 2009-12-02 | 三菱电机株式会社 | Shift-register circuit and be provided with the image display device of this circuit |
| JP5128102B2 (en) * | 2006-02-23 | 2013-01-23 | 三菱電機株式会社 | Shift register circuit and image display apparatus including the same |
| JP2007317288A (en) * | 2006-05-25 | 2007-12-06 | Mitsubishi Electric Corp | Shift register circuit and image display apparatus including the same |
| KR101580897B1 (en) * | 2008-10-07 | 2015-12-30 | 삼성전자주식회사 | Display driver method thereof and device having the display driver |
| JP5210955B2 (en) * | 2009-04-21 | 2013-06-12 | 株式会社ジャパンディスプレイイースト | Gate signal line driving circuit and display device |
| CN102483889B (en) * | 2009-09-11 | 2014-09-03 | 夏普株式会社 | Active matrix substrate and active matrix display device |
| JP5385954B2 (en) * | 2010-10-29 | 2014-01-08 | 三星ディスプレイ株式會社 | Touch screen panel integrated liquid crystal display device and driving method thereof |
| CN201984789U (en) * | 2011-04-19 | 2011-09-21 | 京东方科技集团股份有限公司 | Array substrate row driving circuit, array substrate and liquid crystal display device |
| WO2013002229A1 (en) * | 2011-06-30 | 2013-01-03 | シャープ株式会社 | Shift register, scanning signal line drive circuit, display panel, and display device |
| KR101871993B1 (en) * | 2011-08-23 | 2018-06-28 | 삼성디스플레이 주식회사 | Display device |
| CN204577057U (en) * | 2012-10-05 | 2015-08-19 | 夏普株式会社 | Display device |
| JP6055089B2 (en) * | 2013-04-25 | 2016-12-27 | シャープ株式会社 | Display device |
| JP6315892B2 (en) * | 2013-05-15 | 2018-04-25 | 三菱電機株式会社 | LCD panel |
| CN103926769B (en) * | 2013-12-26 | 2016-08-24 | 上海天马微电子有限公司 | Array substrate, display panel and display |
| US9584111B2 (en) * | 2014-09-30 | 2017-02-28 | Apple Inc. | Systems and methods for improving energy efficiency of gate driver circuits |
| CN104483771B (en) * | 2014-10-28 | 2018-02-06 | 上海中航光电子有限公司 | A kind of tft array substrate, display panel and display device |
| KR102253529B1 (en) * | 2015-01-06 | 2021-05-18 | 삼성디스플레이 주식회사 | Display device and driving method thereof |
| JP2017021087A (en) * | 2015-07-07 | 2017-01-26 | パナソニック液晶ディスプレイ株式会社 | Drive circuit and display |
| CN105139797A (en) * | 2015-10-15 | 2015-12-09 | 京东方科技集团股份有限公司 | Special-shaped display panel and display device |
| JP6539567B2 (en) * | 2015-10-30 | 2019-07-03 | 株式会社ジャパンディスプレイ | Display device |
| CN105334651B (en) * | 2015-12-07 | 2019-03-26 | 深圳市华星光电技术有限公司 | Liquid crystal display, display device and public electrode voltages adjusting method |
| CN105609037B (en) * | 2015-12-31 | 2019-07-09 | 上海中航光电子有限公司 | A kind of array substrate, touch-control display panel and touch control display apparatus |
| JP6689088B2 (en) * | 2016-02-08 | 2020-04-28 | 株式会社ジャパンディスプレイ | Display device |
| JP6806502B2 (en) * | 2016-09-08 | 2021-01-06 | 株式会社ジャパンディスプレイ | Display device |
| CN206421362U (en) * | 2017-01-10 | 2017-08-18 | 上海中航光电子有限公司 | A kind of touch-control display panel and touch control display apparatus |
| CN106547127B (en) * | 2017-01-16 | 2019-10-25 | 上海天马微电子有限公司 | Array substrate, liquid crystal display panel and display device |
| CN107331297B (en) * | 2017-06-28 | 2019-09-24 | 厦门天马微电子有限公司 | A kind of abnormity display panel and display device |
| CN107561799B (en) * | 2017-08-25 | 2021-07-20 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN107644614B (en) * | 2017-10-26 | 2019-12-03 | 上海中航光电子有限公司 | A kind of array substrate, display panel and display device |
| CN107991799B (en) * | 2018-01-02 | 2021-01-29 | 上海中航光电子有限公司 | Display panel and display device |
-
2018
- 2018-06-29 CN CN202110589812.4A patent/CN113325642B/en active Active
- 2018-06-29 CN CN201810698770.6A patent/CN108803172B/en active Active
- 2018-06-29 CN CN202110589540.8A patent/CN113325640B/en active Active
- 2018-06-29 CN CN202110589811.XA patent/CN113325641B/en active Active
Patent Citations (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6078365A (en) * | 1996-01-25 | 2000-06-20 | Kabushiki Kaisha Toshiba | Active matrix liquid crystal panel having an active layer and an intervening layer formed of a common semiconductor film |
| KR100403940B1 (en) * | 1996-10-31 | 2003-12-18 | 삼성전자주식회사 | Contact structure of out lead bonding pad and fan out of LOC panel |
| CN1214282C (en) * | 1997-10-31 | 2005-08-10 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| CN1495700A (en) * | 2002-08-07 | 2004-05-12 | ���ǵ�����ʽ���� | Integrated circuits and displays comprising integrated circuits |
| CN103487962A (en) * | 2007-04-27 | 2014-01-01 | Nlt科技股份有限公司 | Non-rectangular display apparatus |
| CN101419349A (en) * | 2007-10-23 | 2009-04-29 | 爱普生映像元器件有限公司 | Electro-optical device |
| CN103913905A (en) * | 2012-12-31 | 2014-07-09 | 三星显示有限公司 | Display device |
| CN103309107A (en) * | 2013-05-13 | 2013-09-18 | 深圳市华星光电技术有限公司 | Fan-out line structure of array substrate and display panel |
| CN105158998A (en) * | 2015-09-14 | 2015-12-16 | 深圳市华星光电技术有限公司 | Liquid crystal display device and display panel thereof |
| CN107564938A (en) * | 2016-07-01 | 2018-01-09 | 三星显示有限公司 | Display device |
| US9960194B1 (en) * | 2016-10-31 | 2018-05-01 | Lg Display Co., Ltd. | Display device |
| CN107039464A (en) * | 2016-12-23 | 2017-08-11 | 友达光电股份有限公司 | Wire structure and active element array substrate |
| CN106711180A (en) * | 2016-12-29 | 2017-05-24 | 上海天马有机发光显示技术有限公司 | Display panel, display device and display panel manufacture method |
| CN106647071A (en) * | 2017-02-15 | 2017-05-10 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
| CN106971696A (en) * | 2017-05-03 | 2017-07-21 | 昆山龙腾光电有限公司 | Display device, drive circuit and preparation method thereof |
| CN107221536A (en) * | 2017-05-25 | 2017-09-29 | 上海天马微电子有限公司 | Array substrate, special-shaped display and display device |
| CN106991990A (en) * | 2017-05-27 | 2017-07-28 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN107703688A (en) * | 2017-09-28 | 2018-02-16 | 武汉天马微电子有限公司 | Array substrate and display device |
| CN107561806A (en) * | 2017-09-29 | 2018-01-09 | 厦门天马微电子有限公司 | Array base palte and display panel |
| CN107479766A (en) * | 2017-09-30 | 2017-12-15 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN107643638A (en) * | 2017-10-18 | 2018-01-30 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN207458545U (en) * | 2017-11-23 | 2018-06-05 | 昆山龙腾光电有限公司 | A kind of display panel and display device |
| CN107919090A (en) * | 2017-11-30 | 2018-04-17 | 武汉天马微电子有限公司 | Display panel and display device |
| CN108182921A (en) * | 2018-01-03 | 2018-06-19 | 上海中航光电子有限公司 | A kind of array substrate, display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113325640B (en) | 2022-12-30 |
| CN113325641B (en) | 2022-12-30 |
| CN113325642A (en) | 2021-08-31 |
| CN113325641A (en) | 2021-08-31 |
| CN108803172A (en) | 2018-11-13 |
| CN113325642B (en) | 2022-12-30 |
| CN113325640A (en) | 2021-08-31 |
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