CN111816227A - Semiconductor memory device with a plurality of memory cells - Google Patents
Semiconductor memory device with a plurality of memory cells Download PDFInfo
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- CN111816227A CN111816227A CN202010541595.7A CN202010541595A CN111816227A CN 111816227 A CN111816227 A CN 111816227A CN 202010541595 A CN202010541595 A CN 202010541595A CN 111816227 A CN111816227 A CN 111816227A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 8
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- 101001105315 Bacillus subtilis (strain 168) 50S ribosomal protein L17 Proteins 0.000 description 2
- 101000682328 Bacillus subtilis (strain 168) 50S ribosomal protein L18 Proteins 0.000 description 2
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- G—PHYSICS
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- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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Abstract
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a semiconductor memory device. The semiconductor memory device includes: the memory array comprises a plurality of rows of memory chip tuples, each row of memory chip tuples comprises at least one row of memory chip elements, and a group of bit lines are led out of one row of memory chip elements; the first column selection unit is positioned at the first side of the storage array; the second column selection unit is positioned on a second side opposite to the first side; each row of memory slice tuples are sequentially and alternately connected to the first row of selection units and the second row of selection units according to the groups through corresponding bit lines; the memory slice tuple connected to the first row of the selection units is connected to the corresponding interface of the first input/output circuit through the first row of the selection units; and the memory slice tuples connected to the second column selection unit are connected to the corresponding interface of the second input/output circuit through the second column selection unit.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a semiconductor memory device.
Background
With the continuous development of integrated circuit manufacturing technology, semiconductor memory chips are achieving higher speeds and integration. Manufacturers of memory chips are striving to improve the design and manufacture of memory cells and peripheral circuits connected to the memory cells by reducing the size of the memory chips. The circuit line routing technology in the peripheral circuit region has an important influence on the level of miniaturization of integrated circuits.
In the related art, a semiconductor memory device includes a memory array, a row decoding unit, a column decoding unit, and an input-output circuit; the bit lines of the memory array are distributed in an upper and lower odd-even order according to the serial numbers, namely, the bit lines with the serial numbers being odd are upwards connected with the column decoding units, and the bit lines with the serial numbers being even are downwards connected with the column decoding units.
The column decoding unit is also required to be connected with an input/output circuit, so that the bit lines are correspondingly distributed to different interfaces, and the corresponding bit lines can be gated when the column decoding unit receives a column selection signal, so that a signal path is formed between the corresponding interface and the gated bit lines. However, the above-described semiconductor memory device in the related art has a bit line wiring structure such that the column decoding unit has a problem of line waste when the bit lines are correspondingly allocated to different interfaces.
Disclosure of Invention
The invention provides a semiconductor memory device which can solve the problem of data line lane waste in the related art.
A semiconductor memory device, the semiconductor memory device comprising:
the memory array comprises a plurality of rows of memory chip tuples, each row of memory chip tuples comprises at least one row of memory chip elements, and a group of bit lines are led out of one row of memory chip elements;
a first column selection unit located at a first side of the memory array;
a second column selection unit located at a second side opposite to the first side;
each row of the memory slice tuples are sequentially and alternately connected to the first row selection unit and the second row selection unit according to the group through corresponding bit lines; the memory slice group connected to the first column of menu elements is connected to an interface corresponding to a first input/output circuit through the first column of menu elements; and the memory slice tuples connected to the second column selection unit are connected to the corresponding interface of the second input/output circuit through the second column selection unit.
Optionally, the semiconductor memory device includes a plurality of interfaces arranged in order; the first input/output circuit comprises a plurality of interfaces with odd serial numbers, and the second input/output circuit comprises a plurality of interfaces with even serial numbers.
Optionally, the first column selection unit and the second column selection unit each include a plurality of bit line selection switches;
one end of each bit line selection switch is correspondingly connected with one bit line, the other end of each bit line selection switch is connected with the corresponding interface, and each bit line selection switch further comprises a control end capable of receiving a bit line selection signal.
Alternatively, the first column selection unit and the second column selection unit may be capable of selecting the corresponding bit lines by a bit line selection signal.
Optionally, the bit line selection switches of a column of the memory slice tuples are connected, and the other ends of the bit line selection switches are connected to form a common node, and the interface is connected to the corresponding common node.
Optionally, a column of the memory chips comprises at least two columns of memory cells, and each column of the memory cells comprises a plurality of rows of memory cells.
Optionally, the semiconductor memory device further includes a row selection unit; the row selection unit comprises a plurality of word lines, and one word line is correspondingly connected with one row of storage bit cells in the storage array and is used for selecting the row where the corresponding storage bit cell is located.
The technical scheme of the invention at least comprises the following advantages: the semiconductor memory device can save the wire path of the data wire under the condition of ensuring the connection of the peripheral circuit
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a semiconductor memory device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of bit line, column select unit and input/output circuit connections provided by an embodiment of the present application;
FIG. 3 is a schematic diagram of a first column selection unit and a first input/output circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a semiconductor memory device in the related art.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
An embodiment of the present application provides a semiconductor memory device including: the memory array comprises a plurality of rows of memory slice tuples, each row of memory slice tuples comprises at least one row of memory slice elements, and one row of memory slice elements leads out a group of bit lines.
A first column selection unit located at a first side of the memory array.
A second column selection unit located at a second side opposite to the first side.
Each memory slice tuple is sequentially and alternately connected to the first row selection unit and the second row selection unit according to the group through the corresponding bit line; the memory slice group connected to the first row of the selection units is connected to the corresponding interface of the first input/output circuit through the first row of the selection units; the memory slice tuple connected to the second column selection unit is connected to the corresponding interface of the second input/output circuit through the second column selection unit.
Referring to fig. 1, which shows a schematic diagram of a semiconductor memory device provided by an embodiment of the present application, as shown in fig. 1, the semiconductor memory device includes:
the memory array 100 includes a plurality of rows of memory slice groups, each row of the memory slice group includes two rows of memory slices, one row of the memory slices leads to a group of bit lines, and one group of the bit lines has three bit lines. Taking the first memory slice group 110 as an example, the first memory slice group 110 includes two columns of memory slices, which are a first memory slice 111 and a second memory slice 112.
The first memory chip 111 includes a row of first memory cells 1111 and a row of second memory cells 1112, and each of the first memory cells 1111 and the second memory cells 1112 includes a plurality of rows of memory bits. The first memory chip cell 111 leads to a first bit line BL1, a second bit line BL2, and a third bit line BL 3; the first memory cell 1111 is connected to a first bit line BL1 and a second bit line BL2, and the second memory cell 1112 is connected to a second bit line BL2 and a third bit line BL 3; the first memory cell 1111 and the second memory cell 1112 share the second bit line BL 2.
With continued reference to FIG. 1, taking as an example the first memory bit M1 of the first memory cell 1111 and the second memory cell M2 of the second memory cell 1112, the first memory bit M1 and the second memory cell M2 each include a first storage bit C1 and a second storage bit C2, the first storage bit C1 of the first memory bit M1 is connected to the first bit line BL1, and the second storage bit C2 of the first memory bit M1 is connected to the second bit line BL 2; first memory bit C1 of second memory cell M2 is coupled to third bit line BL3, second memory bit C2 of second memory cell M2 is coupled to second bit line BL2, and first memory bit M1 and second memory cell M2 are commonly coupled to second bit line BL 2.
With continued reference to fig. 1, the second memory chip 112 also includes two columns of memory cells, and the bit lines from the second memory chip 112 are bit lines BL4, BL5, and BL6, respectively, wherein the bit line BL5 is a common bit line for the two columns of memory cells of the second memory chip 112.
It is understood that the minimum unit of the memory array 100 is a memory bit, and the memory array 100 shown in fig. 1 includes memory bits arranged in rows and columns, each row of memory bits forms a row of memory cells, each two rows of memory cells forms a row of memory chips, and each two columns of memory chips forms a column of memory chip groups.
The semiconductor memory device further includes a row selection unit 400, wherein the row selection unit 400 includes a plurality of word lines, such as word lines WL1, WL2, WL3, and wl4.
In the present embodiment, the semiconductor memory device includes a plurality of interfaces arranged in order, I/01, I/02, I/03, I/04, I/05, I/06 as shown in fig. 1; the first input/output circuit 310 includes a plurality of interfaces with odd numbers, such as I/01, I/03, I/05 shown in fig. 1, and the second input/output circuit 320 includes a plurality of interfaces with even numbers, such as I/02, I/04, I/06 shown in fig. 1.
The first row of cell units 210 is located at the lower side of the memory array 100, and the second row of cell units 220 is located at the upper side of the memory array 100, i.e. the lower side of the memory array 100 is the first side and the upper side is the second side in this embodiment.
The memory slice tuples are arranged in sequence and comprise a first memory slice tuple, a second memory slice tuple, a third memory slice tuple, a fourth memory slice tuple, a fifth memory slice tuple, a sixth memory slice tuple and the like which are arranged in sequence. The bit lines in each memory slice tuple are connected to the interface of the corresponding serial number.
With continued reference to FIG. 1, the bit lines BL1, BL2, BL3, BL4, BL5, and BL6 in the first memory slice group 110 are all connected to the first column of single cells 210 and connected to the interface I/O1 of the first input/output circuit 310 through the first column of single cells 210. The bit lines BL7, BL8, BL9, BL10, BL11 and BL12 in the second group of memory slices 120 are all connected to the second column of selection cells 220 and to the interface I/O2 of the second input/output circuit 320 through the second column of selection cells 220, and so on (not shown in the figure), the bit line in the third group of memory slices is connected to the interface I/O3 of the first input/output circuit through the first column of selection cells, the bit line in the fourth group of memory slices is connected to the interface I/O4 of the second input/output circuit through the second column of selection cells, the bit line in the fifth group of memory slices is connected to the interface I/O5 of the first input/output circuit through the first column of selection cells, the bit line in the sixth group of memory slices is connected to the interface I/O6 of the second input/output circuit through the second column of selection cells, and so on.
Referring to fig. 2, a schematic diagram of the connections of the bit lines, the column selection units and the input/output circuits provided by the embodiment of the present application is shown.
As shown in fig. 2, the memory array is divided into several columns of memory slice tuples from left to right, and each column of memory slice tuple includes six bit lines; the first column selection unit and the first input/output circuit are positioned below the storage array, the second column selection unit and the second input/output circuit are positioned above the storage array, the first column selection unit is connected with the first input/output circuit, the second column selection unit is connected with the second input/output circuit, the first input/output circuit comprises a plurality of interfaces with odd serial numbers, and the second input/output circuit comprises a plurality of interfaces with even serial numbers; optionally, the first input/output circuit includes a plurality of interfaces with even numbers, and the second input/output circuit includes a plurality of interfaces with odd numbers. And the six bit lines of each row of memory chip groups are sequentially and alternately connected with the first row selection unit and the second row selection unit from left to right according to the sequence of the memory chip groups, so that the two adjacent rows of memory chip groups are respectively connected with the first row selection unit and the second row selection unit.
With continued reference to fig. 2, the plurality of columns of slice tuples includes a first slice tuple 110, a second slice tuple 120, a third slice tuple 130, a fourth slice tuple 140, and the like arranged from left to right. The first memory slice tuple 110 includes six bit lines, which are bit lines BL1, BL2, BL3, BL4, BL5, and BL 6; the second memory slice group 120 includes six bit lines, which are bit lines BL7, BL8, BL9, BL10, BL11, and BL 12; the third memory slice tuple 130 includes six bit lines, which are bit lines BL13, BL14, BL15, BL16, BL17, and BL 18; the fourth memory slice group 140 includes six bit lines, which are bit lines BL19, BL20, BL21, BL22, BL23, and BL 24. Wherein, six bit lines of the first slice group 110 and six bit lines of the third slice group 130 are connected to the first column of menu units 210; the six bit lines of the second memory slice group 120 and the six bit lines of the fourth memory slice group 140 are connected down to the second column select unit 220.
In this embodiment, each of the first column selection unit and the second column selection unit includes a plurality of bit line selection switches;
one end of each bit line selection switch is correspondingly connected with one bit line, the other end of each bit line selection switch is connected with the corresponding interface, and each bit line selection switch further comprises a control end capable of receiving a bit line selection signal.
The first column selection unit and the second column selection unit are capable of selecting corresponding bit lines by a bit line selection signal.
And the other ends of the bit line selection switches are connected to form a common node, and the interfaces are connected with the corresponding common node.
Referring to fig. 3, a schematic diagram of connection between a first column selection unit and a first input/output circuit provided in an embodiment of the present application is shown.
As shown in fig. 3, only the bit lines of the first slice group 110 and the third slice group 130 are shown in fig. 3, and the bit lines of the other slice groups are omitted.
The first memory slice tuple 110 includes six bit lines, which are bit lines BL1, BL2, BL3, BL4, BL5, and BL6, the first column selection unit 210 includes a first bit line selection switch group 211 connected to the bit line of the first memory slice tuple 110, the first bit line selection switch group 211 includes bit line selection switches C1, C2, C3, C4, C5, and C6, the bit line selection switches include first connection terminals, second connection terminals, and control terminals, and the control terminals of the bit line selection switches are used for connecting bit line selection signals to select corresponding bit lines; in the first bit line selection switch group 211, a first connection terminal of each bit line selection switch is correspondingly connected to each bit line of the first memory slice group 110, and a second connection terminal is connected to the first interface I/O1 of the first input/output circuit 310.
The third memory slice group 130 in fig. 3 includes six bit lines, which are bit lines BL13, BL14, BL15, BL16, BL17, and BL18, the first column selection unit 210 includes a third bit line selection switch group 213 connected to the bit line of the third memory slice group 130, the third bit line selection switch group 213 includes bit line selection switches C13, C14, C15, C16, C17, and C18, the bit line selection switches each include a first connection terminal, a second connection terminal, and a control terminal, and the control terminal of the bit line selection switch is used for connecting a bit line selection signal to select a corresponding bit line; in the third bit line selection switch group 213, the first connection terminal of each bit line selection switch is connected to each bit line of the third memory slice group 130, and the second connection terminal is connected to the third interface I/O3 of the first input/output circuit 310.
It should be noted that, for the even-numbered selection switch groups such as the second bit line selection switch group and the fourth bit line selection switch group, which are located in the second row selection unit, the structure thereof can be referred to fig. 3, and will not be described herein.
Fig. 4 is a schematic diagram of a semiconductor memory device in the related art. As shown in fig. 4, in the related art, the semiconductor memory device includes a memory array, a row decoding unit, a column decoding unit, and an input-output circuit; the bit lines of the memory array are distributed in an upper and lower odd-even order according to the serial numbers, namely, the bit lines with the serial numbers being odd are upwards connected with the column decoding units, and the bit lines with the serial numbers being even are downwards connected with the column decoding units.
The column decoding unit includes a plurality of column gating units, such as a first column gating unit and an x-th column gating unit. The bit lines of the memory array are distributed in an upper and lower odd-even order according to the serial numbers, namely, the bit lines with the serial numbers being odd are upwards connected with the column decoding units, and the bit lines with the serial numbers being even are downwards connected with the column decoding units.
As shown in fig. 4, a wiring structure of the bit line BL1 to the bit line BL12 is taken as an example. Six bit lines of bit lines BL1, BL3, BL5, BL7, BL9 and BL11 are connected with the first column of gating cells downwards, six bit lines of bit lines BL2, BL4, BL6, BL8, BL10 and BL12 are connected with the first column of gating cells upwards, wherein the bit lines BL1, BL2 and BL3, the bit lines BL4, BL5 and BL6, the bit lines BL7, BL8 and BL9, the bit lines BL10, BL11 and BL12 are respectively connected with a column of memory chips correspondingly, and the bit lines BL1 to BL12 are connected with the first interface I/O1 of the input and output circuit through the first column of gating cells.
Therefore, the column decoding unit is connected with the input and output circuit, correspondingly distributes the bit lines to different interfaces, and can gate the corresponding bit lines when the column decoding unit receives the column selection signal, so that a signal path is formed between the corresponding interface and the gated bit lines. However, the above-described semiconductor memory device in the related art has a problem that the bit line wiring structure thereof causes the column decoding unit to waste the data line lanes connecting the interfaces when the bit lines are correspondingly allocated to different interfaces.
Comparing the semiconductor memory device provided by the embodiment of the present application shown in fig. 1 to 3 with the semiconductor memory device in the related art shown in fig. 4, it can be seen that the semiconductor memory device provided by the embodiment of the present application can save lanes of data lines while ensuring the connection of peripheral circuits.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (7)
1. A semiconductor memory device, characterized in that the semiconductor memory device comprises:
the memory array comprises a plurality of rows of memory chip tuples, each row of memory chip tuples comprises at least one row of memory chip elements, and a group of bit lines are led out of one row of memory chip elements;
a first column selection unit located at a first side of the memory array;
a second column selection unit located at a second side opposite to the first side;
each row of the memory slice tuples are sequentially and alternately connected to the first row selection unit and the second row selection unit according to the group through corresponding bit lines; the memory slice group connected to the first column of menu elements is connected to an interface corresponding to a first input/output circuit through the first column of menu elements; and the memory slice tuples connected to the second column selection unit are connected to the corresponding interface of the second input/output circuit through the second column selection unit.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device includes a plurality of interfaces arranged in order; the first input/output circuit comprises a plurality of interfaces with odd serial numbers, and the second input/output circuit comprises a plurality of interfaces with even serial numbers.
3. The semiconductor memory device according to claim 1, wherein the first column selection unit and the second column selection unit each include a plurality of bit line selection switches;
one end of each bit line selection switch is correspondingly connected with one bit line, the other end of each bit line selection switch is connected with the corresponding interface, and each bit line selection switch further comprises a control end capable of receiving a bit line selection signal.
4. The semiconductor memory device according to claim 3, wherein the first column selection unit and the second column selection unit are capable of selecting the corresponding bit lines by a bit line selection signal.
5. The semiconductor memory device of claim 3, wherein each bit line select switch connected to a column of the memory slice groups has another end connected to form a common node, and the interface connects the corresponding common nodes.
6. The semiconductor memory device of claim 1, wherein a column of the memory chips comprises at least two columns of memory cells, each column of the memory cells comprising a plurality of rows of memory bits.
7. The semiconductor memory device according to claim 6, further comprising a row selection unit; the row selection unit comprises a plurality of word lines, and one word line is correspondingly connected with one row of storage bit cells in the storage array and is used for selecting the row where the corresponding storage bit cell is located.
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| CN202010541595.7A CN111816227A (en) | 2020-06-15 | 2020-06-15 | Semiconductor memory device with a plurality of memory cells |
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| CN202010541595.7A CN111816227A (en) | 2020-06-15 | 2020-06-15 | Semiconductor memory device with a plurality of memory cells |
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Application publication date: 20201023 |
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| RJ01 | Rejection of invention patent application after publication |