CN111403407A - Three-dimensional memory and its control method, control device and storage medium - Google Patents

Abstract

The present invention provides a three-dimensional memory, a control method, a control device and a storage medium thereof. The three-dimensional memory includes a semiconductor substrate; a semiconductor material layer, located on the semiconductor substrate; a stack structure, located on the semiconductor material layer, and the The stacked structure includes alternately stacked dielectric layers and gate layers; memory strings pass through the stacked structure and the semiconductor material layers; wherein, at least two gate layers at the bottom of the stacked structure serve as the bottom Select the gate layer of the tube. By using the present invention, by designing and using multi-layer bottom selection tubes in the three-dimensional memory, the closing and opening operations of the lower selection tubes can be better realized during data operations (including programming, reading and parameter operations), and the three-dimensional memory is improved. The overall performance of the memory.

Description

Three-dimensional memory and its control method, control device and storage medium

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a three-dimensional memory and its control method, control device and storage medium.

Background technique

In the traditional three-dimensional memory, the silicon selective epitaxial growth (Silicon Epitaxy Growth, SEG for short) technology is generally used to form a single crystal silicon epitaxial layer connected to the channel layer at the bottom of the channel hole. The P well (or N well) in the semiconductor substrate together forms the L-type channel of the bottom selection transistor, that is, in the SEG technology, the bottom selection transistor is composed of an L-type SEG transistor, and the L-type channel of the bottom selection transistor BSG The type channel is single crystal silicon with less defect states, and the bottom selection transistor BSG of the single layer can realize normal turn-off and turn-on operations.

However, as the number of gate layers in three-dimensional memory increases, for example, when the number of layers is greater than 96, the SONO (silicon-silicon oxide-silicon nitride-silicon oxide) etching process window combined with silicon selective epitaxial growth SEG becomes more and more More and more marginalized (Margin), can not meet the process requirements, at this time sidewall polysilicon epitaxial growth (Sidewall SEG, referred to as SWS) technology is introduced, in SWS, all used are more defect state silicon channel, in the three-dimensional memory. When performing data operations (including programming, reading, and parameter operations), it is difficult for the single-layer bottom selection transistor BSG to perform normal turn-off and turn-on operations, which will affect the storage performance of the three-dimensional memory.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional memory and its control method, control device and storage medium, which are used to solve the three-dimensional memory using SWS technology in the prior art. The technical problem of turning off and turning on is not well implemented.

In order to achieve the above object and other related objects, the present invention provides a three-dimensional memory, the three-dimensional memory includes:

semiconductor substrate;

a semiconductor material layer on the semiconductor substrate;

a stacked structure on the semiconductor material layer, the stacked structure including alternately stacked dielectric layers and gate layers;

memory strings passing through the stack structure and the layers of semiconductor material;

Wherein, at least two of the gate layers at the bottom of the stacked structure serve as gate layers of the bottom selection transistor.

In an optional embodiment, the memory string includes functional sidewall layers and channel layers sequentially disposed in a radially inward direction.

In an optional embodiment, the memory string further includes a high-k dielectric layer, and the high-k dielectric layer surrounds the functional sidewall layer.

In an optional embodiment, the functional sidewall layer includes:

a barrier layer formed on the sidewall surface of the channel hole;

a storage layer formed on the surface of the barrier layer; and

A tunneling layer is formed on the surface of the storage layer.

In an optional embodiment, the three-dimensional memory structure further includes a filling insulating layer, and the filling insulating layer is formed on the surface of the channel layer and filled in the channel hole.

In an optional embodiment, an insulating gap is further formed in the filling insulating layer.

In an optional embodiment, the semiconductor material layer is located at the periphery of the channel layer and is in contact with the sidewall of the channel layer.

In an optional embodiment, the material of the semiconductor material layer includes polysilicon.

In an optional embodiment, the three-dimensional memory further includes a dummy gate layer located between the stacked structure and the semiconductor material layer, and the memory string passes through the dummy gate layer.

In an optional embodiment, the three-dimensional memory includes a three-dimensional NAND-type memory.

In an optional embodiment, the gate layers of all the bottom selection transistors are connected in common.

In order to achieve the above purpose and other related purposes, the present invention also provides a control method for the three-dimensional memory described in any one of the above, the control method comprising:

The semiconductor substrate of the three-dimensional memory is provided with a doped well, and the doped well is connected to the storage string through the semiconductor material layer; the three-dimensional memory control method includes an erasing operation, and when the erasing operation is performed :

applying an erase voltage to the doped well of the semiconductor substrate of the three-dimensional memory;

After applying the erasing voltage for a preset period of time, a turn-on voltage is applied to the gate layers of all bottom selection transistors of the three-dimensional memory; wherein, within the preset period of time, all of the three-dimensional memory The gate voltage on the gate layer of the bottom select transistor is zero.

In an optional embodiment, the erase voltage is greater than the turn-on voltage.

In an optional embodiment, the doped well includes a P-well or an N-well.

In an optional embodiment, the three-dimensional memory control method further includes a programming operation. During the programming operation, the gate voltages of the gate layers of all the bottom selection transistors of the three-dimensional memory are zero, so as to use All of the bottom selection tubes of the three-dimensional memory are turned off.

In an optional embodiment, the three-dimensional memory control method further includes a data reading operation, and during data reading, a turn-on voltage is simultaneously applied to the gate layers of all the bottom selection transistors of the three-dimensional memory. .

In order to achieve the above object and other related objects, the present invention also provides a control device, the control device includes:

a communicator for communicating with the outside world;

memory for storing computer programs;

The processor is connected to the communicator and the memory, and is used for running the computer program to execute the three-dimensional memory control method described in any one of the above.

To achieve the above and other related purposes, the present invention also provides a computer-readable storage medium storing a computer program; the computer program executes any of the three-dimensional memory control methods described above when running.

By using the present invention, by designing and using the multi-layer bottom selection tube BSG in the three-dimensional memory, the turn-off and turn-on operations of the lower selection tube can be better realized when performing data operations (including programming, reading and parameter operations), thereby improving the The overall performance of the 3D memory;

During erasing, better erasing can be achieved through the siphon effect generated by the time delay between the erasing voltage of the P well (it can also be the N well) and the gate voltage of the bottom selection transistor BSG, while the multi-layer bottom selection transistor BSG It can be turned off more effectively, and effectively prevent the impact of the upward hole during the delay period on the erasing efficiency;

When programming a selected memory cell, the good turn-off effect of the multi-layer bottom selection transistor BSG can reduce the gate disturbance (Disturbance) to other unselected memory cells located on the same word line as the selected cell. ), and at the same time, the multi-layer bottom selection tube BSG can also be fully opened during reading, which hardly affects the reading performance of the three-dimensional memory.

Description of drawings

FIG. 1 shows a schematic structural diagram of an exemplary three-dimensional memory.

FIG. 2 is a schematic diagram showing the structure of the three-dimensional memory of the present invention.

FIG. 3 shows a partial circuit diagram of an equivalent circuit of one memory block of the three-dimensional memory of FIG. 2 .

FIG. 4 is a schematic diagram illustrating the implementation of the P-well voltage and the gate voltage of the bottom selection transistor during the erasing operation in the control method of the three-dimensional memory of the present invention.

FIG. 5 shows a partial circuit diagram of an equivalent circuit of one memory block of the three-dimensional memory of FIG. 2 during programming.

FIG. 6 shows a partial circuit diagram of an equivalent circuit of one memory block of the three-dimensional memory of FIG. 1 when programming.

FIG. 7 is a block diagram showing the structure of the control device of the three-dimensional memory of the present invention.

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual production.

For convenience of description, spatially relative terms such as "below," "below," "below," "below," "above," "on," etc. may be used herein to describe an element shown in the figures or The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures. In addition, when a layer is referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the context of this application, descriptions of structures where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include further features formed over the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact. It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the diagrams only show the components related to the present invention rather than the number, shape and size of the components in actual implementation. For drawing, the shape, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the component layout shape may also be more complicated.

FIG. 1 shows a schematic diagram of a partial structure of a three-dimensional memory. As shown in FIG. 1, the three-dimensional memory structure includes: a semiconductor substrate 110, a semiconductor material layer 190, a stack structure 130 and a memory string (only shown in FIG. 1 ). In the case of having one memory string, in practice it generally includes multiple ones. The semiconductor material layer 190 is located between the semiconductor substrate 110 and the stacked structure 130 ; the stacked structure 130 is formed on the semiconductor substrate 110 and a channel hole is formed in the stack structure 130, wherein the stack structure 130 includes alternately stacked gate layers 132 and insulating dielectric layers 131, and the channel hole penetrates through the stack structure 130, the The semiconductor material layer 190 extends into the semiconductor substrate 110; the memory strings are formed in the channel holes, and the memory strings sequentially include a filling insulating layer 170 from the center of the channel holes to the outside. , a channel layer 160, a functional sidewall layer 150 and a high dielectric constant dielectric layer 140; the functional sidewall layer 150 sequentially includes a barrier layer 151, a storage layer 152 and a direction from the sidewall to the center of the channel hole. Tunneling layer 153. It should be noted that, in order to distinguish the structures marked “1xx” in FIG. 1 respectively corresponding to “2xx” in the first embodiment below, please refer to the description in the relevant part below, and will not be repeated here.

Referring to FIG. 1 , in this example, the upper surface of the semiconductor material layer 190 is in contact with the insulating dielectric layer 131 in the stacked structure 130 . The channel hole penetrates through the semiconductor material layer 190 , and the semiconductor material layer 190 is located at the periphery of the channel layer 160 and is in contact with the sidewall of the channel layer 160 , and the channel layer 160 passes through the semiconductor material Layer 190 is connected to a well layer (eg, P-well or N-well) formed in semiconductor substrate 110 . Specifically, please refer to FIG. 1 , the high-k dielectric layer 140 and the functional sidewall layer 150 are formed with epitaxial deposition grooves at positions corresponding to the semiconductor material layer 190 , and the semiconductor material layer 190 is formed in In the epitaxial deposition groove, in contact with the outer sidewall of the channel layer 160, the semiconductor material layer 190 covers this part of the high-k dielectric 140 and the functional sidewall layer 150, and the semiconductor material layer The material of 190 may be a polysilicon layer, which may be formed by but not limited to a selective epitaxy process (Selective Epitaxy Growth, SEG for short).

In the three-dimensional memory shown in FIG. 1, the bottom layer of the gate layer 132 of the stacked structure 130 is used as the gate layer 132 of the bottom selection transistor BSG, that is, the three-dimensional memory adopts a single-layer bottom selection transistor BSG, Since the channel layer 160 is made of polysilicon, and the semiconductor material layer 190 is also made of polysilicon, since the channel layer made of polysilicon has many defect states, it is difficult for the single-layer BSG to turn off and on normally when performing data operations on the three-dimensional memory. operate. Based on this, as shown in FIG. 2 , the present invention provides a three-dimensional memory. By designing and using multi-layer bottom selection tubes, the three-dimensional memory can be better turned off and on during data operations.

Example 1

FIG. 2 shows a schematic diagram of a partial structure of a three-dimensional memory according to an embodiment of the present invention. Referring to FIG. 2, the three-dimensional memory structure includes: a semiconductor substrate 210, a semiconductor material layer 290, a stack structure 230, and a memory string (FIG. 1 shows only one memory string, but in practice it generally includes multiple memory strings. The semiconductor material layer 290 is located between the semiconductor substrate 210 and the stacked structure 230; the stacked structure 230 is formed on the semiconductor substrate 210, and a channel hole is formed in the stacked structure 230, The stacked structure 230 includes alternately stacked gate layers 232 and insulating dielectric layers 231 , and the channel hole penetrates through the stacked structure 230 , the semiconductor material layer 290 and extends into the semiconductor substrate 210 ; The storage string is formed in the channel hole, that is, the storage string passes through the stacked structure and the semiconductor material layer, and the storage string at least includes functional sidewalls arranged in sequence along the radially inward direction Layer 250 and channel layer 260 , the functional sidewall layer 250 is formed on the inner wall (sidewall and bottom) of the channel hole, and the channel layer 260 is formed on the surface of the functional sidewall layer 250 .

Specifically, in the present invention, the semiconductor substrate 210 may be selected according to the actual requirements of the device, and the semiconductor substrate 210 may include a silicon substrate, a germanium (Ge) substrate, and a silicon germanium (SiGe) substrate , SOI (Silicon-on-insulator, silicon-on-insulator) substrate or GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc. In other embodiments, the semiconductor substrate 210 may also include other A substrate of elemental semiconductor or compound semiconductor, such as gallium arsenide, indium phosphide, or silicon carbide, etc., the semiconductor substrate 210 may also be a stacked structure, such as a silicon/germanium silicon stack, etc. In this embodiment, the The semiconductor substrate 210 includes a single crystal silicon substrate. In addition, the semiconductor substrate 210 may be an ion-doped substrate, either P-type doping or N-type doping, and a plurality of peripheral devices may also be formed in the semiconductor substrate 210. Such as field effect transistors, capacitors, inductors and/or pn junction diodes, etc., the semiconductor substrate 210 may also have peripheral circuits.

Specifically, referring to FIG. 2 , in the present invention, the stacked structure 230 includes a plurality of gate layers 232 stacked in a vertical direction (perpendicular to the extension plane of the substrate), and adjacent gate layers A plurality of insulating dielectric layers 231 for isolation between 232, the number of the gate layers 232 can be selected according to needs, as an example, the number of layers of the gate layer 232 as the word line WL can be, for example, 8, 16 , 32 layers, 64 layers, 128 layers, etc. As an example, the gate layer 232 can be made of conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped polycrystalline Si (polysilicon), doped Any one of single crystal Si and silicide or any combination thereof; the insulating dielectric layer 231 adopts insulating material, including but not limited to any one of silicon oxide, silicon nitride, and silicon oxynitride or any combination thereof.

It should be noted that the functional sidewall layer 250 may be directly formed on the sidewall and bottom of the channel hole, or may be formed on the sidewall surface of the channel hole and the channel hole through other material layers. Other material layers are also formed between the bottom of the channel hole, that is, the sidewall surface of the channel hole and the bottom of the channel hole and the functional sidewall layer 250 . Referring to FIG. 2 , in this embodiment, a high-k dielectric layer 240 is formed on the sidewall and bottom of the channel hole, and the functional sidewall layer 250 is formed on the surface of the high-k dielectric layer 240 In other words, the high-k dielectric layer surrounds the functional sidewall layer. As an example, the functional sidewall layer 250 includes a blocking layer 251 , a storage layer 252 and a tunneling layer 253 in order from the sidewall of the channel hole to the center. As an example, the blocking layer 251 includes an oxide layer and an oxynitride layer that are alternately stacked laterally; the storage layer 252 includes a nitride layer and an oxynitride layer that are alternately stacked laterally; the tunnel layer 253 includes Laterally spaced oxide layers and an oxynitride layer between the oxide layers. As an example, the blocking layer 251 may include, but is not limited to, a silicon oxide layer, the storage layer 252 may include, but is not limited to, a silicon nitride layer, and the tunneling layer 253 may include, but is not limited to, a silicon oxide layer. In a specific example, the blocking layer 251 includes a silicon oxide layer, the storage layer 252 includes a silicon nitride layer, and the tunneling layer 253 includes a silicon oxide layer, thereby forming the functional sidewall layer 250 of the ONO structure.

Referring to FIG. 2, in an optional embodiment, the memory string further includes a filling insulating layer, the filling insulating layer is formed on the surface of the channel layer 260, and is filled in the channel hole; Controlling the process parameters of the filling insulating layer to form an insulating gap 280 in the insulating filling layer, the insulating gap 280 can release the stress of the material layer around the insulating gap 280 and is beneficial to the layers of the stacked structure 230 increase in numbers.

Referring to FIG. 2 , in this embodiment, the upper surface of the semiconductor material layer 290 is in contact with the insulating dielectric layer 231 in the stacked structure 230 . It can be understood that, in other embodiments, an additional oxide layer, such as a silicon oxide layer, may also be formed between the semiconductor material layer 290 and the stacked structure 230 . Specifically, the channel hole penetrates the semiconductor material layer 290 , and the semiconductor material layer 290 is located at the periphery of the channel layer 260 and is in contact with the sidewall of the channel layer 260 , and the channel layer 260 A doped well (eg, P-well or N-well) formed in the semiconductor substrate 210 is connected through the semiconductor material layer 290 . Specifically, referring to FIG. 2 , epitaxial deposition grooves are formed in the high-k dielectric layer 240 and the functional sidewall layer 250 corresponding to the positions of the semiconductor material layer 290 , and the semiconductor material layer 290 is formed in In the epitaxial deposition groove, in contact with the outer sidewall of the channel layer 260, the semiconductor material layer 290 covers this part of the high-k dielectric and the functional sidewall layer 250, and the semiconductor material layer 290 The material may be a silicon layer, which may be formed by, but not limited to, a selective epitaxy process SEG.

It should be noted that, in this embodiment, at least two gate layers 232 at the bottom of the stack structure 230 are used as gate layers 232 of the two-layer bottom selection transistor BSG, that is, at least two layers at the bottom of the stack structure 230 The gate layer 232 is connected to the source select lines GSL of the three-dimensional memory (eg, GSL1 and GSL2 in FIG. 3 and FIG. 5 ), and the other gate layers 232 above the gate layer 232 of the bottom select transistor BSG are used as storage layers 252, that is to say, each memory string in the semiconductor structure of the present invention has at least two bottom selection transistors BSG, so that when data operations are performed on the three-dimensional memory, all the bottom selection transistors BSG are simultaneously turned off or on. state, the use of multiple bottom selection transistors BSG can better realize the turn-off and turn-on operations, and improve the performance of erasing, programming and reading of the three-dimensional memory, which will be described in detail below, and will not be repeated here. The top of the storage string also has top selection transistors TSG connected to it in a one-to-one correspondence, and the storage string is connected to the corresponding bit line through the top selection transistor TSG.

In this embodiment, the gate layers 232 of all the bottom selection transistors are connected in common, so that the gate voltages of the gate layers 232 of the corresponding bottom selection transistors BSG can be controlled at the same time, and the gate voltage of the bottom selection transistor BSG can be controlled simultaneously. On or off. In one embodiment, the gate layers 232 of all the bottom selection transistors may also be disconnected from each other. During the control, the gate layers 232 of the bottom selection transistors are controlled by applying the same all gate layers. The desired gate voltage can also achieve the purpose of the present invention.

FIG. 3 shows an equivalent circuit diagram of the three-dimensional memory of this embodiment, and specifically shows a circuit diagram of a relevant part of an equivalent circuit of a memory block Block in the three-dimensional memory. Referring to FIG. 3, memory strings (hereinafter referred to as NAND strings) NAND strings NS11 and NS21 are arranged between the first bit line BL1 and the common source line ACS; NAND strings NS12, NS22 are arranged between the second bit line BL2 and the common source line Between the pole lines ACS (Array common Source, array common source). The top select transistor TSG for each NAND string NS is connected to the corresponding bit line BL; the bottom select transistor BSG for each NAND string NS is connected to the common source line ACS, and memory cells MC are arranged in each NAND string NS The top selection tube TSG and the bottom selection tube BSG.

Hereinafter, the NAND strings NS will be defined in units of rows and columns. The NAND strings NS connected in common to one bit line BL form a column, therefore, the NAND strings NS11, NS21 are connected to the first bit line BL1 corresponding to the first column; the NAND strings NS12, NS22 are connected to the second corresponding to the second column Bit line BL2; NAND strings NS connected to one string select line SSL form a row, so NAND strings NS11, NS12 are connected to the first string select line SSL1 corresponding to the first row; NAND strings NS21, NS22 are connected to the first string select line corresponding to the first row The second string select line SSL2 of the two rows. NAND strings NS in the same row share one string selection line SSL; NAND strings NS in different rows are respectively connected to different string selection lines SSL, namely SSL1 and SSL2 in the figure. Memory cells MC having the same height in NAND strings NS on the same row share one word line WL, and on the same height, word lines WL of NAND strings NS on different rows are commonly connected.

As shown in FIG. 3, word lines WL having the same height are connected in common, so when a specific word line WL is selected, all NAND strings NS connected to the specific word line WL are selected. The NAND strings NS of different rows are connected to different string select lines SSL, and the NAND strings NS of different columns are connected to different bit lines BL. Therefore, the string select lines SSL1 and SSL2, the bit lines BL1 and BL2, and the word line WL1 can be connected through the string select lines SSL1 and SSL2. -WL4 to select a memory cell of a particular NAND string NS.

In an optional embodiment, the three-dimensional memory further includes a dummy gate layer (not shown) located between the stacked structure and the semiconductor material layer 290, and the memory string passes through the dummy gate. Floor. The upper surface of the dummy gate layer is in contact with the insulating dielectric layer 231 in the stacked structure 230 , and an additional oxide layer (such as silicon oxide or other layers) is passed between the dummy gate layer and the semiconductor material layer 290 . insulating dielectric layer) for isolation.

It should be noted that, in FIG. 3 and FIG. 5 and FIG. 6 to be introduced below, for simplicity, only four memory strings NS11, NS21, NS12 and NS22, two bit lines (BL1, BL2) are shown, In the case of four word lines (WL1, WL2, WL3, WL4), two string select lines (SSL1 and SSL2), and two source select lines (GSL1 and GSL2) at different layers, in practical applications, the memory string , the number of bit lines, word lines, string selection lines and source selection lines can be set according to needs, not limited to this; it is also understood that the bottom selection tube BSG in each memory string can also include three or more. , the number of memory cells MC in each memory string can also be adjusted as required. As an example, each memory cell may be a one-bit memory cell or a multi-bit memory cell.

Embodiment 2

An embodiment of the present invention also provides a control method for the three-dimensional memory shown in FIG. 2 . The control method for the three-dimensional memory includes an erasing method, a programming method, and a reading method. The following three aspects will be developed, and the following In the text, the three-dimensional memory includes a storage block Block. It can be understood that the following control method is also applicable to the erasing of a storage block Block in the three-dimensional storage that includes a plurality of storage blocks, and programming. and read operations.

The semiconductor substrate 210 of the three-dimensional memory is provided with a doped well, and the doped well is connected to the channel layer of the memory string through the semiconductor material layer; the three-dimensional memory control method includes an erasing operation step, When the erasing operation is performed, the erasing operation is generally performed in a unit of a memory block. In this embodiment, during the erasing operation: first, an erasing voltage is applied to the doped wells of the semiconductor substrate 210 of the three-dimensional memory; then, after applying the erasing voltage for a preset period of time, the The source selection line GSL applies a turn-on voltage on the gate layers 232 of all bottom selection transistors of the three-dimensional memory (assuming only one memory block Block); wherein, within a preset time period, the storage of the three-dimensional memory The gate voltage on the gate layer 232 of the bottom selection transistor of the block is zero; it should be noted that during the erasing operation, the voltage of each word line WL in the three-dimensional memory is zero during the erasing process, that is, During an erase operation, no turn-on voltage is applied to all of the storage layers 252 . It should be noted that the length of the preset time period can be adjusted according to the actual situation.

The erasing process will be described in detail below with reference to FIG. 4 . During erasing, an erasing voltage PW Vers is applied through a P well (in some embodiments, an N well) in the semiconductor substrate 210; after applying the erasing voltage for a predetermined period of time, all bottom The turn-on voltage Vers-α is applied to the gate layer 232 of the selection transistor BSG, wherein, within a preset time period, the gate voltages on the gate layers 232 of all bottom selection transistors BSG are 0, that is, within a preset time period In the segment, all the bottom selection transistors BSG are in the off state; the siphon effect generated by the delay between PW Vers and BSG Vers-α can better achieve erasing, and in the preset time period, the use of multiple layers of BSG can be more effective. It can be turned off to prevent the upward flow of holes during the delay period, which will affect the erasing efficiency. As an example, during the erasing process, the erasing voltage PW Vers needs to remain greater than the turn-on voltage Vers-α applied to the gate layer 232 of the bottom selection transistor BSG. As an example, the preset time period is less than the time of the rising period of the erase voltage PW Vers.

During a programming operation (which can also be understood as writing data), memory cells are programmed according to a word line programming sequence or other programming rules. For example, programming may begin at a word line at the source side of the memory block and continue to the word line at the drain side of the memory block. In a programming rule, each word line is programmed before proceeding to programming of the next word line (ie, programming is performed in units of pages). During programming, a layer in the three-dimensional memory is selected as the selection layer; the programming voltage is applied to the selection layer, and the bit line voltage is not applied to the bit line corresponding to the selection string, that is, the selection string is The corresponding bit line is grounded to perform programming operations on the select string and inhibit operations on other memory strings.

According to the written data in the program command, each memory cell will be in a certain data state, the memory cell is in an erased state, or a programmed state. At the same time, there are differences in the data states of the memory cell tubes of different bits. For example, in a one-bit memory cell transistor (SLC, Single-Level Cell), there are two data states of an erased state L0 and a programmed state L1. In a two-bit memory cell tube (MLC, Multi-Level Cell), there are four data states of an erased state L0 and three higher data states called L1, L2 and L3 data status. In a three-bit memory cell tube (TLC, Trinary-Level Cell), there are eight data states including an erased state L0 and seven higher data states called L1, L2 , L3, L4, L5, L6, L7 data status.

FIG. 5 shows a partial circuit diagram of an equivalent circuit of a memory block of the three-dimensional memory of FIG. 3 when programming. As an example, taking the memory cell A in the NAND string NS21 as an example, during programming, as shown in FIG. 5 , 0V is applied to the bit line BL1, the power supply voltage V _cc is applied to the bit line BL2, and the string select 0V is applied to the line SSL1, and the power supply voltage V _cc is applied to the string selection line SSL2, so that the NAND string NS21 can be uniquely selected as the selection string, and other storage strings (such as NAND strings NS11, NS12, NS22) are used as non-selected strings (or It is called inhibit string), the programming voltage V _pgm is applied to the word line WL2 corresponding to the memory cell A, and the pass voltage V is applied to the word lines WL1, WL3 and WL4 corresponding to the other layers 252 of different layers from the memory cell A. _pass to complete the programming of memory cell A. Wherein, in the process of programming, at least two layers at the bottom of each memory string (only two layers are shown in the figure, in other embodiments there may be more than two layers, such as three layers, four layers, etc.) bottom selection transistors The gate layer 232 of the BSG is grounded through the source selection lines GSL1 and GSL2 (that is, the gate voltages on the gate layers 232 of at least two bottom select transistors BSG at the bottom of each memory string are zero), that is, the gate voltages on the gate layers 232 of the bottom select transistors BSG are zero at the bottom of each memory string. At least two layers of bottom selection transistors BSG at the bottom of the string are in the off state, and the shutdown effect can be better achieved through at least two layers of bottom selection transistors BSG, which effectively prevents memory cells B, C, D from being programmed when memory cell A is programmed. Disturb. It should be noted that other memory cells can also be programmed using a method similar to that of memory cell A, which is not repeated here.

As a comparison, FIG. 6 shows a partial circuit diagram of an equivalent circuit of a memory block of the three-dimensional memory of FIG. 1 during programming. Applying a voltage according to a similar method described in FIG. 5 can also complete the programming of memory cell A, However, since there is only one layer of bottom selection transistor BSG at the bottom of each memory string, it can be seen from the foregoing analysis that the single-layer bottom selection transistor BSG cannot be effectively turned off. Other memory cells B, C, and D in the same layer of cell A cause weak programming, that is, when memory cell A is programmed, it will cause interference to memory cells B, C, and D. In this embodiment, the design of the multi-layer bottom selection transistor BSG shown in FIG. 2 can better realize the shutdown, can effectively prevent the upward hole during programming, and effectively reduce the memory cell B, when the memory cell A is programmed. C, D interference.

In this embodiment, after the programming operation is performed on the memory cells, the data written in the programming operation can be read through a read operation. After the read pass voltage is applied to the selected word line, the data stored in the memory is read out through the corresponding bit line, wherein, during data reading, the gate layers 232 of all bottom selection transistors of the three-dimensional memory are simultaneously The turn-on voltage is applied to make the corresponding bottom selection transistor BSG of the three-dimensional memory in an on state, which hardly affects the read performance of the three-dimensional memory.

In practical application, the control method of the above-mentioned three-dimensional memory can be realized by the processor of the control device as shown in FIG. 7 , and the control device includes: a communicator 12 for communicating with the outside; a memory 13 for storing computer programs a processor 11, connected to the communicator 12 and the memory 13, for running the computer program to execute the above-mentioned three-dimensional memory control method. The various components in the control device are coupled together by a bus system (thick horizontal lines in Figure 7). It can be understood that the bus system is used to realize the connection communication between these components. In addition to the data bus, the bus system also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, the various buses are labeled as bus systems in FIG. 7 .

In an exemplary embodiment, an embodiment of the present invention also provides a storage medium, which is a computer-readable storage medium, for example, a memory including a computer program, and the computer program can be executed by a processor of a control device of a 3D memory to complete the foregoing the steps of the method. The computer-readable storage medium may be a removable storage device, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and other mediums that can store program codes.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (15)

1. a three-dimensional memory, is characterized in that, described three-dimensional memory comprises: semiconductor substrate; a semiconductor material layer on the semiconductor substrate; a stacked structure on the semiconductor material layer, the stacked structure including alternately stacked dielectric layers and gate layers; memory strings passing through the stack structure and the layers of semiconductor material; Wherein, at least two of the gate layers at the bottom of the stacked structure serve as gate layers of the bottom selection transistor. 2 . The three-dimensional memory according to claim 1 , wherein the memory strings comprise functional sidewall layers and channel layers that are sequentially arranged in a radially inward direction. 3 . 3 . The three-dimensional memory of claim 2 , wherein the memory string further comprises a high-k dielectric layer, the high-k dielectric layer surrounding the functional sidewall layer. 4 . 4. The three-dimensional memory according to claim 2, wherein the semiconductor material layer is located at the periphery of the channel layer and is in contact with the sidewall of the channel layer. 5. The three-dimensional memory according to claim 4, wherein the material of the semiconductor material layer comprises polysilicon. 6 . The three-dimensional memory according to claim 1 , wherein the three-dimensional memory further comprises a dummy gate layer located between the stacked structure and the semiconductor material layer, and the memory string passes through the dummy gate layer. 7 . gate layer. 7 . The three-dimensional memory according to claim 1 , wherein the gate layers of all the bottom selection transistors are connected in common. 8 . 8. The three-dimensional memory according to any one of claims 1-7, wherein the three-dimensional memory comprises a three-dimensional NAND type memory. 9 . The three-dimensional memory control method according to claim 1 , wherein a semiconductor substrate of the three-dimensional memory is provided with a doped well, and the doped well passes through the semiconductor material. 10 . The layer is connected to the memory string; the three-dimensional memory control method includes an erasing operation, and when the erasing operation is performed: applying an erase voltage to the doped well of the semiconductor substrate of the three-dimensional memory; After the erasing voltage is applied for a preset period of time, a turn-on voltage is applied to the gate layers of all bottom selection transistors of the three-dimensional memory; wherein, within the preset period of time, all of the three-dimensional memory The gate voltage on the gate layer of the bottom select transistor is zero. 10 . The three-dimensional memory control method according to claim 9 , wherein the erase voltage is greater than the turn-on voltage. 11 . 11. The three-dimensional memory control method according to claim 9, wherein the doped well comprises a P-well or an N-well. 12 . The three-dimensional memory control method according to claim 9 , wherein the three-dimensional memory control method further comprises a programming operation, and during the programming operation, the gates of all the bottom selection transistors of the three-dimensional memory The gate voltage of the layer is zero to achieve turn-off with all of the bottom select transistors of the three-dimensional memory. 13. The three-dimensional memory control method according to claim 9, wherein the three-dimensional memory control method further comprises a data reading operation, when performing data reading, all the bottoms of the three-dimensional memory are simultaneously A turn-on voltage is applied to the gate layer of the select tube. 14. A control device, characterized in that the control device comprises: a communicator for communicating with the outside world; memory for storing computer programs; A processor, connected with the communicator and the memory, is used for running the computer program to execute the control method of the three-dimensional memory according to any one of claims 9 to 13. 15 . A computer-readable storage medium, characterized in that a computer program is stored; the computer program executes the control method for a three-dimensional memory according to any one of claims 9 to 13 when the computer program runs. 16 .

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