CN111384005A - Microelectronic package, flip-chip process and its application, microelectronic device - Google Patents

Abstract

The invention relates to the field of chip packaging, and in particular, provides a microelectronic package, a flip-chip process and its application, and a microelectronic device. The flip-chip process of the microelectronic package includes the following steps: (a) providing a substrate provided with conductive blocks; (b) sequentially applying conductive adhesive and non-conductive adhesive on the surfaces of the conductive blocks; (c) placing bumps The chip and the substrate are pressed together and then cured to obtain a microelectronic package. The process adopts the combination of conductive glue and non-conductive glue, the process is simple, the packaging efficiency is high, the chip function is stable and reliable, the package body is not easily warped and deformed, and the service life is long.

Description

Microelectronic package, flip-chip process and its application, microelectronic device

technical field

The invention relates to the field of chip packaging, in particular, to a microelectronic package body, a flip-chip process and its application, and a microelectronic device.

Background technique

The flip-chip packaging process is a packaging technology to improve packaging speed and component reliability. The traditional solder paste flip-chip assembly process includes: fluxing, chip cloth, solder paste reflow and underfill, etc. Design considerations include solder bumps and underbump structures. The role of the solder bumps is to serve as a mechanical, electrical, and sometimes thermal interconnect between the IC and the circuit board.

The existing flip-chip process has the following disadvantages: First, during the flip-chip process, when there are too many fluxes (such as solder balls) or bumps, it is necessary to use glue with finer particles to fill the bottom first, and then perform plastic sealing. At this time, the flux Or the bumps are easily unable to touch the bottom conductive block, and it is cured in a single piece, and the efficiency is low. Secondly, the flux needs to be cleaned before underfilling. If the cleaning is not clean, it will cause gaps or holes, and it is easy to fail directly when the board is loaded. In addition, when underfilling, the filler needs to leave no gap, and ion migration will occur even in nano-level delamination, resulting in excessive electrical loss, model distortion, and even functional failure. Furthermore, the reflow soldering temperature is generally over 250°C, and the temperature is relatively high, which not only requires higher mechanical properties of the unprotected chips, but also re-melts the internal tin bumps when the product is finally placed on the board. If the tin is not sufficiently melted, the tin will be redistributed, and the circuit may be disconnected, seriously affecting the electrical performance of the chip. In addition, the use of conventional tin for conduction, the temperature is high, and special material requirements for the substrate and the chip are required. Different materials in the package will have different warpages at different temperatures, and the overall material warpage should be matched during design. , to reduce the overall warpage, the height of flip-chip bumps is generally 10-50 microns, and the height of the solder paste coating on the bumps is 10-50 microns, so it is particularly sensitive to material deformation.

In view of this, the present invention is proposed.

SUMMARY OF THE INVENTION

The first object of the present invention is to provide a microelectronic package, which uses a conductive adhesive layer to electrically connect the substrate and the chip, which changes the traditional structure of using a tin block to electrically connect the substrate and the chip. The structure is novel, and the chip and the substrate are connected. The bonding strength is high, the conductive ions in the conductive adhesive layer are not easy to migrate, and the function of the chip is stable and reliable.

The second object of the present invention is to provide a flip-chip process for a microelectronic package. The process uses conductive glue and non-conductive glue to cooperate, and the process is simple, the packaging efficiency is high, the chip function is stable and reliable, and the package is not easily warped and deformed. long life.

The third object of the present invention is to provide an application of the above-mentioned microelectronic package.

The fourth object of the present invention is to provide a microelectronic device.

In order to realize the above-mentioned purpose of the present invention, the following technical solutions are specially adopted:

In a first aspect, the present invention provides a microelectronic package, comprising a substrate and a chip, a conductive block is arranged on the substrate, a conductive adhesive layer and a non-conductive adhesive layer are arranged on the surface of the conductive block in sequence, and the chip is provided with a bump, the convex The block is pressed over the conductive block.

As a further preferred technical solution, the substrate is further provided with solder resist ink, and the solder resist ink is provided on the periphery of the conductive block.

As a further preferred technical solution, the height of the solder resist ink is greater than the height of the conductive block.

As a further preferred technical solution, the conductive block is provided with a groove, and the opening of the groove faces the chip.

In a second aspect, the present invention provides a flip-chip process for the above-mentioned microelectronic package, comprising the following steps:

(a) providing a substrate provided with conductive blocks;

(b) Coating conductive adhesive and non-conductive adhesive on the surface of the conductive block in turn;

(c) pressing the chip provided with the bumps to the substrate, and then curing to obtain a microelectronic package.

As a further preferred technical solution, the volume resistance of the conductive adhesive is lower than 0.05Ω/cm.

As a further preferred technical solution, the height of the conductive adhesive is 1/4-2/3 of the height of the conductive block.

As a further preferred technical solution, the Ti value of the conductive adhesive and the non-conductive adhesive is not lower than 3 and not higher than 6;

Preferably, the Ti value of the non-conductive adhesive is higher than that of the conductive adhesive;

Preferably, the conductive glue includes conductive silver glue;

Preferably, the pressing pressure in step (c) is 0.5-10N;

Preferably, in step (c), the curing temperature is 150-180° C., and the curing time is 15-120 min.

In a third aspect, the present invention provides an application of the above-mentioned microelectronic package or the microelectronic package obtained by the above-mentioned flip-chip process in preparing a microelectronic device.

In a fourth aspect, the present invention provides a microelectronic device, comprising the above-mentioned microelectronic package or a microelectronic package obtained by the above-mentioned flip-chip process.

Compared with the prior art, the beneficial effects of the present invention are:

The microelectronic package provided by the present invention is pressed on the conductive block through the bump, and the conductive adhesive layer connects the bump and the conductive block, thereby realizing the electrical connection between the substrate and the chip. The package body uses a conductive adhesive layer to electrically connect the substrate and the chip, which changes the traditional structure of using a tin block to electrically connect the substrate and the chip. The structure is novel, and the bonding strength between the chip and the substrate is high, and the conductive ions in the conductive adhesive layer are not easy to migrate. The function of the chip is stable and reliable; the bump is pressed on the conductive block without reflow soldering, which avoids the warping deformation caused by the mismatch between the thermal expansion coefficient of the chip and the substrate caused by high temperature, and has a long service life; conductive adhesive layer and non-conductive The deformation of the adhesive layer is small, and the thickness of the package body is small.

In the flip-chip process provided by the present invention, a conductive block is arranged on the substrate, and the conductive block has conductivity to realize the electrical connection between the substrate and the chip. The conductive glue has conductivity, and coating the conductive glue on the surface of the conductive block can ensure that the glue has conductivity after curing, and realize the electrical connection between the bump of the chip and the conductive block of the substrate. The non-conductive adhesive has no conductivity and can isolate the ions that are easily migrated in the conductive adhesive. The conductive adhesive and the non-conductive adhesive jointly provide adhesion and bond the substrate and the chip together. The chip and the substrate are pressed together and then cured to complete the packaging of the chip.

The above process has the following advantages:

(1) The conductive glue is matched with the non-conductive glue. The conductive glue is electrically connected to the bump and the conductive block. The non-conductive glue isolates the conductive medium and improves the bonding strength between the chip and the substrate. Compared with the traditional method, the amount of the non-conductive glue in this process is relatively low. Small, can ensure that the bumps fully contact the conductive blocks, and can be cured together with multiple pieces, which greatly improves the packaging efficiency.

(2) The process does not use flux, so there is no need to clean the flux, the process is simpler, and there is no risk of chip failure due to unclean cleaning. Moreover, there is no need for a subsequent sealing process, and it is possible to directly perform plastic sealing or no plastic sealing.

(3) The non-conductive components that play the role of bonding in the conductive adhesive are mainly non-conductive components, and their proportion is very low, which will not affect the conductivity of the conductive adhesive, but can effectively isolate the easily migrated conductive ions in the adhesive without using too many non-conductive components. The conductive adhesive can ensure that the ions do not migrate, thereby avoiding electrical loss and ensuring that the function of the chip does not fail.

(4) The conductive adhesive and non-conductive adhesive are cured in one time, no reflow soldering is required, and when the board is finally put on the board, it will not be melted twice, and there will be no re-melting and disconnection (in the electrical test of a single product, it is A good product may be a defective product after being put on the board).

(5) The use of conductive adhesive for electrical connection can realize lower temperature flip-chip electrical connection, which is lower than the deformation transition temperature (160-175°C) of most materials at present, thereby reducing the thermal expansion of the substrate and the chip material. The matching of coefficients is difficult, the material design time is short, the cost is low, the operation requirements are low, the stress generated by the material deformation is small, and the chip is not easily deformed.

(6) The amount of deformation of the conductive adhesive and the non-conductive adhesive is small, so there is no need to reserve expansion and contraction space for the deformation of the substrate, and the substrate can be thinner, thereby reducing the thickness of the overall package.

Description of drawings

FIG. 1 is a schematic structural diagram of a microelectronic package according to an embodiment of the present invention;

2 is a schematic diagram of step (a) of a flip-chip process according to an embodiment of the present invention;

3 is a schematic diagram of step (b) of a flip-chip process according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of step (c) of a flip-chip process according to an embodiment of the present invention.

Icon: 1-substrate; 101-conductive block; 1011-groove; 102-solder mask ink; 103-conductive adhesive layer; 1031-conductive adhesive; 104-non-conductive adhesive layer; 1041-non-conductive adhesive; 2-chip; 201 - Bump.

Detailed ways

The embodiments of the present invention will be described in detail below with reference to the examples, but those skilled in the art will understand that the following examples are only used to illustrate the present invention and should not be regarded as limiting the scope of the present invention. If the specific conditions are not indicated in the examples, it is carried out according to the conventional conditions or the conditions suggested by the manufacturer.

According to one aspect of the present invention, a microelectronic package is provided. As shown in FIG. 1 , it includes a substrate 1 and a chip 2 . The substrate 1 is provided with a conductive block 101 , and the surface of the conductive block 101 is sequentially provided with a conductive adhesive layer 103 and a chip 2 . On the non-conductive adhesive layer 104 , bumps 201 are disposed on the chip 2 , and the bumps 201 are pressed on the conductive bumps 101 .

The above-mentioned microelectronic package body is pressed on the conductive block through the bump, and the conductive adhesive layer connects the bump and the conductive block, so as to realize the electrical connection between the substrate and the chip. The package body uses a conductive adhesive layer to electrically connect the substrate and the chip, which changes the traditional structure of using a tin block to electrically connect the substrate and the chip. The structure is novel, and the bonding strength between the chip and the substrate is high, and the conductive ions in the conductive adhesive layer are not easy to migrate. The function of the chip is stable and reliable; the bump is pressed on the conductive block without reflow soldering, which avoids the warping deformation caused by the mismatch between the thermal expansion coefficient of the chip and the substrate caused by high temperature, and has a long service life; conductive adhesive layer and non-conductive The deformation of the adhesive layer is small, and the thickness of the package body is small.

It should be noted:

The above-mentioned "conductive adhesive layer" refers to a coating formed after the conductive adhesive is cured or dried, and the conductive adhesive refers to an adhesive with certain conductivity after curing or drying.

"Non-conductive glue" refers to the coating formed after curing or drying of the non-conductive glue, and non-conductive glue refers to the adhesive that does not have electrical conductivity after curing or drying.

"Press fit" refers to the process of joining two separate parts or assemblies together using pressure.

The "surface of the conductive block" refers to all surfaces of the conductive block except the surface that is in direct contact with the substrate. "The conductive adhesive layer and the non-conductive adhesive layer are sequentially arranged on the surface of the conductive block" means that the conductive adhesive layer and the non-conductive adhesive layer are sequentially arranged on the periphery of the surface of the conductive block, the conductive adhesive layer completely covers the surface of the conductive block, and the non-conductive adhesive layer will The conductive adhesive layer is completely covered.

In a preferred embodiment, the substrate 1 is further provided with solder resist ink 102 , and the solder resist ink 102 is provided on the periphery of the conductive block 101 . The role of solder resist ink is mainly used to prevent line oxidation on the chip, prevent line open or short circuit and other problems, so as to realize the packaging and protection of chip lines.

Preferably, the height of the solder resist ink 102 is greater than the height of the conductive block 101 .

"Height of the solder mask ink" refers to the vertical distance between the top end of the solder mask ink and the bottom end of the solder mask ink.

The "height of the conductive block" refers to the vertical distance between the top end of the conductive block and the bottom end of the conductive block.

The above "top" refers to the end with the largest vertical distance between the solder mask ink or the conductive block and the horizontal surface when the substrate is flat on the horizontal surface; on the contrary, the "bottom end" refers to the solder mask ink when the substrate is flat on the horizontal Or the end of the conductive block with the smallest vertical distance from the horizontal plane.

In a preferred embodiment, the conductive block 101 is provided with a groove 1011 , and the opening of the groove 1011 faces the chip 2 . When the conductive block is provided with grooves, more conductive adhesives can be accommodated in the grooves, so more conductive particles can be accommodated. At this time, the same amount of conductive adhesive can make the conductive adhesive layer thinner, so the overall thickness of the package body will be reduced. thinner.

Of course, the surface of the conductive block can also be flat without grooves. When there is no groove on the surface of the conductive block, when the conductive adhesive layer is very thin, the conductive particles in the conductive adhesive are more likely to be squeezed to the side, and the amount of conductive particles left between the conductive block and the bump will be less, and the conductive The electrical connections between bumps and bumps work slightly less well. As mentioned in the previous paragraph, when the conductive blocks are provided with grooves, the amount of conductive particles left between the conductive blocks and the bumps will be more, which is not only conducive to maintaining a better electrical connection between the conductive blocks and the bumps , but also reduce the thickness of the conductive adhesive layer.

Figure 1 provides a schematic structural diagram of a microelectronic package with a typical structure of the present invention. It can be seen from the figure that the amount of non-conductive glue is large, which is enough to fully bond the chip and the bottom plate, without the need for subsequent plastic sealing, etc. craft. Obviously, the microelectronic package can also have another structure. In this structure, the non-conductive adhesive also exists in the space enclosed by the solder resist ink after curing, and the space includes the conductive block, the conductive adhesive and the non-conductive adhesive. , at this time, the encapsulation body still needs subsequent processes such as plastic encapsulation.

According to an aspect of the present invention, there is provided a flip-chip process for the above-mentioned microelectronic package, as shown in FIG. 2 to FIG. 4 , including the following steps:

(a) providing the substrate 1 provided with the conductive blocks 101;

(b) sequentially applying conductive adhesive 1031 and non-conductive adhesive 1041 on the surface of the conductive block 101;

(c) Pressing the chip 2 provided with the bumps 201 and the substrate 1, and then curing, to obtain a microelectronic package.

In the above flip-chip process, a conductive block is provided on the substrate, and the conductive block has conductivity to realize the electrical connection between the substrate and the chip. The conductive glue has conductivity, and coating the conductive glue on the surface of the conductive block can ensure that the glue has conductivity after curing, and realize the electrical connection between the bump of the chip and the conductive block of the substrate. The non-conductive adhesive has no conductivity and can isolate the ions that are easily migrated in the conductive adhesive. The conductive adhesive and the non-conductive adhesive jointly provide adhesion and bond the substrate and the chip together. The chip and the substrate are pressed together and then cured to complete the packaging of the chip. A typical but non-limiting structure diagram of the package body is shown in FIG. 1 .

The above process has the following advantages:

(1) The conductive glue is matched with the non-conductive glue. The conductive glue is electrically connected to the bump and the conductive block. The non-conductive glue isolates the conductive medium and improves the bonding strength between the chip and the substrate. Compared with the traditional method, the amount of the non-conductive glue in this process is relatively low. Small, can ensure that the bumps fully contact the conductive blocks, and can be cured together with multiple pieces, which greatly improves the packaging efficiency.

(2) The process does not use flux, so there is no need to clean the flux, the process is simpler, and there is no risk of chip failure due to unclean cleaning. Moreover, there is no need for a subsequent sealing process, and it is possible to directly perform plastic sealing or no plastic sealing.

(3) The non-conductive components that play the role of bonding in the conductive adhesive are mainly non-conductive components, and their proportion is very low, which will not affect the conductivity of the conductive adhesive, but can effectively isolate the easily migrated conductive ions in the adhesive without using too many non-conductive components. The conductive adhesive can ensure that the ions do not migrate, thereby avoiding electrical loss and ensuring that the function of the chip does not fail.

(4) The conductive adhesive and non-conductive adhesive are cured in one time, no reflow soldering is required, and when the board is finally put on the board, it will not be melted twice, and there will be no re-melting and disconnection (in the electrical test of a single product, it is A good product may be a defective product after being put on the board).

(5) The use of conductive adhesive for electrical connection can realize lower temperature flip-chip electrical connection, which is lower than the deformation transition temperature (160-175°C) of most materials at present, thereby reducing the thermal expansion of the substrate and the chip material. The matching of coefficients is difficult, the material design time is short, the cost is low, the operation requirements are low, the stress generated by the material deformation is small, and the chip is not easily deformed.

(6) The amount of deformation of the conductive adhesive and the non-conductive adhesive is small, so there is no need to reserve expansion and contraction space for the deformation of the substrate, and the substrate can be thinner, thereby reducing the thickness of the overall package.

In a preferred embodiment, the volume resistance of the conductive adhesive is lower than 0.05Ω/cm. Low volume resistance is beneficial to ensure the conductivity of the conductive adhesive after curing.

Preferably, the height of the conductive adhesive is 1/4-2/3 of the height of the conductive block. The height of the conductive adhesive is controlled. The lower limit of 1/4 is to ensure that the conductive particles in the conductive adhesive can have a sufficient ratio between the chip bumps and the conductive blocks of the substrate, and the upper limit of 2/3 is to prevent the conductive adhesive from contacting the chip surface. The diffusion of conductive particles affects the electrical properties.

The "height of the conductive glue" is the vertical distance between the top of the conductive glue and the top of the conductive block.

The "height of the conductive block" refers to the vertical distance between the top end of the conductive block and the bottom end of the conductive block.

The above "top" refers to the end with the largest vertical distance between the conductive adhesive or the conductive block and the horizontal plane when the substrate is laid flat on the horizontal plane; on the contrary, the "bottom end" refers to the conductive block and the horizontal plane when the substrate is laid flat on the horizontal plane. The end with the smallest vertical distance.

Optionally, the conductive particles may be spherical, ellipsoid, flake or columnar, and the length in the diameter direction of the conductive particles is less than or equal to 0.3 μm.

In a preferred embodiment, the Ti values of the conductive adhesive and the non-conductive adhesive are not lower than 3 and not higher than 6. Ti value refers to the thixotropic index, which means the ratio of the viscosity value at low speed (6r/min) to the viscosity value at high speed (60r/min). For example, the Ti values of the conductive paste and the non-conductive paste are each independently 3, 3.5, 4, 4.5, 5, 5.5, or 6.

Preferably, the Ti value of the non-conductive paste is higher than that of the conductive paste. When the Ti value of the non-conductive adhesive is higher than that of the conductive adhesive, the thixotropy of the non-conductive adhesive is relatively higher, so that the non-conductive adhesive can diffuse to the surroundings during pressing, filling the space around the conductive block, ensuring non-conductive adhesive. The coverage of the conductive glue on the surface of the conductive glue, while minimizing the amount of non-conductive glue between the conductive glue and the bumps, enhances the electrical connection between the substrate and the chip.

Preferably, the conductive glue includes conductive silver glue.

Preferably, the pressing pressure in step (c) is 0.5-10N. The above pressure is typically but not limited to 0.5, 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10N.

Preferably, in step (c), the curing temperature is 150-180° C., and the curing time is 15-120 min. The above curing temperature is typically but not limited to 150, 155, 160, 165, 170, 175 or 180°C, and the curing time is typically but not limited to 15, 20, 25, 30, 35, 40, 50, 60, 70, 80, 90, 100, 110 or 120 min.

It should also be noted that the above process can be used to complete the protection of the solder joints, which can be directly plastic-sealed without special underfilling. If the amount of glue applied is large, the electrical connection and protection of the chip can be completed without plastic encapsulation. If it needs to be filled, the thickness of the non-conductive glue/the thickness of the conductive glue in the height direction of the chip bump sidewall is greater than 1/4, so Make sure that the conductive glue does not touch the surface of the chip.

According to another aspect of the present invention, there is provided an application of the above-mentioned microelectronic package in preparing a microelectronic device. The application of the above-mentioned microelectronic package in the preparation of microelectronic devices has the advantages of simple preparation process, effective reduction of device thickness, stable and reliable device function, non-deformation, long service life, and the like.

According to another aspect of the present invention, a microelectronic device is provided, comprising the above-mentioned microelectronic package. The microelectronic device includes the above-mentioned microelectronic package, and thus at least has the advantages of stable and reliable function, small thickness, not easy to warp and deform, and long service life.

The above-mentioned "microelectronic device" mainly refers to the miniaturized electronic system chip and device realized by the use of microelectronic process technology, the microelectronic device may include one or more microelectronic package They are connected in a way, or exist independently, and together constitute the whole of the microelectronic device.

Although specific embodiments of the present invention have been illustrated and described, it should be understood that various other changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, it is intended that all such changes and modifications as fall within the scope of this invention be included in the appended claims.

Claims (10)

1. A microelectronic package is characterized in that, comprising a substrate and a chip, a conductive block is provided on the substrate, a conductive adhesive layer and a non-conductive adhesive layer are arranged on the surface of the conductive block in turn, and a bump is provided on the chip, and the bump is pressed. fit over the conductive block. 2 . The microelectronic package according to claim 1 , wherein a solder resist ink is further provided on the substrate, and the solder resist ink is provided on the periphery of the conductive block. 3 . 3. The microelectronic package according to claim 2, wherein the height of the solder resist ink is greater than the height of the conductive block. 4 . The microelectronic package according to claim 1 , wherein the conductive block is provided with a groove, and the opening of the groove faces the chip. 5 . 5. The flip-chip process for a microelectronic package according to any one of claims 1-4, characterized in that it comprises the following steps: (a) providing a substrate provided with conductive blocks; (b) Coating conductive adhesive and non-conductive adhesive on the surface of the conductive block in turn; (c) pressing the chip provided with the bumps to the substrate, and then curing to obtain a microelectronic package. 6 . The flip-chip process according to claim 5 , wherein the volume resistance of the conductive adhesive is lower than 0.05Ω/cm. 7 . 7 . The flip-chip process according to claim 5 , wherein the height of the conductive adhesive is 1/4-2/3 of the height of the conductive block. 8 . 8. The flip-chip process according to any one of claims 5-7, wherein the Ti value of the conductive adhesive and the non-conductive adhesive is not lower than 3 and not higher than 6; Preferably, the Ti value of the non-conductive adhesive is higher than that of the conductive adhesive; Preferably, the conductive glue includes conductive silver glue; Preferably, the pressing pressure in step (c) is 0.5-10N; Preferably, in step (c), the curing temperature is 150-180° C., and the curing time is 15-120 min. 9 . The application of the microelectronic package according to any one of claims 1 to 4 or the microelectronic package obtained by the flip-chip process according to any one of claims 5 to 8 in the preparation of a microelectronic device. 10 . 10. A microelectronic device, characterized by comprising the microelectronic package according to any one of claims 1-4 or a microelectronic package obtained by the flip-chip process according to any one of claims 5-8 .

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