CN111244056A - Wafer level package device with high standoff peripheral solder bumps - Google Patents

Abstract

The present application discloses a wafer level package device and a fabrication technique for the device, the device including a second integrated circuit chip electrically connected to a base integrated circuit chip, wherein the second integrated circuit chip is in a plurality of solder bumps Between high support peripheral posts are placed on and connected to the base integrated circuit chip. In various implementations, a wafer level package device according to the present application employing the techniques of the examples includes a base integrated circuit chip, a plurality of high support peripheral pillars with solder bumps, and a second integrated circuit chip, the second integrated circuit chip An integrated circuit chip is electrically connected to the base integrated circuit chip and placed on the base integrated circuit chip in the center of an array of high-support peripheral pillars with solder bumps.

Description

Wafer-level packaged devices with high-support peripheral solder bumps

This application is a divisional application of Chinese Invention Patent Application No. 201410092684.2 filed on March 13, 2014.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of US Provisional Application No. 61/779,635, filed March 13, 2013, entitled "WAFER-LEVEL PACKAGE DEVICEHAVING HIGH-STANDOFF PERIPHERAL SOLDER BUMPS." US Provisional Application No. 61/779,635 is incorporated herein by reference in its entirety.

technical field

The present application relates to wafer-level packaged devices and methods of making the same.

Background technique

Packaging technology has advanced to develop smaller, cheaper, more reliable, and more environmentally friendly packages. For example, chip scale packaging techniques have been developed using directly surface mountable packages having a surface area no greater than 1.2 times the area of an integrated circuit chip. Wafer-level packaging (WLP) is a chip-level packaging technology that encompasses a wide variety of techniques whereby integrated circuit chips are packaged at the wafer level prior to singulation. Wafer level packaging extends the wafer fabrication process to include device interconnect and device protection processes. Thus, wafer level packaging unifies the manufacturing process by allowing for the integration of wafer fabrication, packaging, testing, and burn-in processes at the wafer level.

A conventional fabrication process used in the manufacture of semiconductor devices employs microlithography to pattern integrated circuits onto circular wafers formed from semiconductors such as silicon, gallium arsenide, and the like. Typically, the patterned wafer is singulated into individual integrated circuit chips or dies in order to separate the integrated circuits from each other. These individual integrated circuit chips are assembled or packaged using a variety of packaging techniques to form semiconductor devices that can be mounted to printed circuit boards.

SUMMARY OF THE INVENTION

Techniques are described for making wafer level packaged semiconductor devices having form factors similar to those employing flat no-lead (eg, QFN) packaging technology. In one or more implementations, a wafer level package device includes an integrated circuit chip (eg, a die) having at least one pillar (eg, a copper pillar) formed over the integrated circuit chip. The pillars are configured to provide electrical interconnection to the integrated circuit chip. A package structure configured to support the pillars is formed on the surface of the integrated circuit chip. In one or more implementations, a second integrated circuit device may be mounted to the integrated circuit chip such that the integrated circuit device is in electrical communication with the integrated circuit chip. The second integrated circuit device is at least partially encapsulated by the encapsulation structure.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

Description of drawings

The detailed description is described with reference to the accompanying drawings. The use of the same reference numbers in different instances in the specification and drawings may refer to similar or identical features.

FIG. 1A is a schematic partial cross-sectional side view illustrating a wafer level package device including a base integrated circuit chip device formed on the base integrated circuit chip device according to implementations of examples of the present application. A unitary device configuration of at least one post having a high support peripheral structure on the base, and a second integrated circuit chip device electrically connected to the base integrated circuit chip device.

FIG. 1B is a schematic partial cross-sectional side view illustrating a wafer level package device including a base integrated circuit chip device formed on the base integrated circuit chip device according to implementations of examples of the present application. A unitary device configuration of at least one post having a high support peripheral structure on the base, and a second integrated circuit chip device electrically connected to the base integrated circuit chip device.

2 is a process flow diagram illustrating, in an example implementation, a process flow for fabricating a wafer-level packaged device, such as the device shown in FIGS. 1A and 1B .

3A is a schematic partial cross-sectional side view illustrating fabrication of a wafer-level packaged device, such as the device shown in FIGS. 1A and 1B , according to the process shown in FIG. 2 .

3B is a schematic partial cross-sectional side view illustrating fabrication of a wafer-level packaged device, such as the device shown in FIGS. 1A and 1B , according to the process shown in FIG. 2 .

3C is a schematic partial cross-sectional side view illustrating fabrication of a wafer-level packaged device, such as the device shown in FIGS. 1A and 1B , according to the process shown in FIG. 2 .

3D is a schematic partial cross-sectional side view illustrating fabrication of a wafer-level packaged device, such as the device shown in FIGS. 1A and 1B , according to the process shown in FIG. 2 .

3E is a schematic partial cross-sectional side view illustrating fabrication of a wafer-level packaged device, such as the device shown in FIGS. 1A and 1B , according to the process shown in FIG. 2 .

3F is a schematic partial cross-sectional side view illustrating fabrication of a wafer-level packaged device, such as the device shown in FIGS. 1A and 1B, according to the process shown in FIG. 2. FIG.

Detailed ways

Overview

Wafer-level packaging is a chip-level packaging technology that encompasses a wide variety of techniques whereby integrated circuit chips are packaged at wafer level prior to singulation. Wafer level packaging extends the wafer fabrication process to include device interconnect and device protection processes. Thus, wafer level packaging unifies the manufacturing process by allowing for the integration of wafer fabrication, packaging, testing, and burn-in processes at the wafer level. Wafer-level packaging is typically less expensive to implement than some packaging technologies (eg, Flat No-Lead (QFN)) because the packaging occurs at the wafer level, whereas Flat No-Lead packaging is implemented at the strip level. Finish.

As the number of computer applications increases, greater amounts of processing functionality and memory functionality provided by integrated circuits may be necessary. However, the greater the number of circuits required may be related to the greater physical space required in the multimedia device. 3D dies can be constructed using two or more layers of electronic components integrated into a single device, typically by stacking and processing semiconductor wafers. These electronic components can be stacked to form a single circuit. It is advantageous to embed silicon chips on active device wafers for 3D integration in order to save physical space and provide increased functionality.

Accordingly, devices and fabrication techniques are described that include a second integrated circuit chip electrically connected to a base integrated circuit chip, wherein the second integrated circuit chip is between a plurality of high standoff peripheral pillars having solder bumps A spacer is placed on the base integrated circuit chip and connected to the base integrated circuit chip. In various implementations, a wafer level package device employing techniques according to examples of the present application includes a base integrated circuit chip, a plurality of high-support peripheral pillars with solder bumps, and a plurality of high-support peripheral pillars that are electrically connected to and placed on the A second integrated circuit chip centered on an array of high-support peripheral pillars with solder bumps on the base integrated circuit chip. In implementations, a process for fabricating the wafer level package device employing techniques according to examples of the present application includes forming at least one pillar on a processed base integrated circuit chip, wherein the at least one pillar has a high Supporting a peripheral structure, and placing a second integrated circuit chip device on the base integrated circuit chip device in the center of the at least one post having a high supporting peripheral structure. Once singulated from a wafer, these devices can be mounted to a printed circuit board or other semiconductor device to form an electronic device, and the solder bumps can provide electrical connections to the pads of the printed circuit board.

Implementation of the instance

FIG. 1 illustrates a wafer-level packaged device 100 according to implementations of examples of the present application. In some implementations, wafer level packaged device 100 may comprise a wafer level integrated circuit packaged device. As shown in FIGS. 1A and 1B , wafer-level packaged device 100 includes a base integrated circuit chip 102 that includes one or more integrated circuits formed therein. The base integrated circuit chip 102 may be included as part of a semiconductor wafer substrate, such as a silicon wafer (eg, p-type wafer, n-type wafer, etc.), germanium wafer, etc., including formed therein one or more integrated circuits. These integrated circuits can be formed near the surface of the semiconductor wafer substrate by suitable front-end-of-line (FEOL) fabrication techniques. In various implementations, these integrated circuits may include digital integrated circuits, analog integrated circuits, mixed-signal integrated circuits, combinations thereof, and the like.

As shown in FIGS. 1A-1B , the wafer level package device 100 includes at least one pillar 104 having a high support peripheral structure. In certain implementations, high support peripheral structure posts 104 may include posts 104 having a height greater than that of second integrated circuit die 106 (and any additional structures on second integrated circuit die 106 ), wherein second integrated circuit die 106 is configured to be placed in the center of the array of high support peripheral posts 104 and wherein the second integrated circuit chip 106 is connected to the base integrated circuit chip 102 . In one implementation, wafer level package device 100 includes pillars 104, which are copper pillars fabricated through a suitable fabrication process, such as a dual stack/deposition process. Other processes can also be used to fabricate the posts 104, such as copper plating. The pillars 104 may be used to provide electrical interconnection between the base integrated circuit chip 102 and another semiconductor device (eg, another integrated circuit chip, a printed circuit board, etc.) as well as to act as a physical barrier to crack propagation, to reduce Welding stress, and to reduce welding current density (eg, to slow down electromigration). In a particular implementation, wafer level package device 100 includes an array of twenty pillars 104 with high support peripheral structures, wherein the pillars are configured such that a second integrated circuit chip 106 can be placed in the array of pillars 104 . center.

Additionally, each post 104 may include a solder bump 112 disposed on one end of the post 104 configured to function as an electrical/mechanical connection to another semiconductor device. In these embodiments, the posts 104 extend at least partially into the solder bumps 112 to relieve thermal stress to the solder bumps 112 . In various implementations, the solder bumps 112 may be made of materials such as tin-silver-copper (Sn-Ag-Cu) alloy solder (ie, SAC), tin-silver (Sn-Ag) alloy solder, tin-copper (Sn -Cu) alloy solder, etc. made of lead-free solder components. In a number of implementations, the array of high-support peripheral studs 104 with solder bumps may include studs 104 configured to raise the solder bumps 112 to a height that is generally greater than the height of the second integrated circuit chip 106 . In these implementations, the raised solder bumps 112 may be configured to function as an electrical/mechanical connection to another semiconductor or electrical device (eg, a printed circuit board, an integrated circuit chip, etc.). Thus, while maintaining the inherent benefits in wafer level packaging (eg, lower cost, smaller package size, large pin count, etc.), wafer level package device 100 may provide for inclusion in a package similar to that provided by other devices Mechanical protection of the second integrated circuit chip 106 disposed between the high support peripheral pillars 104 with solder bumps 112 inside the device package. Additionally, the high support peripheral pillars 104 with solder bumps 112 may better enable compact 3D IC wafer level packaging and provide increased functionality.

As shown in FIGS. 1A and 1B , wafer level package device 100 includes a second integrated circuit chip 106 connected to base integrated circuit chip 102 . The second integrated circuit chip 106 may include one or more integrated circuits formed therein, which may include digital integrated circuits, analog integrated circuits, mixed-signal integrated circuits, combinations thereof, and the like. The second integrated circuit chip 106 may be connected to the base integrated circuit chip 102 in various ways. In some implementations and as illustrated in FIG. 1A , the second integrated circuit chip 106 may be connected to the base integrated circuit chip 102 using an adhesive compound. In these implementations, for example, the second integrated circuit chip 106 may be electrically connected to the base integrated circuit chip 102 using through silicon via technology ("TSV"). In other implementations, the second integrated circuit chip 106 may be electrically connected to the base integrated circuit chip 102 using wires. When the second integrated circuit chip 106 is attached to the base integrated circuit chip 102 using an adhesive, an array of solder bumps 108 may be provided on one side of the second integrated circuit chip 106 (eg, as opposed to being configured to be glued) attached to the side of the base integrated circuit chip 102), wherein the solder bumps 108 are configured to function as an electrical connection to another electrical or semiconductor device (eg, a printed circuit board, an integrated circuit chip, etc.). Additionally, the array of solder bumps 108 disposed on the second integrated circuit chip 106 may be located at approximately the same height as the solder bump(s) 112 disposed on the high support peripheral pillars 104 such that the second integrated circuit is disposed The solder bump(s) 108 on the chip 106 may be electrically connected to the same electrical or semiconductor device as the solder bumps 112 on the pillars 104 of the high support peripheral structure.

In other implementations and as illustrated in FIG. 1B , the second integrated circuit chip 106 may be connected to and in electrical communication with the base integrated circuit chip 102 using an array of solder bumps 108 and/or leads 114 . In this implementation, the second integrated circuit chip 106 may be connected to the base integrated circuit chip 102 and positioned in the center of the array of high support peripheral pillar(s) 104 . When the second integrated circuit chip 106 is connected to the base integrated circuit chip 102 using the array of solder bumps 108 , the surface of the second integrated circuit chip 106 may be located on the (plurality of) disposed on the (plurality of) high-support peripheral pillars 104 ) under the solder bumps 112. In various implementations, the second integrated circuit chip 106 may be electrically connected to the base integrated circuit using other methods or combinations of methods (eg, wires, solder bumps, TSVs, redistribution layers ("RDL"), etc.) Chip 102 or another electronic device. Placing the second integrated circuit chip 106 may include mounting over the surface of the base integrated circuit chip 102 and mounting to the surface of the base integrated circuit chip 102 . In some implementations, the second integrated circuit chip 106 may be positioned over electrical interconnect structures (eg, redistribution layers, solder ball arrays, leadframes, etc.) disposed on the base integrated circuit chip 102 while the first Two integrated circuit chips 106 are disposed in the center of the array of high support peripheral pillar(s) 104 .

As illustrated in FIG. 1B , wafer level package device 100 may include an underfill layer disposed in open spaces between second integrated circuit chip 106 and base integrated circuit chip 102 between these solder bumps 108 layer) 110. The underfill layer 110 may function to protect the solder bumps 108 and a portion of the second integrated circuit chip 106 from moisture, contaminants, and other environmental hazards. In various embodiments, the underfill layer 110 may mechanically connect the surface of the second integrated circuit chip 106 to the base integrated circuit chip 102 , thereby reducing the gap between expansion of the second integrated circuit chip 106 and the base integrated circuit chip 102 . difference. The underfill layer 110 also prevents the solder bumps 108 from being damaged by shear stresses caused by differences in thermal expansion of the second integrated circuit chip 106 and the base integrated circuit chip 102 . In various implementations, the underfill layer 110 includes a non-conductive material (eg, epoxy) disposed substantially under the second integrated chip 106 .

Multiple additional layers (eg, electrical interconnects, encapsulation layers, dielectric and/or passivation layers, and/or layers configured to serve as electrical/mechanical/structural support, encapsulation layers, etc.) may be integrated in the second In addition to the circuit chip 106 and the high support peripheral pillars 104 are added to the wafer level package device 100 . Further, the wafer level package device 100 may be singulated into individual semiconductor devices and connected to a printed circuit board (not shown) after formation of a plurality of additional layers, thereby forming an electronic device. Printed circuit boards may include electrical components (eg, the individual semiconductor devices) that are used to mechanically support and electrically connect electronic components (eg, the individual semiconductor devices) using conductive vias, tracks, or signal traces etched from copper sheets laminated to a non-conductive substrate circuit board. Thus, the second integrated circuit chip 106 imparts additional functionality to the wafer-level packaged device 100 by enabling system-in-a-package capability.

Example production process

FIG. 2 illustrates a process 200 employing wafer level packaging to fabricate an example of a semiconductor device including a second integrated circuit chip 106 disposed in the center of a plurality of high-support peripheral pillars 104 having solder bumps 112, A wafer level packaged device 100 such as shown in Figures 1A-1B. Figures 3A-3F illustrate a base integrated circuit chip 302, a second integrated circuit chip 306, and a high support peripheral used to fabricate an example of a semiconductor device, such as the wafer level packaged device 100 shown in Figures 1A and 1B Section 300 of an array of posts 304 .

Accordingly, the base integrated circuit chip is processed (block 202). 3A illustrates a portion of a base integrated circuit chip 302, which, after being processed by a suitable FEOL fabrication technique, includes a semiconductor substrate including one or more integrated circuits formed therein. Processing the base integrated circuit chip 302 may include processing a portion of a semiconductor wafer substrate, such as a silicon wafer (eg, p-type wafer, n-type wafer, etc.), germanium wafer, etc., that includes the semiconductor wafer substrate formed therein one or more integrated circuits. The integrated circuits being processed can be constructed in a variety of ways. For example, the integrated circuits being processed may be digital integrated circuits, analog integrated circuits, mixed-signal integrated circuits, and the like. The integrated circuits being processed are connected to one or more conductive layers (eg, bump interfaces, redistribution layers, etc.) that provide electrical contacts through which these integrated circuits are interconnected to the base integration Other elements associated with the circuit chip 302, such as a printed circuit board, a second integrated circuit chip 306, and the like. In one implementation, processing the base integrated circuit chip 302 includes processing a silicon wafer configured to receive a pick-and-placed second integrated circuit chip 306, wherein the silicon wafer has been processed using FEOL techniques.

At least one high support peripheral stud is formed on the base integrated circuit chip (block 204). FIG. 3B illustrates the formation of an array of high support peripheral posts 304 . The high bracing peripheral posts 304 may be formed using various methods. In one implementation, forming the high support peripheral studs 304 includes utilizing a suitable copper plating process. In another embodiment, forming the high support peripheral pillars 304 includes using a lamination/deposition process. The size, shape, and size of the high support peripheral pillars 304 may vary according to various design/fabrication considerations of the wafer level package device 100 . In implementations, the high support peripheral pillars 304 are formed generally to a height greater than the second integrated circuit chip 306 . When the second integrated circuit chip 306 is processed to have an array of solder bumps 308 on the side of the second integrated circuit chip 306 that is farthest from the base integrated circuit chip 302, the high support peripheral pillars 304 may have solder bumps therein Bumps 308 are formed at approximately the same height as solder bumps 312 . In one embodiment, the high support peripheral posts 304 may extend from the base integrated circuit chip 302 to a height of from about thirty-five micrometers (35 μm) to about sixty micrometers (60 μm). In certain implementations, the shape of the high bracing peripheral post 304 may include a cylindrical cross-section, a rectangular cross-section, or a trapezoidal cross-section.

Forming the high-support peripheral pillars 304 may include forming solder bumps 312 disposed on one end of the high-support peripheral pillars 304 (eg, the end opposite the base integrated circuit chip 302 ). In some embodiments, forming solder bumps 312 on posts 304 may include placing flux on posts 304 and positioning solder balls on posts 304 over the flux. The solder balls may be held by the flux to the pillars 304 until the wafer level package device 100 is subjected to a suitable reflow process. The solder balls are then reflowed over posts 304 to form solder bumps 312 .

Additionally, a plurality of solder bumps may be formed on the second integrated circuit chip (block 206). As illustrated in FIG. 3D , the second integrated circuit chip 306 may include solder bumps 308 configured to serve as electrical and/or electrical connections between the second integrated circuit chip 306 and another device such as the base integrated circuit chip 302 or mechanical connection. Forming the solder bumps 308 on the second integrated circuit chip 306 may include using a suitable deposition method (eg, solder paste printing, evaporation, electroplating, spraying, stud bumping, etc.). In one implementation, forming the solder bumps 308 includes applying solder paste to predetermined locations on the second integrated circuit chip 306, wherein the solder paste is configured to be subsequently reflowed and form the wafer level package device 100 and another component ( For example, a connection between a printed circuit board, another integrated circuit chip, etc.). In one implementation, the solder bumps 308 are formed on the second integrated circuit chip 306 using a ball drop process. In this implementation, at least one solid, pre-formed solder ball may be dropped using a ball drop process. In another embodiment, forming the at least one solder bump 308 on the second integrated circuit chip 306 includes placing a solder ball in liquid or molten form on the second integrated circuit chip 306 (eg, placed on the second integrated circuit chip 306 as a second integrated circuit) A portion of the chip 306 is included on the solder short tabs). In these embodiments, by heating the solder balls and the contact material, the solder balls may be bonded to the underlying second integrated circuit chip 306 to form the solder bumps 308 .

The second integrated circuit chip is placed on the base integrated circuit chip (block 208). The second integrated circuit chip 306 may be placed on the base integrated circuit chip 302 in a variety of ways. In some implementations, the second integrated circuit chip 306 may be placed using surface mount technology and a pick and place machine. In some implementations and as shown in FIG. 3D, the second integrated circuit chip 306 may be mounted using a die attach technique using an adhesive such as polyimide, epoxy, or silver filled glass. Mounted to the base integrated circuit chip 302 . In some implementations, the adhesive can be dispensed in a controlled amount onto the base integrated circuit chip 302 , and then the second integrated circuit chip 306 can be mounted to the base integrated circuit chip 302 . In other implementations, the adhesive may be dispensed on the second integrated circuit chip 306 in a controlled amount prior to placing the second integrated circuit chip 306 on the base integrated circuit chip 302 . In some implementations and as shown in Figure 3E, the second integrated circuit chip 306 may be placed on the base integrated circuit chip 302 using flip chip technology. In these implementations, placing or mounting the second integrated circuit chip 306 to a circuit (eg, a circuit board, base integrated circuit chip 302 , etc.) may include flipping the second integrated circuit chip 306 (eg, flip chip) such that The side with the electrical connections (eg, solder bumps 308 ) is face down, and the second integrated circuit chip 306 may be aligned such that its solder bumps 308 (or other electrical connection structures) are matching pad alignment. A subsequent reflow process can be used to melt the solder bumps and secure the solder to the bump interface. Additional processes may be used to place and mount the second integrated circuit chip 306 to the base integrated circuit chip 302 , such as wirebonding configured to establish an electrical connection between the second integrated circuit chip 306 and the base integrated circuit chip 302 At least one lead 314 that acts.

Next, an underfill layer may be formed between the second integrated circuit chip and the base integrated circuit chip (block 210). As shown in FIG. 3F, an underfill layer 310 may be formed in the open space between the second integrated circuit chip 306 and the base integrated circuit chip 302 (eg, between the solder bumps). Forming the underfill layer 310 may include pin distribution along the edge of the second integrated circuit chip 306 . Capillary action then draws the dispensed underfill material (eg, a non-conductive material such as a polymer or epoxy) inward until the open space is filled. Subsequently, thermal curing is performed to form a permanent bond.

The wafer-level packaged device 100 is then subjected to a singulation process (block 212) to singulate the wafer-level packaged device into individual stacked dies (eg, stacked semiconductor packaged devices). The singulation process may include utilizing conventional singulation techniques (chip sawing, scribe-and-break techniques, etc.).

in conclusion

Although the subject matter has been described in language directed to structural features and/or process operations, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features or acts described above are disclosed as example forms of implementing these claims.

Claims (20)

1. A wafer-level packaged device comprising: Basic integrated circuit chip devices; at least one post formed on the first side of the base integrated circuit chip device, wherein the at least one post has a high support peripheral structure and includes at least one solder bump formed on the post; and a second integrated circuit chip device electrically connected to the first side of the base integrated circuit chip device, the second integrated circuit chip device being disposed in the center of the at least one post having a high support peripheral structure, wherein the The second integrated circuit chip device includes at least one solder bump formed on a side remote from the first side of the base integrated circuit chip device, wherein the second integrated circuit chip device is connected to the base integrated circuit chip device using an adhesive compound The basic integrated circuit chip device. 2. The wafer level package device of claim 1, wherein the base integrated circuit chip comprises a silicon wafer. 3. The wafer level package device of claim 1, wherein the at least one pillar comprises at least one copper pillar. 4. The wafer level package device of claim 1, wherein the second integrated circuit chip device is adhesively attached to the base integrated circuit chip and is included on a side facing away from the base integrated circuit chip of at least one solder bump. 5. The wafer level package device of claim 1, wherein the second integrated circuit chip device is connected to the base integrated circuit chip in an array of solder bumps. 6. The wafer level package device of claim 5, further comprising an underfill layer disposed between the base integrated circuit chip device and the second integrated circuit chip, wherein the underfill layer surrounds the solder Bump array. 7. The wafer level package device of claim 6, wherein the underfill layer comprises epoxy. 8. An electronic device comprising: printed circuit boards; and A wafer level package device connected to the printed circuit board, the wafer level package device comprising Basic integrated circuit chip devices; at least one post formed on the first side of the base integrated circuit chip device, wherein the at least one post has a high support peripheral structure and includes at least one solder bump formed on the post; and a second integrated circuit chip device electrically connected to a first side of the base integrated circuit chip, the second integrated circuit chip disposed in the center of the at least one post having a high support peripheral structure, wherein the first integrated circuit chip A second integrated circuit chip device includes at least one solder bump formed on a side remote from a first side of the base integrated circuit chip device, wherein the second integrated circuit chip device is attached to the second integrated circuit chip device using an adhesive compound Basic integrated circuit chip device. 9. The wafer level package device of claim 8, wherein the base integrated circuit chip comprises a silicon carrier wafer. 10. The wafer level package device of claim 8, wherein the at least one pillar comprises at least one copper pillar. 11. The wafer level package device of claim 8, wherein the second integrated circuit chip device is adhesively attached to the base integrated circuit chip and is included on a side facing away from the base integrated circuit chip of at least one solder bump. 12. The wafer level package device of claim 8, wherein the second integrated circuit chip device is connected to the base integrated circuit chip in an array of solder bumps. 13. The wafer level package device of claim 12, further comprising an underfill layer disposed between the base integrated circuit chip device and the second integrated circuit chip, wherein the underfill layer surrounds the solder Bump array. 14. The wafer level package device of claim 13, wherein the underfill layer comprises epoxy. 15. A process method comprising: forming at least one stud on the first side of the processed base integrated circuit chip, wherein the at least one stud has a high support peripheral structure, the at least one stud includes a solder bump; placing a second integrated circuit chip device on the first side of the base integrated circuit chip device, wherein the second integrated circuit chip is positioned in the center of the at least one post having a high support peripheral structure, wherein, The second integrated circuit chip device includes at least one solder bump formed on a side remote from the first side of the base integrated circuit chip device. 16. The process of claim 15, wherein processing the first integrated circuit chip comprises processing a silicon wafer. 17. The process of claim 15, wherein forming the at least one pillar includes forming at least one copper pillar. 18. The process of claim 15, wherein placing the second integrated circuit chip comprises placing the second integrated circuit chip on the base integrated circuit chip with an adhesive. 19. The process of claim 18, wherein placing the second integrated circuit chip on the base integrated circuit chip with an adhesive comprises placing an array of solder bumps on the second integrated circuit chip on the side facing away from the base integrated circuit chip. 20. The process of claim 15, wherein placing the second integrated circuit chip comprises placing the second integrated circuit chip on the base integrated circuit chip using an array of solder bumps.

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