TWI885507B - Semiconductor package and fabricating method thereof - Google Patents

Abstract

A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

Description

Semiconductor package and method for manufacturing the same

This application relates to a semiconductor package and a method for manufacturing the same.

Cross-reference/Incorporation of Related Applications

This application is related to U.S. Patent Application Serial No. 13/753,120 filed on January 29, 2013 and entitled "Semiconductor Device and Method for Making the Same"; U.S. Patent Application Serial No. 13/863,457 filed on April 16, 2013 and entitled "Semiconductor Device and Method for Making the Same"; and U.S. Patent Application Serial No. 13/863,457 filed on November 19, 2013 and entitled "Half-well having through-silicon via-less deep well" No. 14/083,779, filed on March 18, 2014, entitled "Semiconductor device and method of making the same"; No. 14/218,265, filed on March 18, 2014, entitled "Semiconductor device and method of making the same"; No. 14/313,724, filed on June 24, 2014, entitled "Semiconductor device and method of making the same"; No. 14/313,724, filed on July 28, 2014, entitled "Semiconductor device and method of making the same"; U.S. Patent Application Serial No. 14/444,450, filed on October 27, 2014, entitled "Semiconductor Device with Reduced Thickness"; U.S. Patent Application Serial No. 14/524,443, filed on November 4, 2014, entitled "Interposer, Method of Making Same, Semiconductor Package Using Same, and Method for Making the Same" No. 14/532,532; U.S. patent application Ser. No. 14/546,484, filed on Nov. 18, 2014, and entitled “Semiconductor device with reduced warp”; and U.S. patent application Ser. No. 14/671,095, filed on Mar. 27, 2015, and entitled “Semiconductor device and method of making the same”; the contents of each of these U.S. patent applications are hereby incorporated by reference in their entirety.

Current semiconductor packages and methods for forming semiconductor packages are inadequate, for example resulting in excessive cost, reduced reliability, or excessive package size. Further limitations and disadvantages of such known and conventional approaches will become apparent to those skilled in the art through comparison of such known and conventional approaches with the present disclosure as described in the remainder of the referenced drawings of this application.

Various features of this disclosure provide a semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various features of this disclosure provide various semiconductor package structures and methods for manufacturing the same, which include a thin fine-pitch redistribution structure.

The following discussion presents various features of the present disclosure by providing various examples of such features. Such examples are non-limiting, and thus the scope of the various features of the present disclosure should not be necessarily limited to any particular features of the examples provided. In the following discussion, the terms "for example," "for example," and "exemplary" are non-limiting and are generally synonymous with "exemplary and non-limiting," "for example and non-limiting," and the like.

As used herein, "and/or" means any one or more of the items added by "and/or" in a list. For example, "x and/or y" means any one of the three-element set {(x), (y), (x, y)}. In other words, "x and/or y" means "one or both of x and y." As another example, "x, y, and/or z" means any one of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y, and/or z" means "one or more of x, y, and z."

The terms used herein are for the purpose of describing specific examples only and are not intended to limit the present disclosure. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. It will be further understood that when the terms "include", "comprise", "have", and the like are used in this specification, they specify the presence of the features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

It will be appreciated that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish one element from another element. Therefore, for example, a first element, a first component or a first section discussed below may be referred to as a second element, a second component or a second section without departing from the teaching of this disclosure. Similarly, various spatial terms such as "above", "below", "side" and the like may be used in a relative manner to distinguish one element from another element. However, it should be appreciated that components may be oriented in different ways, such as a semiconductor device may be turned to the side, so that its "top" surface is horizontally oriented, and its "side" surface is vertically oriented without departing from the teaching of this disclosure.

Various features of the present disclosure provide a semiconductor device or package and a method of manufacturing the same that can reduce cost, improve reliability, and/or improve the manufacturability of the semiconductor device.

The above features and other features of the present disclosure will be described in the following various exemplary embodiments, or will be apparent from the description. The various features of the present disclosure will now be presented with reference to the attached drawings so that those skilled in the art can easily implement the various features.

Figures 1A-1J are cross-sectional views showing a semiconductor package and a method for making a semiconductor package according to various features of the present disclosure. The structures shown in Figures 1A-1J can share any or all features with similar structures shown in Figures 3A-3B, 4A-4D, 5A-5F, 6A-6D, 7A-7L, 9, 10A-10B, 11A-11D, 12A-12B, 13, 14, 15 and 16. Figure 2 is a flow chart of a method 200 for making a semiconductor package according to various features of the present disclosure. Figures 1A-1K can, for example, depict a semiconductor package of various steps (or blocks) of the method 200 of Figure 2. 1A-1K and FIG. 2 will now be discussed together. It should be noted that the order of the blocks of the example of method 200 may be varied without departing from the scope of this disclosure.

The example method 200 may include preparing a logic wafer for processing (eg, for packaging) at block 205. Block 205 may include preparing a logic wafer for processing in any of a variety of ways, non-limiting of which are presented herein.

For example, block 205 may include receiving a logic wafer, such as a shipment from a supplier, from an upstream process at a manufacturing location, etc. The logic wafer may include, for example, a semiconductor wafer including a plurality of active semiconductor dies. The semiconductor dies may include, for example, a processor die, a memory die, a programmable logic die, a special application integrated circuit die, a general logic die, etc.

Block 205 may, for example, include forming a conductive interconnect structure on the logic wafer. Such a conductive interconnect structure may, for example, include a conductive pad, land, bump or ball, conductive pillar, etc. The forming may, for example, include attaching a pre-formed interconnect structure to the logic wafer, electroplating the interconnect structure on the logic wafer, etc.

In an exemplary embodiment, the conductive structures may include conductive pillars (including copper and/or nickel) and may include a solder cap (including tin and/or silver, for example). For example, a conductive structure including a conductive pillar may include: (a) an under bump metallization ("UBM") structure including (i) a titanium-tungsten (TiW) layer formed by sputtering (which may be referred to as a "seed layer"), and (ii) a copper (Cu) layer formed by sputtering on the titanium-tungsten layer; (b) a copper pillar formed by electroplating on the UBM; and (c) a solder layer formed on the copper pillar, or a nickel layer formed on the copper pillar and a solder layer formed on the nickel layer.

Furthermore, in an exemplary embodiment, the conductive structures may include a lead and/or lead-free wafer bump. For example, the lead-free wafer bump (or interconnect structure) may be formed at least in part by: (a) forming an under bump metallization (UBM) structure by (i) forming a titanium (Ti) or titanium-tungsten (TiW) layer by sputtering, (ii) forming a copper (C) on the titanium or titanium-tungsten layer by sputtering, and (iii) forming a copper (C) on the titanium or titanium-tungsten layer by sputtering. (i) forming a nickel (Ni) layer on the copper layer by electroplating; and (b) forming a lead-free solder material on the nickel layer of the UBM structure by electroplating, wherein the lead-free solder material has a composition of 1 to 4% by weight of silver (Ag), and the remainder of the composition by weight is tin (Sn).

Block 205 may, for example, include performing partial or full thinning (e.g., grinding, etching, etc.) of the logic wafer. Block 205 may, for example, also include dicing the logic wafer into individual die or groups of die for subsequent mounting. Block 205 may also include receiving the logic wafer from an adjacent or upstream manufacturing station in a manufacturing facility, from another geographical location, etc. The received logic wafer may, for example, have already been prepared, or additional preparation steps may be performed.

Generally, block 205 may include preparing a logic wafer for processing (eg, for packaging). Thus, the scope of this disclosure should not be limited to the features of a particular type of logic wafer and/or die processing.

The exemplary method 200 may include preparing a carrier, substrate, or wafer at block 210. The prepared (or received) wafer may be referred to as a redistributed structure wafer or RD wafer. Block 210 may include preparing an RD wafer for processing in any of a variety of ways, non-limiting examples of which are presented herein.

The RD wafer may, for example, include an interposer wafer, a wafer of a packaging substrate, and the like. The RD wafer may, for example, include a redistributed structure formed (for example, in a die-by-die manner) on a semiconductor (for example, silicon) wafer. The RD wafer may, for example, include only electrical paths but not electronic devices (for example, semiconductor devices). The RD wafer may, for example, also include passive electronic devices but not active semiconductor devices. For example, the RD wafer may include one or more conductive layers or circuits that are formed on a substrate or carrier (for example, directly or indirectly thereon) or coupled to a substrate or carrier. Examples of the carrier or substrate may include a semiconductor (for example, silicon) wafer or a glass substrate. Examples of processes used to form conductive layers (e.g., copper, aluminum, tungsten, etc.) on a semiconductor wafer include utilizing semiconductor wafer processes, which may also be referred to herein as back-end of line (BEOL). In one exemplary implementation, the conductive layers may be deposited on or over a substrate using a sputtering and/or electroplating process. The conductive layers may be referred to as redistribution layers. The redistribution layers may be used to route an electrical signal between two or more electrical connections and/or route an electrical connection to a wider or narrower spacing.

In one exemplary embodiment, various portions of the redistribution structure (e.g., interconnect structures (e.g., planes, lines, etc.) that can be attached to an electronic device) can be formed with a sub-micron pitch (or center-to-center spacing) and/or less than a 2 micron pitch. In various other embodiments, a 2-5 micron pitch can be utilized.

In one example implementation, a silicon wafer on which the redistribution structure is formed may include lower grade silicon than can be fully utilized to form semiconductor dies that are ultimately attached to the redistribution structure. In another example implementation, the silicon wafer may be a recycled silicon wafer from a failed semiconductor device wafer fabrication. In another example implementation, the silicon wafer may include a thinner silicon layer than can be fully utilized to form semiconductor dies that are ultimately attached to the redistribution structure. Block 210 may also include receiving the RD wafer from an adjacent or upstream manufacturing station in a manufacturing facility, from another geographical location, and the like. The received RD wafer may, for example, have already been prepared, or additional preparation steps may be performed.

FIG. 1A is a diagram that provides an example of various features of a block 210. Referring to FIG. 1A, the RD wafer 100A may include, for example, a supporting layer 105 (e.g., a silicon or other semiconductor layer, a glass layer, etc.). A redistribution (RD) structure 110 may be formed on the supporting layer 105. The RD structure 110 may include, for example, a base dielectric layer 111, a first dielectric layer 113, a first conductive line 112, a second dielectric layer 116, a second conductive line 115, and an interconnect structure 117.

The base dielectric layer 111 may be, for example, on the support layer 105. The base dielectric layer 111 may include, for example, an oxide layer, a nitride layer, etc. The base dielectric layer 111 may be, for example, formed according to specifications and/or may be natural. The dielectric layer 111 may be referred to as a protective layer. For example, the dielectric layer 111 may be a silicon dioxide layer formed using a low pressure chemical vapor deposition (LPCVD) process, or may include the silicon dioxide layer.

The RD wafer 100A may also include, for example, first conductive lines 112 and a first dielectric layer 113. The first conductive lines 112 may include, for example, deposited conductive metals (e.g., copper, aluminum, tungsten, etc.). The conductive lines 112 may be formed by sputtering and/or electroplating. The conductive lines 112 may be formed, for example, at a sub-micron or sub-two-micron spacing (or center-to-center spacing). The first dielectric layer 113 may include, for example, an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). It is noted that in various embodiments, the dielectric layer 113 may be formed before the first conductive lines 112, for example, being formed with holes, which are then filled with the first conductive lines 112 or a portion thereof. In one example implementation including copper conductive lines, for example, a dual damascene process may be utilized to deposit the lines.

In an alternative assembly, the first dielectric layer 113 may include an organic dielectric material. For example, the first dielectric layer 113 may include bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzo cyclo butene (BCB), poly benz oxazole (PBO), epoxy resin, and equivalents thereof and combinations thereof, but the features of the present disclosure are not limited thereto. The organic dielectric material may be formed by any of a variety of methods, such as chemical vapor deposition (CVD). In such an alternative assembly, the first conductive lines 112 may be, for example, spaced at a 2-5 micron pitch (or center-to-center spacing).

The RD wafer 100A may also include, for example, second conductive lines 115 and a second dielectric layer 116. The second conductive lines 115 may include, for example, deposited conductive metals (e.g., copper, etc.). The second conductive lines 115 may, for example, be connected to the respective first conductive lines 112 through respective conductive vias 114 (e.g., in the first dielectric layer 113). The second dielectric layer 116 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the second dielectric layer 116 may include an organic dielectric material. For example, the second dielectric layer 116 may include bis(maleic acid) imide/trinitrogen well (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy resin, and equivalents and compounds thereof, but the features of the present disclosure are not limited thereto. The second dielectric layer 116 may be formed, for example, by a CVD process, but the scope of the present disclosure is not limited thereto.

Although two sets of dielectric layers and conductive lines are depicted in FIG. 1A , it should be understood that the RD structure 110 of the RD wafer 100A may include any number of such layers and lines. For example, the RD structure 110 may include only one dielectric layer and/or multiple sets of conductive lines, three sets of dielectric layers and/or conductive lines, and so on.

As with the logic wafer fabrication in block 205, block 210 may include forming interconnect structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive planes or pads, etc.) on a surface of the RD structure 110. An example of such an interconnect structure 117 is shown in FIG. 1A, where the RD structure 110 includes an interconnect structure 117, which is shown as being formed on the front (or top) side of the RD structure 110 and electrically connected to respective second conductive lines 115 through conductive vias in the second dielectric layer 116. Such an interconnect structure 117 may be utilized, for example, to couple the RD structure 110 to various electronic components (e.g., active semiconductor components or dies, passive components, etc.).

The interconnect structures 117 may include, for example, any one of various conductive materials (eg, any one or a combination of copper, nickel, gold, etc.). The interconnect structures 117 may also include, for example, solder.

Generally speaking, block 210 may include fabricating a redistributed structure wafer (RD wafer). Thus, the scope of this disclosure should not be limited to the features of any particular manner of performing such fabrication.

The example method 200 may include forming an interconnect structure (eg, a through mold via (TMV) interconnect structure) on the RD wafer at block 215. Block 215 may include forming such an interconnect structure in any of a variety of ways.

The interconnect structures may include any of a variety of features. For example, the interconnect structures may include solder balls or bumps, multi-spherical solder pillars, elongated solder balls, metal (e.g., copper) core balls with a solder layer over a metal core, electroplated pillar structures (e.g., copper pillars, etc.), wire structures (e.g., wirebond wires), and the like.

The interconnect structures may include any of a variety of sizes. For example, the interconnect structures may extend from the RD wafer to a height that is less than the height of the electronic components coupled to the RD wafer (e.g., in block 220). Also, for example, the interconnect structures may extend from the RD wafer to a height that is greater than or equal to the height of the electronic components coupled to the RD wafer. The importance of such relative heights will become apparent in the discussion herein (e.g., in discussions of mold thinning, package stacking, top substrate attachment, formation of top redistribution structures, etc.). The interconnect structures may also be formed, for example, at various spacings (or center-to-center spacings). For example, the interconnect structures (e.g., conductive posts or columns) may be plated and/or bonded at a spacing of 150-250 microns or less. Also for example, the interconnect structures (e.g., elongated and/or metal-filled solder structures) can be attached at a pitch of 250-350 microns or less. Also for example, the interconnect structures (e.g., solder balls) can be attached at a pitch of 350-450 microns or less.

Block 215 may include attaching the interconnect structures in any of a variety of ways. For example, block 215 may include reflow attaching interconnect structures on the RD wafer, electroplating interconnect structures on the RD wafer, wire bonding interconnect structures on the RD wafer, using a conductive epoxy to attach pre-formed interconnect structures to the RD wafer, and the like.

1B provides an example of various features (e.g., features formed by interconnect structures) of block 215. In the example assembly 100B, interconnect structures 121 (e.g., solder balls) are attached (e.g., reflow attached, attached using a solder ball drop process, etc.) to RD structures 110 of the RD wafer 100A.

Although two rows of interconnect structures 121 are shown, various implementations may include a single row, three rows, or any number of rows. As will be discussed herein, various example implementations may not have such an interconnect structure 121, and therefore block 215 may be included in the example method 200.

Note that, although in the example method 200, the block 215 is performed before the wafer molding operation of the block 230, the interconnect structures may alternatively be formed after the wafer molding operation (e.g., forming vias in the molding material and then filling such vias with a conductive material). Also note that, as shown in FIG. 2, the block 215 may be performed after the die attach operation of the block 220, for example, rather than before the die attach.

Generally speaking, block 215 may include forming interconnect structures on the RD wafer. Thus, the scope of this disclosure should not be limited to the features of a particular type of interconnect structure, or to the features of any particular manner of forming such an interconnect structure.

The example method 200 may include attaching one or more semiconductor dies to the RD structure (e.g., the RD structure of the RD wafer) at block 220. Block 220 may include attaching the die to the RD structure in any of a variety of ways, non-limiting examples of which are provided herein.

The semiconductor die may include features of any of a variety of types of semiconductor die. For example, the semiconductor die may include a processor die, a memory die, a special application integrated circuit die, a general logic die, an active semiconductor component, etc.) Note that passive components may also be attached to block 220.

Block 220 may include attaching the semiconductor die (e.g., as prepared in block 205) in any of a variety of ways. For example, block 220 may include attaching the semiconductor die using mass reflow, thermocompression bonding (TCB), conductive epoxy, etc.

1B is a diagram that provides an example of various features (e.g., die attach features) of block 220. For example, a first die 125 (e.g., which may have been diced from a logic wafer fabricated in block 205) is electrically and mechanically attached to the redistribution structure 110. Similarly, a second die 126 (e.g., which may have been diced from a logic wafer fabricated in block 205) is electrically and mechanically attached to the redistribution structure 110. For example, as illustrated at block 205, the logic wafer (or die thereof) may have been prepared with various interconnect structures (e.g., conductive pads, planes, bumps, balls, wafer bumps, conductive pillars, etc.) formed thereon. Such structures are generally shown in FIG. 1B as item 119. Block 220 may include, for example, utilizing any of a variety of attachment processes (e.g., batch reflow, thermal compression bonding (TCB), conductive epoxy, etc.) to electrically and mechanically attach such interconnect structures to the redistribution structure 110.

The first die 125 and the second die 126 may include any of a variety of die characteristics. In one example scenario, the first die 125 may include a processor die, and the second die 126 may include a memory die. In another example scenario, the first die 125 may include a processor die, and the second die 126 may include a co-processor die. In another example scenario, the first die 125 may include a sensor die, and the second die 126 may include a sensor processing die. Although the assembly 100B of FIG. 1B is shown as having two dies 125, 126, it may have any number of dies. For example, it may have only one die, three dies, four dies, or more than four dies.

In addition, although the first die 125 and the second die 126 are shown as being attached to the redistribution structure 110 laterally relative to each other, they may also be configured in a vertical assembly. Various non-limiting examples of such structures are shown and discussed herein (e.g., die-on-die stacking, die attached to opposite substrate sides, etc.). Furthermore, although the first die 125 and the second die 126 are shown as having substantially similar sizes, such dies 125, 126 may include different individual features (e.g., die height, footprint, connection pitch, etc.).

The first die 125 and the second die 126 are depicted as having substantially uniform pitches, but this is not necessarily the case. For example, most or all of the contacts 119 of the first die 125 in an area of the first die coverage area adjacent to the second die 126 and/or most of the contacts 119 of the second die 126 in an area of the second die coverage area adjacent to the first die 125 may have substantially finer pitches than most or all of the other contacts 119. For example, the first 5, 10, or n rows of contacts 119 of the first die 125 closest to the second die 126 (and/or the second die 126 closest to the first die 125) may have a pitch of 30 microns, while the other contacts 119 may have a pitch of approximately 80 microns and/or 200 microns. The RD structure 110 may thus have corresponding contact structures and/or lines at the corresponding spacing.

Generally, block 220 includes attaching one or more semiconductor dies to the redistribution structure (e.g., a redistribution structure of a redistribution wafer). Thus, the scope of this disclosure should not be limited to the characteristics of any particular die, or to the characteristics of any particular multi-die layout, or to the characteristics of any particular manner of attaching such dies, etc.

The example method 200 may include underfilling (underfilling) semiconductor dies and/or other components attached to the RD structure at block 220 at block 225. Block 225 may include performing such underfilling in any of a variety of ways, non-limiting examples of which are presented herein.

For example, after die attachment in block 220, block 225 may include underfilling the semiconductor die using a capillary underfill. For example, the underfill may include a sufficiently viscous reinforced polymer material that flows between the attached die and the RD wafer in a capillary action.

Also for example, block 225 may include filling the semiconductor die with a non-conductive paste (NCP) and/or a non-conductive film (NCF) or tape underfill while the die is being attached (e.g., using a thermocompression bonding process) in block 220. For example, such underfill material may be deposited (e.g., printed, sprayed, etc.) prior to attaching the semiconductor die.

As with all blocks depicted in the example method 200, block 225 may be performed anywhere in the flow of the method 200 as long as the space between the die and the redistribution structure is accessible.

The underfill may also occur at a different area of the example method 200. For example, the underfill may be performed as part of the wafer molding area 230 (eg, using a molding underfill).

1B is a diagram providing an example of various features (e.g., features of the underfill) of the block 225. The underfill 128 is disposed between the first semiconductor die 125 and the redistribution structure 110, and between the second semiconductor die 126 and the redistribution structure 110, for example, around the contacts 119.

Although the underfill 128 is depicted as being generally flat, the underfill can rise and form fillets on the sides of the semiconductor die and/or other components. In one example scenario, at least a quarter or at least half of the side surfaces of the die can be covered with the underfill material. In another example scenario, one or more or all of the entire side surfaces can be covered with the underfill material. Similarly, for example, a substantial portion of the space directly between the semiconductor die, between the semiconductor die and other components, and/or between other components can be filled with the underfill material. For example, at least half of the space between laterally adjacent semiconductor dies, between the die and other components, and/or between other components, or all of the space can be filled with the underfill material. In an exemplary implementation, the underfill 128 can cover the entire redistributed structure 110 of the RD wafer. In such an exemplary implementation, when the RD wafer is subsequently cut, such cutting can also cut through the underfill 128.

Generally, area 225 may include an underfill to attach semiconductor die and/or other components to the RD structure in area 220. Thus, the scope of this disclosure should not be limited to any particular type of underfill or the characteristics of any particular manner of performing such underfill.

The example method 200 may include molding the RD wafer (eg, or an RD structure) at block 230. Block 230 may include molding the RD wafer in any of a variety of ways, non-limiting examples of which are presented herein.

For example, block 230 may include a molded-on top surface of the RD wafer, on a die and/or other component attached to block 220, on an interconnect structure (e.g., a conductive sphere, ellipse, pillar or column (e.g., electroplated pillars, wires or bonding wires, etc.), etc.) formed in block 215, on a primer fill formed in block 225, and the like.

Block 230 may include, for example, compression molding (eg, using liquid, powder and/or film), or vacuum molding. Also, for example, block 230 may include a transfer molding process (eg, a wafer-level transfer molding process).

The molding material may include any of a variety of characteristics, for example. For example, the molding material (e.g., epoxy molding compound (EMC), epoxy molding compound, etc.) may include a relatively high modulus, such as to provide wafer support during a subsequent process. Similarly, the molding material may include a relatively low modulus to provide wafer flexibility during a subsequent process.

As explained herein, for example, with respect to block 225, the molding process of block 230 can provide an underfill between the die and the RD wafer. In such an example, there can be a uniform material between the underfill material of the molding and the molding material encapsulating the semiconductor die.

1C is a diagram that provides an example of various features (e.g., molding features) of block 230. For example, molded assembly 100C is shown where molding material 130 covers the top surfaces of interconnect structures 121, first semiconductor die 125, second semiconductor die 126, underfill 128, and redistribution structure 110. Although the molding material 130 (which may also be referred to herein as encapsulation material) is shown as completely covering the sides and tops of the first semiconductor die 125 and second semiconductor die 126, this is not necessarily the case. For example, block 230 may include a molding technique utilizing a film-assisted or die-sealed molding technique to keep the tops of the die free of molding material.

In general, the molding material 130 may, for example, directly contact and cover the portions of the dies 125, 126 that are not covered by the underfill 128. For example, in a scenario where at least a first portion of the sides of the dies 125, 126 are covered by the underfill 128, the molding material 130 may directly contact and cover a second portion of the sides of the dies 125, 126. The molding material 130 may, for example, also fill the space between the dies 125, 126 (e.g., at least a portion of the space that has not yet been filled with the underfill 128).

Generally speaking, block 230 may include molding the RD wafer. Thus, the scope of this disclosure should not be limited to the features of any particular molding material, structure and/or technique.

The example method 200 may include, at block 235, grinding (or thinning) the molding material applied at block 230. Block 235 may include grinding (or thinning) the molding material in any of a variety of ways, non-limiting examples of which are presented herein.

Block 235 may include, for example, mechanically grinding the molding material to thin the molding material. Such thinning may, for example, leave the die and/or interconnect structures as overmolded, or such thinning may expose one or more die and/or one or more interconnect structures.

Block 235 may, for example, include grinding other components in addition to the mold compound. For example, block 235 may include grinding the top side (e.g., the back side or the inactive side) of the die to which block 220 is attached. Block 235 may, for example, also include grinding the interconnect structure formed in block 215. In addition, in a scenario where the primer fill applied in block 225 or block 230 is sufficiently extended upward, block 235 may also include grinding such primer fill material. Such grinding may, for example, produce a flat planar surface at the top of the material being ground.

Block 235 may, for example, be skipped in a scenario where the height of the molding material is originally formed at a desired thickness.

FIG1D is a diagram that provides an example of various features (e.g., the mold grinding features) of block 235. Assembly 100D is depicted in which the molding material 130 (e.g., relative to the molding material 130 depicted in FIG1C) is thinned to expose the top surfaces of the dies 125, 126. In this example, the dies 125, 126 may also have been ground (or thinned).

Although as depicted in FIG1D , the top surface of the molding material is above the interconnect structures 121 and thus the interconnect structures 121 are not ground, the interconnect structures 121 may be ground. Such an exemplary embodiment may, for example, produce a top surface at this stage that includes a top surface of the die 125, 126, a top surface of the molding material 130, and a top surface of the interconnect structure 121, all of which are on a common plane.

As explained herein, the molding material 130 can be retained in an overmold configuration to cover the die 125, 126. For example, the molding material 130 can be unmilled, or the molding material 130 can be milled, but not to a height that exposes the die 125, 126.

Generally speaking, the area 235 may include grinding (or thinning) the molding material applied in the area 230. Thus, the scope of this disclosure should not be limited to any particular grinding (or thinning) amount or type of features.

The example method 200 may include, at block 240, stripping the molding material applied at block 230. Block 240 may include stripping the molding material in any of a variety of ways, non-limiting examples of which are provided herein.

As discussed herein, the molding material may cover the interconnect structures formed in block 215. If the molding material covers the interconnect structures, and the interconnect structures need to be exposed (e.g., for subsequent package attachment, top-side redistribution layer formation, top-side build-up substrate attachment, electrical connection, heat sink connection, electromagnetic shielding connection, etc.), block 240 may include stripping the molding material to expose the interconnect structures.

Block 240 may include, for example, laser etching through the molding material to expose the interconnect structures. Also for example, block 240 may include soft beam drilling, mechanical drilling, chemical drilling, etc.

1D is an illustration of an example of various features (e.g., the etch features) of the block 240. For example, the assembly 100D is shown to include etched through holes 140 extending through the molding material 130 to the interconnect structure 121. Although the etched through holes 140 are shown as having vertical sidewalls, it should be understood that the through holes 140 may include any of a variety of shapes. For example, the sidewalls may be sloped (e.g., having a larger opening at the top surface of the molding material 130 than at the interconnect structure 121).

Although block 240 is depicted in FIG2 as immediately following wafer molding of block 230 and mold grinding of block 235, block 240 may be performed at any point later in the method 200. For example, block 240 may be performed after the wafer support structure (e.g., to which block 245 is attached) is removed.

Generally, area 240 may include etching away molding material applied at area 230 (e.g., to expose interconnect structures formed at area 215). Thus, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing such etching or to the characteristics of any particular etched through-hole structure.

The example method 200 may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure at block 245. Block 245 may include attaching the molded RD wafer to the wafer support structure in any of a variety of ways, non-limiting examples of which are provided herein.

The wafer support structure may include, for example, a wafer or fixture formed of silicon, glass, or various other materials (e.g., dielectric materials). Block 245 may include, for example, utilizing an adhesive, a vacuum fixture, etc. to attach the molded RD wafer to the wafer support structure. Note that, as depicted and illustrated herein, a redistribution structure may be formed on the top side (or backside) of the die and molding material prior to attachment of the wafer support.

1E is a diagram that provides an example of various features (e.g., wafer support attachment features) of block 245. Wafer support structure 150 is attached to the molding material 130 and the top sides of the dies 125, 126. The wafer support structure 150 may be attached, for example, using an adhesive, and such adhesive may also be formed in the through holes 140 and contact the interconnect structures 121. In another example assembly, the adhesive does not enter the through holes 140 and/or does not contact the interconnect structures 121. Note that in an assembly where the tops of the dies 125 , 126 are covered with molding material 130 , the wafer support structure 150 may only be directly coupled to the tops of the molding material 130 .

Generally, block 245 may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Thus, the scope of this disclosure should not be limited to the features of any particular type of wafer support structure or to the features of any particular manner of attaching a wafer support structure.

The example method 200 may include removing a support layer from the RD wafer at block 250. Block 250 may include removing the support layer in any of a variety of ways, non-limiting examples of which are presented herein.

As discussed herein, the RD wafer may include a supporting layer on which an RD structure is formed and/or supported. The supporting layer may, for example, include a semiconductor material (e.g., silicon). In an example scenario in which the supporting layer includes a silicon wafer layer, block 250 may include removing the silicon (e.g., removing all of the silicon from the RD wafer, removing substantially all of the silicon from the RD wafer (e.g., at least 90% or 95%), etc.). For example, block 250 may include mechanically grinding substantially all of the silicon, followed by a dry or wet chemical etch to remove the remaining portion (or substantially all of the remaining portion). In an example scenario where the support layer is loosely attached to the RD structure formed (or carried) thereon, block 250 may include pulling or peeling to separate the support layer from the RD structure.

1F is a diagram providing an example of various features (e.g., support layer removal features) of block 250. For example, the support layer 105 (shown in FIG. 1E ) is removed from the RD structure 110. In the illustrated example, the RD structure 110 may still include a base dielectric layer 111 (e.g., an oxide, nitride, etc.) as discussed herein.

Generally, block 250 may include removing a support layer from the RD wafer. Thus, the scope of this disclosure should not be limited to the characteristics of any particular type of wafer material or to the characteristics of any particular manner of wafer material removal.

The exemplary method 200 may include forming and patterning a first redistribution layer (RDL) dielectric layer for etching an oxide layer of the RD structure at block 255. Block 255 may include forming and patterning the first RDL dielectric layer in any of a variety of ways, non-limiting examples of which are presented herein.

In the examples generally discussed herein, the RD structures of the RD wafer are generally formed on an oxide layer (or nitride or other dielectric). To enable metal-to-metal attachment to the RD structure, portions of the oxide layer covering the lines (or pads or planes) of the RD structure may be removed, for example, by etching. Note that the oxide layer does not necessarily need to be removed or completely removed, as long as it has acceptable conductivity.

The first RDL dielectric layer may, for example, include a polyimide or a polybenzoxazole (PBO) material. The first RDL dielectric layer may, for example, include a stack of films or other materials. The first RDL dielectric layer may, for example, generally include an organic material. However, in various exemplary embodiments, the first RDL dielectric layer may include an inorganic material.

In an exemplary implementation, the first RDL dielectric layer may include an organic material (eg, polyimide, PBO, etc.) formed on a first side of a base dielectric layer of the RD structure, which may include an oxide or nitride or other dielectric materials.

The first RDL dielectric layer may be used, for example, as a mask for etching a base dielectric layer such as an oxide or nitride layer (e.g., at block 260). Also, for example, after etching, the first RDL dielectric layer may remain, for example, to be used to form conductive RDL lines thereon.

In an alternative example scenario (not shown), a temporary mask layer (e.g., a temporary photoresist layer) may be utilized. For example, after etching, the temporary mask layer may be removed and replaced by a permanent RDL dielectric layer.

1G is a diagram providing an example of various features of block 255. For example, the first RDL dielectric layer 171 is formed and patterned on the base dielectric layer 111. The patterned first RDL dielectric layer 171 may, for example, include a through hole 172 passing through the first RDL dielectric layer 171, and the base dielectric layer 111 may, for example, be etched through the through hole 172 (e.g., in block 260), and a first line (or portion thereof) may be formed in the through hole 172 (e.g., in block 265).

Generally speaking, block 255 may include, for example, forming and patterning a first dielectric layer (eg, a first RDL dielectric layer) on the base dielectric layer. Thus, the scope of this disclosure should not be limited to the features of a particular dielectric layer or to the features of a particular method of forming a dielectric layer.

The example method 200 may include etching the base dielectric layer (e.g., oxide layer, nitride layer, etc.) from the RD structure, such as an unmasked portion thereof, at block 260. Block 260 may include performing the etching in any of a variety of ways, non-limiting examples of which are presented herein.

For example, block 260 may include performing a dry etching process (or alternatively a wet etching process) to etch through the base dielectric layer (e.g., oxide, nitride, etc.) exposed by vias through the first dielectric layer, the first dielectric layer acting as a mask for the etching.

FIG1G is a diagram providing an example of various features (e.g., dielectric etch features) of block 260. For example, a portion of the base dielectric layer 111 shown in FIG1F as being below the first conductive line 112 is removed from FIG1G. This enables, for example, a metal-to-metal contact between the first conductive line 112 and the first RDL line formed in block 265.

Generally speaking, block 260 may include, for example, etching the base dielectric layer. Thus, the scope of this disclosure should not be limited to any particular manner of performing such etching.

The example method 200 may include forming a first redistribution layer (RDL) line at block 265. Block 265 may include forming the first RDL line in any of a variety of ways, non-limiting examples of which are presented herein.

As discussed herein, the first RDL dielectric layer (e.g., formed at block 255) can be utilized for etching (e.g., at block 260) and then retained for formation of the first RDL lines. Alternatively, the first RDL dielectric layer can be formed and patterned after the etching process. In yet another alternative embodiment discussed herein, the etching process for the base dielectric layer can be skipped, such as in an embodiment where the base dielectric layer (e.g., a thin oxide or nitride layer) is sufficiently conductive to adequately serve as a conductive path between metal lines.

Block 265 may include forming the first RDL line to attach to the first conductive line exposed through the patterned first RDL dielectric layer of the RD structure. The first RDL line may also be formed on the first RDL dielectric layer. Block 265 may include forming the first RDL line in any of a variety of ways (e.g., by electroplating), but the scope of this disclosure is not limited to the characteristics of any particular way of forming such a line.

The first RDL lines may include any of a variety of materials (e.g., copper, gold, nickel, etc.). The first RDL lines may, for example, include any of a variety of sized features. For example, a typical pitch for the first RDL lines may, for example, be 5 microns. In an exemplary embodiment, the first RDL lines may, for example, be formed at a center-to-center spacing that is approximately or at least an order of magnitude greater than a spacing at which various lines of the RD structure of the RD wafer are formed (e.g., at a sub-micron spacing, a spacing of approximately 0.5 microns, etc.).

1G and 1H provide diagrams of an example of various features (e.g., RDL line formation features) of block 265. For example, a first portion 181 of a first RDL line can be formed in a through hole 172 of the first RDL dielectric layer 171 and contact the first conductive line 112 of the RD structure 110 exposed by such through hole 172. Also for example, a second portion 182 of the first RDL line can be formed on the first RDL dielectric layer 171.

Generally, block 265 may include forming a first redistribution layer (RDL) line. Thus, the scope of this disclosure should not be limited to the features of any particular RDL line, or to the features of any particular manner of forming such an RDL line.

The example method 200 may include forming and patterning a second RDL dielectric layer over the first RDL lines (e.g., formed in block 265) and the first RDL dielectric layer (e.g., formed in block 255) at block 270. Block 270 may include forming and patterning the second dielectric layer in any of a variety of ways, non-limiting examples of which are presented herein.

For example, block 270 may share any or all features with block 255. The second RDL dielectric layer may be formed using the same material as the first RDL dielectric layer formed in block 255, for example.

The second RDL dielectric layer may include, for example, a polyimide or a polybenzoxazole (PBO) material. The second RDL dielectric layer may include, for example, an organic material. However, in various exemplary embodiments, the first RDL dielectric layer may include an inorganic material.

1H is a diagram providing an example of various features of block 270. For example, the second RDL dielectric layer 183 is formed on the first RDL lines 181, 182, and on the first RDL dielectric layer 171. As shown in FIG1H, through-holes 184 are formed in the second RDL layer 183, and conductive contact can be made through the through-holes 184 to the first RDL lines 182 exposed by such through-holes 184.

Generally, block 270 may include forming and/or patterning a second RDL dielectric layer. Thus, the scope of this disclosure should not be limited to the features of any particular dielectric layer, or to the features of any particular manner of forming a dielectric layer.

The exemplary method 200 may include forming a second redistribution layer (RDL) circuit at block 275. Block 275 may include forming the second RDL circuit in any of a variety of ways, non-limiting examples of which are presented herein. Block 275 may, for example, share any or all features with block 265.

Block 275 may include forming second RDL lines attached to first RDL lines (e.g., formed in block 265), where the first RDL lines are exposed through vias in the patterned second RDL dielectric layer (e.g., formed in block 270). The second RDL lines may also be formed on the second RDL dielectric layer. Block 275 may include forming the second RDL lines in any of a variety of ways (e.g., by electroplating), but the scope of this disclosure is not limited to the features of any particular way.

As with the first RDL lines, the second RDL lines may include any of a variety of materials (eg, copper, etc.). Additionally, the second RDL lines may include any of a variety of features of various sizes, for example.

1H and 1I are diagrams providing an example of various features of the block 275. For example, the second RDL lines 191 may be formed in the through-holes 184 in the second RDL dielectric layer 183 to contact the first RDL lines 181 exposed through such through-holes 184. In addition, the second RDL lines 191 may be formed on the second RDL dielectric layer 183.

Generally, block 275 may include forming a second redistribution layer (RDL) line. Thus, the scope of this disclosure should not be limited to the features of any particular RDL line, or to the features of any particular manner of forming such an RDL line.

The example method 200 may include forming and patterning a third RDL dielectric layer over the second RDL lines (e.g., formed in block 275) and the second RDL dielectric layer (e.g., formed in block 270) at block 280. Block 280 may include forming and patterning the third dielectric layer in any of a variety of ways, non-limiting examples of which are presented herein.

For example, block 280 may share any or all features with blocks 270 and 255. The third RDL dielectric layer may be formed, for example, using the same material as the first RDL dielectric layer formed in block 255 (and/or after etching of block 260 and stripping of a temporary mask layer) and/or using the same material as the second RDL dielectric layer formed in block 270.

The third RDL dielectric layer may include, for example, a polyimide or a polybenzoxazole (PBO) material. The third RDL dielectric layer may include, for example, an organic material. However, in various exemplary embodiments, the third RDL dielectric layer may include an inorganic material.

1I is a diagram providing an example of various features of block 280. For example, the third RDL layer 185 may be formed on the second RDL lines 191 and on the second RDL layer 183. As shown in FIG. 1I , vias are formed in the third RDL layer 185, and conductive contacts may be made through the vias to the second RDL lines 191 exposed by such vias.

Generally, block 280 may include forming and/or patterning a third RDL dielectric layer. Thus, the scope of this disclosure should not be limited to the features of any particular dielectric layer, or to the features of any particular manner of forming a dielectric layer.

The exemplary method 200 may include forming interconnect structures on the second RDL lines and/or on the third RDL dielectric layer at block 285. Block 285 may include forming the interconnect structures in any of a variety of ways, non-limiting examples of which are presented herein.

Block 285 may, for example, include forming an underbump metal on the portion of the second RDL line exposed through the via in the third dielectric layer. Block 285 may then, for example, include attaching a conductive bump or ball to the underbump metal. Other interconnect structures may also be utilized, examples of which are presented herein (e.g., conductive posts or pillars, solder balls, solder bumps, etc.).

FIG. 1I is a diagram that provides an example of various features (e.g., features formed by interconnect structures) of block 285. For example, interconnect structures 192 are attached to the second RDL lines 191 through vias formed in the third RDL dielectric layer 185. Note that although the interconnect structures 192 are depicted as being smaller than the interconnect structures 121, this disclosure is not so limited. For example, the interconnect structures 192 can be the same size as the interconnect structures 121, or larger than the interconnect structures 121. Furthermore, the interconnect structures 192 can be the same type of interconnect structure as the interconnect structures 121, or can be a different type.

Although the redistribution layers formed in blocks 255-285 (which may also be referred to as front side redistribution layers (RDLs)) are generally depicted in FIG. 1 as a fan-out assembly (e.g., extending outside the footprint of die 125, 126), they may also be formed as a fan-in assembly, e.g., where interconnect structure 192 does not generally extend outside the footprint of die 125, 126. Non-limiting examples of such assemblies are presented herein.

Generally speaking, block 285 may include, for example, interconnect structures formed on the second RDL lines and/or on the third RDL dielectric layer. Therefore, the scope of this disclosure should not be limited to the features of any particular interconnect structure or to any particular way of forming the interconnect structure.

The example method 200 may include, at block 290, debonding (or separating) the wafer support attached at block 245. Block 290 may include performing such debonding in any of a variety of ways, the non-limiting nature of which is presented herein.

For example, in an example scenario where the wafer support is adhesively attached, the adhesive may be released (e.g., using heat and/or force). Also, for example, a chemical release agent may be used. In another example scenario where the wafer support is attached using a vacuum force, the vacuum force may be released. Note that in a scenario involving an adhesive or other substance to aid in the installation of the wafer support, block 285 may include cleaning residues from the electrical component and/or from the wafer support after the debonding.

1I and 1J provide illustrations of one example of various features of block 290. For example, the wafer support 150 depicted in FIG1I is removed in FIG1J.

Generally speaking, block 290 may include debonding the wafer support. Thus, the scope of this disclosure should not be limited to the features of any particular type of wafer support, or to any particular manner of debonding a wafer support.

The example method 200 may include dicing the wafer at block 295. Block 295 may include dicing the wafer in any of a variety of ways, non-limiting examples of which are presented herein.

The discussion herein has generally focused on the processing of a single die of the RD wafer. This focus on a single die of the RD wafer is for the sake of illustration and clarity only. It should be understood that all of the process steps discussed herein can be performed on an entire wafer. For example, each of the illustrations presented in FIGS. 1A-1J and other figures herein can be replicated dozens or hundreds of times on a single wafer. For example, prior to dicing, one of the illustrated components of the wafer may be inseparable from an adjacent component.

Block 295 may, for example, include individual packages cut from the wafer (e.g., mechanical stamping, mechanical sawing, laser cutting, soft beam cutting, plasma cutting, etc.). The final result of such cutting may, for example, be the package shown in FIG. 1J. For example, the cutting may form a side surface of the package that is a coplanar side surface of a plurality of components of the package. For example, any or all of the side surfaces of the molding material 130, the dielectric layer of the RD structure 110, the various RDL dielectric layers, the underfill 128, etc. may be coplanar.

Generally, block 295 may include dicing the wafer. Thus, the scope of this disclosure should not be limited to the features of any particular manner of dicing a wafer.

Figures 1 and 2 present various exemplary method features and variations thereof. Other exemplary method features will now be presented with reference to other figures.

As discussed herein, in the discussion of Figures 1 and 2, block 235 may include grinding (or otherwise thinning) the molding material 130 to expose one or more of the dies 125, 126. An example is provided in Figure ID.

As also discussed, mold grinding (or thinning) at block 235 need not be performed, or may be performed to an extent that the tops of the die 125, 126 are still covered with molding material 130. An example is provided in FIG. 3. As shown in FIG. 3A, the molding material 130 covers the tops of the semiconductor die 125, 126. Note that the interconnect structures 121 may be shorter or taller than the die 125, 126. Continuing with the comparison, rather than the resulting package 100J appearing as shown in FIG. 1J, the resulting package 300B may appear as shown in FIG. 3B.

Furthermore, as discussed herein, in the discussion of FIGS. 1 and 2 , the block 215 where the TMV interconnect structure is formed and the block 240 where the TMV mold strip is performed can be skipped. An example is provided in FIG. 4 . As shown in FIG. 4A , relative to the block 215 and FIG. 1B , the TMV interconnect structure 121 is not formed. As shown in FIG. 4B , relative to the block 230 and FIG. 1C , the molding material 130 does not cover the interconnect structure.

Continuing with the comparison, as explained herein, mold grinding (or thinning) at block 235 may be performed to an extent that one or more of the tops of the die 125, 126 are exposed from the molding material 130. FIG4C is a diagrammatic representation of an example of such a process. Generally speaking, the assembly 400C of FIG4C is similar to the assembly 100J of FIG1J, minus the interconnect structures 121 and the through holes etched through the molding material 130 to expose the interconnect structures.

Also for example, as explained herein, mold grinding (or thinning) at block 235 can be skipped or performed to an extent that the tops of the die 125, 126 are covered with the molding material 130. FIG4D is a diagrammatic representation of an example of such a process. Generally speaking, the assembly 400D of FIG4D is similar to the assembly 100J of FIG1J, minus the interconnect structures 121 and the etched through holes through the molding material 130 to expose the interconnect structures, and wherein the molding material 130 covers the die 125, 126.

In another example, as explained herein, in the discussion of block 215, the TMV interconnects may include any of a variety of structures, such as a conductive post (e.g., a plated post or pillar, a vertical wire, etc.). FIG. 5A is a diagram providing an example of a conductive post 521 attached to the RD structure 110. The conductive posts 521 may, for example, be plated on the RD structure 110. The conductive posts 521 may, for example, also include wires (e.g., wire-bonded wires) attached (e.g., wire-bonded attachment, welding, etc.) to the RD structure 110 and extending vertically. The conductive posts 521 may, for example, extend from the RD structure 110 to a height that is greater than a height of the die 125, 126, equal to a height of one or more of the die 125, 126, less than a height of the die 125, 126, etc. In an exemplary embodiment, the pillars may have a height greater than or equal to 200 microns and at a center-to-center spacing of 100-150 microns. Note that any number of rows of pillars 521 may be formed. In general, the assembly 500A of FIG. 5A is similar to the assembly 100B of FIG. 1B , wherein the conductive pillars 521 serve as interconnect structures instead of the conductive spheres 121.

Continuing with the example, FIG5B depicts the RD structure 110, the conductive pillar 521, the semiconductor die 125, 126, and the underfill 128 covered with the molding material 130. The molding can be performed, for example, according to block 230 of the method 200 of the example. In general, the assembly 500B of FIG5B is similar to the assembly 100C of FIG1C, wherein the conductive pillar 521 is used as the interconnect structure instead of the conductive ball 121.

Still continuing with the example, FIG. 5C depicts the molding material 130 having been thinned (e.g., ground) to a desired thickness. The thinning may be performed, for example, according to block 235 of the example method 200. For example, it is noted that the conductive posts 521 and/or the semiconductor dies 125, 126 may also be thinned. Generally speaking, the assembly 500D of FIG. 5D is similar to the assembly 100D of FIG. 1D, wherein the conductive posts 521 serve as interconnect structures rather than the conductive balls 121, and also lack the etched through-holes 140 of FIG. 1D. For example, the thinning of the molding material 130 may expose the tops of the conductive posts 521. However, if the thinning of the molding material 130 does not expose the tops of the conductive pillars 521, a mold strip operation (e.g., according to block 240) may be performed. Note that although the assembly is shown with the tops of the semiconductor dies 125, 126 exposed, the tops need not be exposed. For example, the pillars 521 may be taller than the semiconductor dies 125, 126. Such an example configuration may, for example, allow the pillars 521 to be exposed from the molding material 130 and/or protrude from the molding material 130 while the molding material 130 continues to cover the back surfaces of the semiconductor dies 125, 126, which may, for example, provide protection to the semiconductor dies 125, 126, avoid or reduce warping, etc.

In an example embodiment where the pillars 521 are formed to have a height that is less than the die 125, 126, the thinning may include first grinding the molding material 130, followed by grinding the back (or inactive) sides of the molding material 130 and the die 125, 126 until the pillars 521 are exposed. At this point, the thinning may be stopped, or may continue, such as by grinding the molding material 130, the die 125, 126, and the pillars 521.

Continuing with the example, the assembly 500C shown in FIG5C can be further processed by forming a redistribution layer (RDL) 532 over the molding material 130 and the dies 125, 126. FIG5D shows an example of such processing. The redistribution layer 532 may also be referred to herein as a backside redistribution (RDL) layer 532. Although such backside RDL formation is not explicitly shown in any of the blocks of the example method 200, such operation may be performed in any of the blocks, such as after the mold grinding operation in block 235 and before the wafer support attachment in block 245 (e.g., in block 235, in block 240, in block 245, or between any of these blocks).

5D , a first backside dielectric layer 533 may be formed and patterned on the molding material 130 and the die 125, 126. The first backside dielectric layer 533 may be formed and patterned in the same or similar manner as the first RDL dielectric layer 171 formed in block 260, although the first RDL dielectric layer 171 is on a different surface. For example, the first back dielectric layer 533 may be formed on the molding material 130 and on the semiconductor grains 125, 126 (e.g., directly above the exposed back surfaces of the grains 125, 126, on the molding material 130 covering the back surfaces of the grains 125, 126, etc.), and through holes 534 may be formed in the first back dielectric layer 533 (e.g., by etching, stripping, etc.) to expose at least the tops of the conductive pillars 521. Note that in an example configuration in which the molding material 130 covers the back surfaces of the semiconductor die 125, 126, the first back dielectric layer 533 may still be formed, but this is not necessarily the case (e.g., the back wiring 535 discussed below may be formed directly on the molding material 130 rather than on the first back dielectric layer 533).

Backside wiring 535 may be formed on the first backside dielectric layer 533 and in the through-holes 534 of the first backside dielectric layer 533. The backside wiring 535 may thus be electrically connected to the conductive pillars 521. The backside wiring 535 may, for example, be formed in the same or similar manner as the first RDL wiring formed in block 265. At least some, if not all, of the backside wiring 535 may, for example, extend horizontally from the conductive pillars 521 to a position directly above the semiconductor dies 125, 126. At least some of the backside wiring 535 may also, for example, extend from the conductive pillars 521 to a position not directly above the semiconductor dies 125, 126.

A second back dielectric layer 536 can be formed and patterned on the first back dielectric layer 533 and the back lines 535. The second back dielectric layer 536 can be formed and patterned in the same or similar manner as the second RDL dielectric layer 183 formed in block 270, although the second RDL dielectric layer 183 is on a different surface. For example, the second back dielectric layer 536 can be formed on the first back dielectric layer 533 and on the back lines 535, and through holes 537 can be formed in the second back dielectric layer 536 (e.g., by etching, stripping, etc.) to expose the contact areas of the back lines 535.

Backside interconnect pads 538 (e.g., ball contact pads) may be formed on the second backside dielectric layer 536 and/or in the through-holes 537 of the second backside dielectric layer 536. The backside interconnect pads 538 may thus be electrically connected to the backside lines 535. The backside interconnect pads 538 may, for example, be formed in the same or similar manner as the second RDL lines formed in block 275. The backside interconnect pads 538 may, for example, be formed by forming metal contact pads and/or forming bump undermetallization (e.g., to enhance subsequent attachment to the backside lines 535 by interconnect structures).

Although the backside RDL layer 532 is shown as having two backside dielectric layers 533, 536 and a layer of backside wiring 535, it should be understood that any number of dielectric layers and/or wiring layers may be formed.

As shown, for example, in FIG. 5E , after the backside RDL layer 532 is formed, a wafer support structure 150 can be attached to the backside RDL layer 532 (e.g., directly, with an intervening adhesive layer, with vacuum force, etc.). The wafer support 150 can be attached, for example, in a manner that is the same or similar to the wafer support 150 attached at block 245. For example, FIG. 5E shows the wafer support 150 being attached in a manner similar to that of FIG. 1E , although attached to the RDL layer 532 rather than to the molding layer 130 and semiconductor die 125 , 126 .

As depicted, for example, in FIG. 5F , the support layer 105 (shown in FIG. 5E ) may be removed from the RD wafer, a front side redistribution layer may be formed on a side of the RD structure 110 opposite the dies 125 , 126 , the interconnect structure 192 may be formed, and the wafer support 150 may be removed.

For example, the support layer 105 can be removed in the same or similar manner as discussed herein in relation to block 250 and FIGS. 1E-1F. Also for example, a front redistribution layer can be formed in the same or similar manner as discussed herein in relation to blocks 255-280 and FIGS. 1G-1H. Also for example, the interconnect structure 192 can be formed in the same or similar manner as discussed herein in relation to block 285 and FIG. 1I. As another example, the wafer support 150 can be removed in the same or similar manner as discussed herein in relation to block 290 and FIG. 1J.

In another example implementation, a substrate (e.g., a laminate substrate, packaging substrate, etc.) can be attached to the semiconductor die 125, 126, for example, instead of or in addition to the backside RDL discussed herein in connection with FIG. 5. For example, as depicted in FIG. 6A, interconnect structures 621 can be formed at a height that will extend to the height of the die 125, 126. Note that this height does not necessarily exist, such as in a scenario where the backside substrate has its own interconnect structures, or where additional interconnect structures are utilized between the interconnect structures 621 and the backside substrate. The interconnect structures 621 can, for example, be attached in a manner that is the same or similar to that discussed herein in connection with block 215 and FIG. 1B.

Continuing with this example, as depicted in Fig. 6B, the assembly 600B can be molded, and if necessary, the molding can be thinned. Such molding and/or thinning can be performed, for example, in the same or similar manner as described in relation to blocks 230 and 235 and Figs. 1C and 1D.

As shown in FIG6C , a wafer support 150 may be attached, support layer 105 may be removed, and a front side RDL may be formed. For example, a wafer support 150 may be attached in the same or similar manner as discussed herein in relation to block 245 and FIG1E . Also, for example, support layer 105 may be removed in the same or similar manner as discussed herein in relation to block 250 and FIG1F . Also, for example, a front side RDL may be formed in the same or similar manner as discussed herein in relation to blocks 255-280 and FIGS1G-1H .

As depicted in FIG6D , the interconnect 192 may be attached, the wafer support 150 may be removed, and the back substrate 632 may be attached. For example, the interconnect 192 may be attached in the same or similar manner as discussed herein in relation to block 285 and FIG1I . Also, for example, the wafer support 150 may be removed in the same or similar manner as discussed herein in relation to block 290 and FIG1J . For another example, the back substrate 632 may be electrically attached to the interconnect 621 and/or mechanically attached to the molding material 130 and/or the die 125, 126. The back substrate 632 may be attached, for example, in wafer (or panel) form and/or in a single package form, and may be attached, for example, before or after dicing (eg, as discussed at block 295).

The exemplary methods and assemblies shown in FIGS. 1-7 and discussed herein are non-limiting examples only and are presented to illustrate various features of the disclosure. Such methods and assemblies may also share any or all features with the methods and assemblies shown and discussed in the following co-applied U.S. patent applications: U.S. Patent Application Serial No. 13/753,120 filed on January 29, 2013 and entitled “Semiconductor Device and Method of Making a Semiconductor Device”; U.S. Patent Application Serial No. 13/863,457 filed on April 16, 2013 and entitled “Semiconductor Device and Method of Making the Same”; U.S. Patent Application Serial No. 14/083,779, filed on November 19, 2013, and entitled "Semiconductor Device with Through Silicon Via - Less Deep Well"; U.S. Patent Application Serial No. 14/218,265, filed on March 18, 2014, and entitled "Semiconductor Device and Method of Making the Same"; U.S. Patent Application Serial No. 14/313,726, filed on June 24, 2014, and entitled "Semiconductor Device and Method of Making the Same" 4; U.S. Patent Application Serial No. 14/444,450, filed on July 28, 2014, and entitled "Semiconductor Device with Thin Redistribution Layer"; U.S. Patent Application Serial No. 14/524,443, filed on October 27, 2014, and entitled "Semiconductor Device with Reduced Thickness"; U.S. Patent Application Serial No. 14/524,443, filed on November 4, 2014, and entitled "Interposer, Method of Making Same, Semiconductor Package Using Same, and Method for Making Same" Serial No. 14/532,532, filed on November 18, 2014, and entitled "Semiconductor device with reduced warp"; U.S. Patent Application Serial No. 14/546,484, filed on November 18, 2014, and entitled "Semiconductor device and method of making the same"; and U.S. Patent Application Serial No. 14/671,095, filed on March 27, 2015, and entitled "Semiconductor device and method of making the same"; the contents of each of these U.S. Patent Applications are hereby incorporated by reference in their entirety.

It should be noted that any or all of the semiconductor packages discussed herein may (but need not) be attached to a package substrate. Various non-limiting examples of such semiconductor device packages and methods of making them will now be discussed.

Fig. 7A-7L is a cross-sectional view showing a semiconductor package of an example and a method for manufacturing an example of a semiconductor package according to various features of the present disclosure. The structure shown in Fig. 7A-7L can, for example, share any or all features with the similar structures shown in Fig. 1A-1J, 3A-3B, 4A-4D, 5A-5F, 6A-6D, 9, 10A-10B, 11A-11D, 12A-12B, 13 and 14. Fig. 8 is a flow chart of a method 800 for manufacturing an example of a semiconductor package according to various features of the present disclosure. The method 800 of this example can, for example, share any or all features with the method 200 of the example described in Fig. 2 and described here and with any method described here. 7A-7L may, for example, depict an exemplary semiconductor package at various steps (or blocks) of the manufacturing method 800 of FIG8. FIG7A-7L and FIG8 will now be discussed together.

The example method 800 may include preparing a logic wafer for processing (e.g., for packaging) at block 805. Block 805 may include preparing a logic wafer for processing in any of a variety of ways, non-limiting examples of which are presented herein. Block 805 may, for example, share any or all features with block 205 of the example method 200 shown in FIG. 2 and discussed herein.

The example method 800 may include preparing a redistributed structure wafer (RD wafer) at block 810. Block 810 may include preparing an RD wafer for processing in any of a variety of ways, non-limiting examples of which are provided herein. Block 810 may, for example, share any or all features with block 210 of the example method 200 shown in FIG. 2 and discussed herein.

FIG. 7A is a diagram providing an example of various features of a block 810. Referring to FIG. 7A, the RD wafer 700A may include, for example, a supporting layer 705 (e.g., a silicon layer). A redistribution (RD) structure 710 may be formed on the supporting layer 705. The RD structure 710 may include, for example, a base dielectric layer 711, a first dielectric layer 713, a first conductive line 712, a second dielectric layer 716, a second conductive line 715, and an interconnect structure 717.

The base dielectric layer 711 may be, for example, on the support layer 705. The base dielectric layer 711 may include, for example, an oxide layer, a nitride layer, etc. The base dielectric layer 711 may be, for example, formed according to specifications and/or may be natural.

The RD wafer 700A may also include, for example, first conductive lines 712 and a first dielectric layer 713. The first conductive lines 712 may include, for example, deposited conductive metals (e.g., copper, etc.). The first dielectric layer 713 may include, for example, an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the first dielectric layer 713 may include an organic dielectric material.

The RD wafer 700A may also include, for example, a second conductive line 715 and a second dielectric layer 716. The second conductive line 715 may include, for example, a deposited conductive metal (e.g., copper, etc.). The second conductive line 715 may, for example, be connected to the individual first conductive lines 712 through individual conductive vias 714 (e.g., in the first dielectric layer 713). The second dielectric layer 716 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the second dielectric layer 716 may include an organic dielectric material.

Although two sets of dielectric layers and conductive lines are depicted in FIG. 7A , it should be understood that the RD structure 710 of the RD wafer 700A may include any number of such layers and lines. For example, the RD structure 710 may include only one dielectric layer and/or one set of conductive lines, three sets of dielectric layers and/or conductive lines, and so on.

As with the logic wafer fabrication in block 805, block 810 may include forming interconnect structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive planes or pads, etc.) on a surface of the RD structure 710. An example of such an interconnect structure 717 is shown in FIG. 7A, where the RD structure 710 includes an interconnect structure 717, which is shown as being formed on the front (or top) side of the RD structure 710 and electrically connected to respective second conductive lines 715 through conductive vias in the second dielectric layer 716. Such an interconnect structure 717 may be utilized, for example, to couple the RD structure 710 to various electronic components (e.g., active semiconductor components or dies, passive components, etc.).

The interconnect structures 717 may include, for example, any one of various conductive materials (eg, any one or a combination of copper, nickel, gold, etc.). The interconnect structures 717 may also include, for example, solder.

Generally speaking, block 810 may include fabricating a redistributed structure wafer (RD wafer). Thus, the scope of this disclosure should not be limited to the features of any particular manner of performing such fabrication.

The example method 800 may include attaching one or more semiconductor dies to the RD structure (e.g., the RD structure of the RD wafer) at block 820. Block 820 may include attaching the die to the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 820 may, for example, share any or all features with block 220 of the example method 200 shown in FIG. 2 and discussed herein.

7B is a diagram that provides an example of various features (e.g., the die attachment) of block 820. For example, a first die 725 (e.g., which may have been cut from a logic wafer fabricated in block 805) is electrically and mechanically attached to the redistribution structure 710. Similarly, a second die 726 (e.g., which may have been cut from a logic wafer fabricated in block 805) is electrically and mechanically attached to the redistribution structure 710.

The first die 725 and the second die 726 may include any of a variety of die characteristics. In one example scenario, the first die 725 may include a processor die, and the second die 726 may include a memory die. In another example scenario, the first die 725 may include a processor die, and the second die 726 may include a co-processor die. In another example scenario, the first die 725 may include a sensor die, and the second die 726 may include a sensor processing die. Although the assembly 700B of FIG. 7B is shown as having two dies 725, 726, it may have any number of dies. For example, it may have only one die, three dies, four dies, or more than four dies.

In addition, although the first die 725 and the second die 726 are shown as being attached to the redistribution structure 710 laterally relative to each other, they may also be configured in a vertical assembly. Various non-limiting example assemblies of such a structure are shown and discussed herein (e.g., die-on-die stacking, die attached to opposite substrate sides, etc.). Furthermore, although the first die 725 and the second die 726 are shown as having substantially similar sizes, such dies 725, 726 may include different individual features (e.g., die height, footprint, connection pitch, etc.).

The first die 725 and the second die 726 are depicted as having substantially uniform spacing, but this is not necessarily the case. For example, most or all of the contacts of the first die 725 in an area of the first die coverage area immediately adjacent to the second die 726 and/or most of the contacts of the second die 126 in an area of the second die coverage area immediately adjacent to the first die 725 may have substantially finer spacing than most or all of the other contacts. For example, the first 5, 10, or n rows of contacts of the first die 725 closest to the second die 726 (and/or the second die 726 closest to the first die 725) may have a spacing of 30 microns, while the other contacts may have a spacing of approximately 80 microns and/or 200 microns. The RD structure 710 may therefore have corresponding contact structures and/or lines at the corresponding spacing.

Generally, block 820 includes attaching one or more semiconductor dies to the redistribution structure (e.g., a redistribution structure of a redistribution wafer). Thus, the scope of this disclosure should not be limited to the characteristics of any particular die, or to the characteristics of any particular multi-die layout, or to the characteristics of any particular manner of attaching such dies, etc.

The example method 800 may include, at block 825, underfilling the semiconductor die and/or other components attached to the RD structure at block 820. Block 825 may include performing such underfilling in any of a variety of ways, non-limiting examples of which are presented herein. Block 825 may, for example, share any or all features with block 225 of the example method 200 shown in FIG. 2 and discussed herein.

7B is a diagram providing an example of various features (eg, the underfill) of the block 825. The underfill 728 is disposed between the first semiconductor die 725 and the redistribution structure 710, and between the second semiconductor die 726 and the redistribution structure 710.

Although the underfill 728 is depicted as being generally flat, the underfill can rise and form fillets on the sides of the semiconductor die and/or other components. In one example scenario, at least a quarter or at least half of the side surfaces of the die can be covered with the underfill material. In another example scenario, one or more or all of the entire side surfaces can be covered with the underfill material. Similarly, for example, a substantial portion of the space directly between the semiconductor die, between the semiconductor die and other components, and/or between other components can be filled with the underfill material. For example, at least half of the space between laterally adjacent semiconductor dies, between the semiconductor die and other components, and/or between other components, or all of the space can be filled with the underfill material. In an exemplary implementation, the underfill 728 can cover the entire redistributed structure 710 of the RD wafer. In this exemplary implementation, when the RD wafer is subsequently cut, the cutting can also cut through the underfill 728.

Generally speaking, block 825 may include an underfill to attach semiconductor die and/or other components to the RD structure in block 820. Thus, the scope of this disclosure should not be limited to the features of any particular type of underfill or any particular manner of performing such underfill.

The example method 800 may include molding the RD wafer (or RD structure) at block 830. Block 830 may include molding the RD wafer in any of a variety of ways, non-limiting examples of which are presented herein. Block 830 may, for example, share any or all features with block 230 of the example method 200 shown in FIG. 2 and discussed herein.

7C is a diagram that provides an example of various features (e.g., molding features) of block 830. For example, the molding assembly 700C is shown where the molding material 730 covers the first semiconductor die 725, the second semiconductor die 726, the underfill 728, and the top surface of the redistributed structure 710. Although the molding material 730 (which may also be referred to herein as an encapsulation material) is shown as completely covering the sides and tops of the first semiconductor die 725 and the second semiconductor die 726, this is not necessarily the case. For example, block 830 may include a molding technique that utilizes a film-assisted or die-sealed molding technique to keep the tops of the die free of molding material.

In general, the molding material 730 may, for example, directly contact and cover portions of the die 725, 726 that are not covered by the underfill 728. For example, in a scenario where at least a first portion of the sides of the die 725, 726 are covered by the underfill 728, the molding material 730 may directly contact and cover a second portion of the sides of the die 725, 726. The molding material 730 may, for example, also fill the space between the die 725, 726 (e.g., at least a portion of the space that has not yet been filled with the underfill 728).

Generally speaking, block 830 may include molding the RD wafer. Thus, the scope of this disclosure should not be limited to the features of any particular molding material, structure and/or technique.

The example method 800 may include, at block 835, grinding (or thinning) the molding material applied at block 830. Block 835 may include grinding (or thinning) the molding material in any of a variety of ways, non-limiting examples of which are presented herein. Block 835 may, for example, share any or all features with block 235 of the example method 200 shown in FIG. 2 and discussed herein.

FIG7D is a diagram that provides an example of various features (e.g., the mold grinding features) of block 835. The assembly 700D is depicted as the molding material 730 (e.g., relative to the molding material 730 depicted in FIG7C) being thinned to expose the top surfaces of the die 725, 726. In this example, the die 725, 726 may also have been ground (or thinned).

As explained herein, the molding material 730 can be retained in an overmolded assembly to cover the die 725, 726. For example, the molding material 730 can be unmilled, or the molding material 730 can be milled, but not to a height that exposes the die 725, 726.

Generally speaking, block 835 may include grinding (or thinning) the molding material applied in block 830. Thus, the scope of this disclosure should not be limited to any particular amount or type of grinding (or thinning) characteristics.

The example method 800 may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure at block 845. Block 845 may include attaching the molded RD wafer to the wafer support structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 845 may, for example, share any or all features with block 245 of the example method 200 shown in FIG. 2 and discussed herein.

FIG. 7E is a diagram that provides an example of various features of block 845 (e.g., features of wafer support attachment). The wafer support structure 750 is attached to the molding material 730 and the top sides of the dies 725, 726. The wafer support structure 750 can be attached, for example, using an adhesive. Note that in an assembly where the tops of the dies 725, 726 are covered with the molding material 730, the wafer support structure 750 can only be directly coupled to the top of the molding material 730.

Generally, block 845 may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Thus, the scope of this disclosure should not be limited to the features of any particular type of wafer support structure or to the features of any particular manner of attaching a wafer support structure.

The example method 200 may include removing a support layer from the RD wafer at block 850. Block 850 may include removing the support layer in any of a variety of ways, non-limiting examples of which are presented herein. Block 850 may, for example, share any or all features with block 250 of the example method 200 shown in FIG. 2 and discussed herein.

As discussed herein, the RD wafer may include a supporting layer on which an RD structure is formed and/or supported. The supporting layer may, for example, include a semiconductor material (e.g., silicon). In an example scenario in which the supporting layer includes a silicon wafer layer, block 850 may include removing the silicon (e.g., removing all of the silicon from the RD wafer, removing almost all of the silicon from the RD wafer (e.g., at least 90% or 95%), etc.). For example, block 850 may include mechanically grinding almost all of the silicon, followed by a dry or wet chemical etch to remove the remaining portion (or almost all of the remaining portion). In an example scenario where the support layer is loosely attached to the RD structure formed (or carried) thereon, block 850 may include pulling or peeling to separate the support layer from the RD structure.

7F is a diagram providing an example of various features (e.g., support layer removal features) of block 850. For example, the support layer 705 (shown in FIG. 7E ) is removed from the RD structure 710. In the illustrated example, the RD structure 710 may still include a base dielectric layer 711 (e.g., an oxide, nitride, etc.) as discussed herein.

Generally, block 850 may include removing a support layer from the RD wafer. Thus, the scope of this disclosure should not be limited to the characteristics of any particular type of wafer material or to the characteristics of any particular manner of wafer material removal.

The example method 800 may include forming and patterning a redistribution layer (RDL) dielectric layer at block 855 for etching an oxide layer of the RD structure. Block 855 may include forming and patterning the RDL dielectric layer in any of a variety of ways, non-limiting examples of which are presented herein. Block 855 may, for example, share any or all features with block 255 of the example method 200 shown in FIG. 2 and discussed herein.

7G is a diagram that provides an example of various features of block 855. For example, the RDL dielectric layer 771 is formed and patterned on the base dielectric layer 711. The patterned RDL dielectric layer 771 may, for example, include a through hole 772 passing through the RDL dielectric layer 771, for example, the base dielectric layer 711 may be etched through the through hole 772 (e.g., in block 860), and a conductive line (or portion thereof) may be formed (e.g., in block 865) in the through hole 772.

Generally, block 855 may include, for example, forming and patterning a dielectric layer (eg, an RDL dielectric layer) on the base dielectric layer. Thus, the scope of this disclosure should not be limited to the features of a particular dielectric layer or to the features of a particular method of forming a dielectric layer.

The example method 800 may include etching the base dielectric layer (e.g., oxide layer, nitride layer, etc.) from the RD structure, such as an unmasked portion thereof, at block 860. Block 860 may include performing the etching in any of a variety of ways, non-limiting examples of which are presented herein. Block 860 may, for example, share any or all features with block 260 of the example method 200 shown in FIG. 2 and discussed herein.

FIG7G is a diagram providing an example of various features of block 860. For example, the portion of the base dielectric layer 711 shown below the first conductive lines 712 in FIG7F is removed from FIG7G. This enables metal-to-metal contact between the first conductive lines 712 and the RDL lines formed in block 865, for example.

Generally speaking, block 860 may include, for example, etching the base dielectric layer. Thus, the scope of this disclosure should not be limited to any particular manner of performing such etching.

The example method 800 may include forming a redistribution layer (RDL) circuit at block 865. Block 865 may include forming the RDL circuit in any of a variety of ways, non-limiting examples of which are presented herein. Block 865 may, for example, share any or all features with block 265 of the example method 200 shown in FIG. 2 and discussed herein.

7G and 7H provide diagrams of an example of various features (e.g., features formed by RDL lines) of block 865. For example, a first portion 781 of the RDL lines can be formed in the through-hole 772 of the RDL dielectric layer 771 and contact the first conductive line 712 of the RD structure 710 exposed by the through-hole 772. Also for example, a second portion 782 of the first RDL line can be formed on the first RDL dielectric layer 771.

Generally, block 865 may include forming redistribution layer (RDL) lines. Thus, the scope of this disclosure should not be limited to the features of any particular RDL lines, or to the features of any particular manner of forming such RDL lines.

Note that although the example method 800 shows only an RDL dielectric layer at block 855 and only an RDL line at block 865, such blocks may be repeated as many times as desired.

The example method 800 may form interconnect structures on the RDL lines at block 885. Block 885 may include forming these interconnect structures in any of a variety of ways, non-limiting examples of which are presented herein. For example, block 885 may share any or all features with block 285 of the example method 200 shown in FIG. 2 and discussed herein.

Block 885 may, for example, form conductive pillars (e.g., metal pillars, copper pillars, solder-capped pillars, etc.) and/or conductive bumps (e.g., solder, etc.) on the RDL lines. For example, block 885 may include electroplating conductive pillars, providing or coating conductive bumps, and the like.

7I is a diagram providing an example of various features (e.g., features formed by bumps) of block 885. For example, interconnect structures 792 (e.g., which are shown as solder-capped pillars, such as copper pillars) are attached to the RDL lines 782.

Although the redistribution layers formed in blocks 855-885 (which may also be referred to as front side redistribution layers (RDLs)) are depicted in FIG. 7 as generally being a fan-in assembly (e.g., generally contained within the footprint of die 725, 726), they may also be formed as a fan-out assembly, e.g., where at least a portion of interconnect structure 792 extends generally outside the footprint of die 725, 726. Non-limiting examples of such assemblies are presented herein.

Generally speaking, block 885 may include, for example, interconnect structures formed on the RDL lines and/or on the RDL dielectric layer. Thus, the scope of this disclosure should not be limited to the features of any particular interconnect structure or to any particular way of forming the interconnect structure.

The example method 800 may include, at block 890, debonding (or separating) the wafer support attached at block 845. Block 890 may include performing such debonding in any of a variety of ways, non-limiting features of which are presented herein. For example, block 890 may share any or all features with block 290 of the example method 200 shown in FIG. 2 and discussed herein.

7H and 7I are diagrams providing an example of various features of block 890. For example, wafer support 750 depicted in FIG7H is removed in FIG7I.

Generally, block 890 may include debonding the wafer support. Thus, the scope of this disclosure should not be limited to the features of any particular type of wafer support, or to any particular manner of debonding a wafer support.

The example method 800 may include dicing the wafer at block 895. Block 895 may include dicing the wafer in any of a variety of ways, non-limiting examples of which are presented herein. Block 895 may, for example, share any or all features with block 295 of the example method 200 shown in FIG. 2 and discussed herein.

The discussion herein has generally focused on the processing of a single die of the RD wafer. This focus on a single die of the RD wafer is for the sake of illustration and clarity. It should be understood that all of the process steps (or blocks) discussed herein can be performed on an entire wafer. For example, each of the illustrations presented in FIGS. 7A-7L and other figures herein can be replicated dozens or hundreds of times on a single wafer. For example, prior to dicing, one of the illustrated device components of the wafer may be inseparable from an adjacent device component.

Block 895 may, for example, include individual packages cut from the wafer (e.g., mechanical stamping, mechanical sawing, laser cutting, soft beam cutting, plasma cutting, etc.). The final result of such cutting may, for example, be the package shown in FIG. 7I. For example, the cutting may form a side surface of the package that is a coplanar side surface of a plurality of components of the package. For example, any or all of the side surfaces of the molding material 730, the dielectric layer of the RD structure 710, the RDL dielectric layer 771, the bottom glue filling 728, etc. may be coplanar.

Generally, block 895 may include dicing the wafer. Thus, the scope of this disclosure should not be limited to the features of any particular manner of dicing a wafer.

The example method 800 may include preparing a substrate, or a wafer or panel thereof, at block 896 for attachment of the assembly 700I thereto. Block 896 may include preparing a substrate in any of a variety of ways, non-limiting examples of which are presented herein. Block 896 may, for example, share any or all features with blocks 205 and 210 of the example method 200 shown in FIG. 2 and discussed herein.

The substrate may, for example, include features of any of a variety of substrates. For example, the substrate may include a package substrate, a motherboard substrate, a laminate substrate, a molded substrate, a semiconductor substrate, a glass substrate, etc.). Block 896 may, for example, include preparing the front and/or back surfaces of the substrate for electrical and/or mechanical attachment. Block 896 may, for example, allow a panel of substrates to remain in a panel form at this stage and later cut into individual packages, or may cut individual substrates from a panel at this stage.

Block 896 may also include receiving the substrate from an adjacent or upstream manufacturing station in a manufacturing facility, from another geographical location, etc. The received substrate may, for example, have already been prepared, or additional preparation steps may be performed.

7J is a diagram that provides an example of various features of block 896. For example, the assembly 700J includes an example substrate 793 that is prepared for attachment.

Generally speaking, block 896 may include preparing a substrate, or a wafer or panel thereof, for attachment of the assembly 700I thereto. Thus, the scope of the various features of this disclosure should not be limited to the features of a particular substrate, or to the features of any particular method of preparing a substrate.

The example method 800 may include attaching a component to the substrate at block 897. Block 897 may include attaching a component (e.g., a component 700I illustrated in FIG. 7I or another component) in any of a variety of ways, non-limiting examples of which are presented herein. Block 897 may, for example, share any or all features with block 220 of the example method 200 illustrated in FIG. 2 and discussed herein.

The assembly may include features of any of a variety of assemblies, non-limiting examples of which are presented herein, such as in all of the figures and/or in the discussion related thereto. Block 897 may include attaching the assembly in any of a variety of ways. For example, block 897 may include utilizing batch reflow, thermocompression bonding (TCB), conductive epoxy, etc. to attach the assembly to the substrate.

7J is a diagram that provides an example of various features (e.g., component attachment features) of block 897. For example, component 700I shown in FIG. 7I is attached to the substrate 793.

Although not shown in FIG. 7J , in various example embodiments (e.g., as shown in FIGS. 7K and 7L ), interconnect structures such as through-mold interconnect structures may be formed on the substrate 793. In such example embodiments, block 897 may share any or all features with block 215 of the example method 200 shown in FIG. 2 and discussed herein, although with respect to forming the interconnect structures on the substrate 793. Note that such interconnect structures may be performed before or after the component is attached, or may also be performed before or after the primer fill of block 898.

Generally, block 897 includes attaching a component to the substrate. Thus, the scope of this disclosure should not be limited to the features of any particular component, substrate, or method of attaching a component to a substrate.

The exemplary method 800 may include a primer filling component on the substrate at block 898. Block 898 may include any of a variety of primer filling methods, non-limiting examples of which are presented herein. Block 898 may, for example, share any or all features with block 825 and/or block 225 of the exemplary method 200 shown in FIG. 2 and discussed herein.

For example, after the assembly of block 897 is attached, block 898 may include primer filling the attached assembly using a capillary primer fill. For example, the primer fill may include a reinforced polymer material that is sufficiently viscous to flow between the assembly and the substrate in a capillary action.

Also for example, block 897 may include underfilling the semiconductor die using a non-conductive paste (NCP) and/or a non-conductive film (NCF) or tape while the component is being attached (e.g., using a thermocompression bonding process) at block 897. For example, such underfill material may be deposited (e.g., printed, sprayed, etc.) prior to attaching the component.

As with all blocks depicted in the example method 800, block 898 may be performed at any point in the flow of the method 800 as long as space between the component and the substrate is accessible.

The underfill may also occur at a different area of the example method 800. For example, the underfill may be performed as part of the substrate molding area 899 (eg, using a molding underfill).

7K is a diagram providing an example of various features (eg, the underfill features) of block 898. The underfill 794 is disposed between the assembly 700I and the substrate 793.

Although the primer fill 794 is generally depicted as flat, the primer fill can be raised and rounded on the sides of the component 700I and/or other components. In one example scenario, at least a quarter or at least half of the side surface of the component 700I can be covered with the primer fill material. In another example scenario, one or more or all of the entire side surface of the component 700I can be covered with the primer fill material. Similarly, for example, a substantial portion of the space directly between the component 700I and other components and/or between other components (shown in the various figures) can be filled with the primer fill material 794. For example, at least half of the space or the entire space between the component 700I and a laterally adjacent member may be filled with the primer filling material.

As shown in FIG. 7J , the assembly 700J may include a first under-glue fill 728 between the die 725, 726 and the RD structure 710, and a second under-glue fill 794 between the RD structure 710 and the substrate 793. Such under-glue fills 728, 794 may be different, for example. For example, in an example scenario where the distance between the die 725, 726 and the RD structure 710 is less than the distance between the RD structure 710 and the substrate 793, the first under-glue fill 728 may generally include a smaller filler size (or have a higher viscosity) than the second under-glue fill 794. In other words, the second under-glue fill 794 may be cheaper than the first under-glue fill 728.

Furthermore, the respective primer filling processes performed in blocks 898 and 825 may be different. For example, block 825 may include a capillary primer filling process, while block 898 may include a non-conductive paste (NCP) primer filling process.

In another example, blocks 825 and 898 may include being performed simultaneously in the same primer fill process, such as after block 897. In addition, as discussed herein, a molded primer fill may also be utilized. In such an example scenario, block 899 may include performing a primer fill of either or both of blocks 825 and/or 898 during the substrate molding process. For example, block 825 may include performing a capillary primer fill, while block 898 is performed as a molded primer fill process at block 899.

Generally speaking, block 898 may include a primer filling of components and/or other components attached to the substrate at block 897. Thus, the scope of this disclosure should not be limited to the characteristics of any particular type of primer filling, or any particular manner of performing primer filling.

The example method 800 may include molding the substrate at block 899. Block 899 may include performing such molding in any of a variety of ways, non-limiting examples of which are presented herein. Block 899 may, for example, share any or all features with block 830 and/or block 230 of the example method 200 shown in FIG. 2 and discussed herein.

For example, block 899 may include a molded-on top surface of the substrate, on a component to which block 897 is attached, on a TMV interconnect structure (if it is formed on the substrate, such as a conductive sphere, ellipse, pillar or column (e.g., electroplated pillars, wires or bond wires, etc.), etc.).

Block 899 may, for example, include utilizing transfer molding, compression molding, etc. Block 899 may, for example, include utilizing a panel molding process where a plurality of substrates are connected in a panel and molded together, or block 899 may include molding substrates individually. In the case of a panel molding, after the panel is molded, block 899 may include performing a slicing process where individual substrates are separated from the substrate panel.

The molding material may, for example, include any of a variety of characteristics. For example, the molding material (e.g., epoxy molding compound (EMC), epoxy molding compound, etc.) may include a relatively high modulus, such as to provide package support in a subsequent process. Similarly, the molding material may include a relatively low modulus to provide package flexibility in a subsequent process.

Block 899, for example, may include a molded material that is different than the molded material utilized in block 830. For example, block 899 may utilize a molded material having a lower modulus than the molded material utilized in block 830. In such a scenario, the central region of the assembly may be relatively stiffer than the peripheral regions of the assembly, providing various force absorption in the stronger regions of the assembly.

In an example scenario where the molding material 735 of the assembly 700K and the molding material 730 of the assembly 700I are different and/or formed at different stages and/or formed using different types of processes, block 899 (or another block) may include preparing the molding material 730 for adhesion to the molding material 735. For example, the molding material 730 may be physically or chemically etched. The molding material 730 may be plasma etched, for example. Also for example, grooves, notches, protrusions, or other physical features may be formed on the molding material 730. For another example, an adhesive may be disposed on the molding material 730.

Block 899 may, for example, utilize a different type of molding process than that utilized at block 830. In one example scenario, block 830 may utilize a compression molding process while block 899 utilizes a transfer molding process. In such an example scenario, block 830 may utilize a molding material specifically adapted for compression molding, and block 899 may utilize a molding material specifically adapted for transfer molding. Such molding materials may, for example, have significantly different material characteristics (e.g., flow characteristics, curing characteristics, hardness characteristics, particle size characteristics, chemical compound characteristics, etc.).

As explained herein, for example, with respect to block 898, the molding process of block 899 may provide an underfill between the assembly 700I and the substrate 793, and/or may provide an underfill between the dies 725, 726 and the RD structure 710. In such examples, there may be material uniformity between the molding underfill material and the molding material encapsulating the substrate 793 and assembly 700I and/or the molding material encapsulating the RD structure 710 and the semiconductor dies 725, 726.

FIG. 7K is a diagram that provides an example of various features (e.g., the molding features) of block 899. For example, the molded assembly 700K is shown with the molding material 735 covering the interconnect structure 795 and assembly 700I. Although the molding material 735 (which may also be referred to herein as encapsulation material) is shown with the top of assembly 700I exposed, this is not necessarily the case. For example, block 899 may completely cover assembly 700I and may not need to be followed by a thinning (or grinding) operation to expose the top of assembly 700I.

In general, the molding material 735 may, for example, directly contact and cover portions of the assembly 700I that are not covered by the underfill 794. For example, in a scenario where at least a first portion of a side of the assembly 700I is covered with the underfill 794, the molding material 735 may directly contact and cover a second portion of the side of the assembly 700I. Furthermore, the molding material 735 may extend laterally to the edge of the substrate 793 and thereby form a side surface that is coplanar with the substrate 793. Such an assembly may, for example, be formed using panel molding, followed by singulation of individual packages from the panel.

Generally speaking, block 899 may include molding the substrate. Thus, the scope of this disclosure should not be limited to the features of any particular molding material, structure and/or technology.

The example method 800 may include forming interconnect structures on the substrate at block 886, such as on a side of the substrate opposite the side to which the component is attached at block 897. The interconnect structures may include features of any of a variety of types of interconnect structures, such as structures that may be utilized to connect a semiconductor package to another package or to a motherboard. For example, the interconnect structures may include conductive balls (e.g., solder balls) or bumps, conductive posts, and the like.

7K is a diagram that provides an example of various features (e.g., the features that form the interconnects) of block 886. For example, the interconnect structures 792 are depicted as being attached to the plane 791 of the substrate 793.

Generally speaking, block 886 may include forming an interconnect structure on the substrate. Thus, the scope of this disclosure should not be limited to the features of a particular interconnect structure, or to any particular manner of forming such a structure.

As discussed herein, the underfill 728 can cover at least a portion of the side of the die 725, 726, and/or the underfill 794 can cover at least a portion of the side of the assembly 700I. Figure 7L provides an example of one example of such covering. For example, the assembly 700I is shown where the underfill 728 is in contact with a portion of the side of the die 725, 726. As discussed herein, during a cutting process, the underfill 728 can also be cut, which produces an assembly 700I including a flat side surface, which side surface includes a side surface of the RD structure 710, a side surface of the molding material 730, and a side surface of the underfill 728.

The assembly 700L (which may also be referred to as a package) is shown with the underfill 794 contacting a portion of the sides of the assembly 700I (e.g., the sides of the RD structure 710, the sides of the underfill 728, and the sides of the molding material 730). Note that, as discussed herein, in various example embodiments, the underfill 794 may include a molded underfill that is the same material as the molding material 735. The molding material 735 is shown encapsulating the substrate 793, the interconnect structure 795, the underfill 794, and the assembly 700I. Although in the illustration of the example, the tops of the assembly 700I and the interconnect structure 795 are exposed from the molding material 735, this is not necessarily the case.

Figures 7 and 8 present various exemplary method features and variations thereof. Other exemplary method features will now be presented with reference to additional figures.

7 and 8, block 835 may include grinding (or thinning) the molding material 730 to expose one or more of the dies 725, 726. An example is provided in FIG. 7D.

As also discussed, mold grinding (or thinning) at block 835 need not be performed, or may be performed to an extent that the tops of the dies 725, 726 are still covered with the molding material 730. An example is provided in FIG. 9 , where the molding material 735 covers the tops of the dies 725, 726 of the assembly 700I.

As also discussed herein, for example with respect to block 897 and FIGS. 7K and 7L , in various example embodiments, interconnect structures may be formed on the substrate. An example is provided in FIG. 9 . For example, although the tops of the die interconnect structures 795 are initially covered with the molding material 735, through holes 940 are etched in the molding material 735 to expose the interconnect structures 795.

Furthermore, as discussed in the discussion of FIGS. 7 and 8 herein, in various example embodiments, TMV interconnect structures need not be formed on the substrate. An example is provided in FIG. 10A . As shown in FIG. 10A , relative to FIG. 7K , no TMV interconnect structure 795 is formed. Also as shown in FIG. 10A , relative to FIG. 1K , the molding material 735 does not cover the interconnect structure.

Also for example, as explained herein, mold grinding (or thinning) at block 899 may be skipped or may be performed to the extent that the top of the assembly 700I and/or at least one of the dies 725, 726 is covered with molding material 735. FIG. 10A is a diagrammatic representation of an example of such a process. Generally speaking, the assembly 1000A of FIG. 10A is similar to the assembly 700K of FIG. 7K minus the interconnect structure 795, and wherein the molding material 735 covers the assembly 700I.

In addition, as explained herein, mold grinding (or thinning) at block 899 may be performed to an extent that the top of the assembly 700I and/or one or more of the dies 725, 726 are exposed from the molding material 735 (and/or molding material 730). FIG. 10B is a diagram that provides an example of such a process. In general, the assembly 1000B of FIG. 10B is similar to the assembly 700K of FIG. 7K, minus the interconnect structure 795.

In another example, as explained herein, in the discussion of block 897, the TMV interconnects may include any of a variety of structures, such as a conductive post (e.g., a plated post or pillar, a vertical wire, etc.). FIG. 11A is an illustration of an example of a conductive post 1121 attached to the substrate 793. The conductive posts 1121 may, for example, be plated on the substrate 793. The conductive posts 1121 may, for example, also include wires (e.g., wire-bonded wires) attached (e.g., wire-bonded attachment, soldered, etc.) to the substrate 793 and extending vertically. The conductive posts 1121 may, for example, extend from the substrate 793 to a height that is greater than a height of the die 725, 726, equal to a height of one or more of the die 725, 726, less than a height of the die 725, 726, etc. Note that any number of rows of pillars 1121 may be formed. In general, assembly 1100A of FIG. 11A is similar to assembly 700K of FIG. 7K (minus the mold compound 735), with conductive pillars 1121 as interconnect structures instead of elongated conductive balls 795.

Continuing with the example, FIG. 11B depicts substrate 793, conductive pillars 1121, assembly 700I (e.g., semiconductor die 725, 726), and underfill 794 covered with molding material 735. The molding may be performed, for example, according to block 899 of method 800 of the example. In general, assembly 1100B of FIG. 11B is similar to assembly 700K of FIG. 7K, having conductive pillars 1121 as interconnects instead of elongated conductive balls 795, and having molding material 735 that has not been thinned or has not been thinned enough to expose assembly 700I.

Still continuing with the example, FIG. 11C depicts the molding material 735 having been thinned (e.g., ground) to a desired thickness. The thinning may, for example, be performed according to block 899 of the example method 800. For example, it is noted that the conductive posts 1121 and/or the assembly 700I (e.g., including the molding material 730 and/or the semiconductor dies 725, 726) may also be thinned. For example, the thinning of the molding material 735 may expose the top of the conductive post 1121. However, if the thinning of the molding material 735 does not expose the top of the conductive post 1121, a mold strip operation may be performed. Note that although the assembly 1100C is shown with the tops of the semiconductor dies 725, 726 of the assembly 700I exposed, those tops need not necessarily be exposed.

In general, assembly 1100C of FIG. 11C is similar to assembly 700K of FIG. 7K , having conductive posts 1121 as interconnect structures instead of elongated conductive balls 795 .

Continuing with the example, the assembly 1100C shown in FIG. 11C can be further processed by forming a redistribution layer (RDL) 1132 over the molding material 735 and the assembly 700I (e.g., including the molding material 730 and/or the semiconductor dies 725, 726 thereof). FIG. 11D shows an example of such processing. The redistribution layer 1132 may also be referred to herein as a backside redistribution (RDL) layer 1132. Although the formation of such a backside RDL is not explicitly shown in one of the blocks of the example method 800, such an operation may be performed in any of the blocks, such as after the mold grinding operation of the block 899 (if performed).

11D , a first backside dielectric layer 1133 may be formed and patterned on the molding material 735 and the assembly 700I (e.g., including the molding material 730 and/or the semiconductor dies 725, 726 thereof). The first backside dielectric layer 1133 may be formed and patterned in a manner similar to or similar to the RDL dielectric layer 771 formed in the block 855, albeit on a different surface. For example, the first back dielectric layer 1133 may be formed on the molding material 735 and/or on the component 700I (e.g., including the molding material 730 and/or its semiconductor grains 725, 726), for example, directly on the exposed back surface of the grains 725, 726, on the molding material 730 and/or 735 covering the back surface of the grains 725, 726, and the like, and a through hole 1134 may be formed in the first back dielectric layer 1133 (e.g., by etching, stripping, etc.) to expose at least the top of the conductive pillar 1121.

Backside wiring 1135 may be formed on the first backside dielectric layer 1133 and in the through-holes 1134 of the first backside dielectric layer 1133. The backside wiring 1135 may thus be electrically connected to the conductive pillars 1121. The backside wiring 1135 may, for example, be formed in the same or similar manner as the RDL wiring 782 formed in the block 865. At least some, if not all, of the backside wiring 1135 may, for example, extend from the conductive pillars 1121 to a position directly above the assembly 700I (e.g., including the molding material 730 and/or the semiconductor dies 725, 726 thereof). At least some of the backside lines 1135 may also extend from the conductive post 1121 to a location that is not directly above the component 700I (eg, including the molding material 730 and/or the semiconductor dies 725 , 726 ), for example.

A second back dielectric layer 1136 can be formed and patterned on the first back dielectric layer 1133 and the back lines 1135. The second back dielectric layer 1136 can be formed and patterned, for example, in a manner the same or similar to the RDL dielectric layer 771 formed in block 855, albeit on a different surface. For example, the second back dielectric layer 1136 can be formed on the first back dielectric layer 1133 and on the back lines 1135, and vias 1137 can be formed in the second back dielectric layer 1136 (e.g., by etching, stripping, etc.) to expose contact areas for the back lines 1135.

Backside interconnect pads 1138 (e.g., ball contact pads, planes, terminals, etc.) may be formed on the second backside dielectric layer 1136 and/or in vias 1137 in the second backside dielectric layer 1136. The backside interconnect pads 1138 may thus be electrically connected to the backside lines 1135. The backside interconnect pads 1138 may, for example, be formed in the same or similar manner as the RDL lines formed in block 865. The backside interconnect pads 1138 may, for example, be formed by forming metal contact pads and/or forming bump undermetallization (e.g., to enhance subsequent attachment to the backside lines 1135 by other interconnect structures).

Although the backside RDL layer 1132 is shown as having two backside dielectric layers 1133, 1136 and a layer of backside wiring 1135, it should be understood that any number of dielectric and/or wiring layers may be formed.

Although not shown in FIG. 11D , interconnect structures may be formed on the substrate 793 , for example on a side of the substrate 793 opposite the assembly 700I and the molding material 735 , as discussed herein, for example, with respect to block 886 and FIG. 7K .

In another example embodiment, a substrate (e.g., a laminate substrate, a packaging substrate, etc.) may be attached to the assembly 700I (e.g., including the semiconductor dies 725, 726 and the molding material 730) and the molding material 735, for example as an alternative to or in addition to the backside RDL discussed in relation to FIGS. 11A-11D herein.

For example, as depicted in FIG. 12A , the interconnect structures 795 may be formed at a height that will extend at least to the height of the assembly 700I. Note that this height need not exist, such as in a scenario where the back substrate has its own interconnect structures, or where additional interconnect structures are utilized between the interconnect structures 795 and the back substrate. The interconnect structures 795 may, for example, be attached in the same or similar manner as discussed herein with respect to block 897 and FIG. 7K .

Continuing with the example, as depicted in FIG12A, the assembly 1200A can be molded using a molding material 735, and if necessary, the molding material 735 can be thinned. Such molding and/or thinning can be performed in the same or similar manner as discussed in relation to block 899 and FIG7K, for example.

As shown in FIG. 12B , a back substrate 1232 may be attached. For example, the back substrate 1232 may be electrically connected to the interconnect structure 795 and/or mechanically attached to the molding material 735 and/or the assembly 700I (e.g., the molding material 730 and/or the semiconductor die 725, 726). The back substrate 1232 may be attached, for example, in a panel form and/or in a single package form, and may be attached, for example, before or after singulation.

As discussed herein, after the assembly 700I is attached to the substrate 793, the substrate 793 and/or the assembly 700I may be covered with a molding material. Alternatively or additionally, the substrate 793 and/or the assembly 700I may be covered with a cover or stiffener. FIG. 13 provides an example of this. FIG. 13 generally shows the assembly 700J of FIG. 7J with a cover 1310 (or stiffener) added.

The cover 1310 may include, for example, metal and provide electromagnetic shielding and/or heat dissipation. For example, the cover 1310 may be electrically coupled to a ground line on the substrate 793 to provide shielding. The cover 1310 may be coupled to the substrate 793 using, for example, solder and/or a conductive epoxy. Although not shown, a thermal interface material may be formed in a gap 1315 between the assembly 700I and the cover 1310.

Although most of the examples shown and discussed herein generally show only the assembly 700I attached to the substrate 793, other components (e.g., active and/or passive components) may also be attached to the substrate 793. For example, as shown in FIG. 14 , a semiconductor die 1427 may be attached (e.g., flip chip bonding, wire bonding, etc.) to the substrate 793. The semiconductor die 1427 is attached to the substrate 793 in a manner that is laterally adjacent to the assembly 700I. After such attachment, any of the packaging structures discussed herein (e.g., interconnect structures, molding, lids, etc.) may then be formed.

In another exemplary embodiment, other components may be coupled to the top side of the assembly 700I in a vertically stacked assembly. FIG. 15 shows an example of such an assembly 1500C. A third die 1527 and a fourth die 1528 (e.g., their non-active sides) may be attached to the top of the assembly 700I. Such attachment may be performed, for example, using an adhesive. The bonding pads on the active sides of the third die 1527 and the fourth die 1528 may then be wire bonded to the substrate 793. Note that in a scenario where an RDL and/or substrate is attached to the assembly 700I, the third die 1527 and/or the fourth die 1528 may be flip-chip bonded to such RDL and/or substrate. Following such attachment, any of the packaging structures discussed herein (e.g., interconnect structures, molding, lid, etc.) may then be formed.

In yet another example embodiment, another component can be coupled to the bottom side of the substrate. FIG. 16 shows an example of such an assembly. A third die 1699 is attached to the bottom side of the substrate 793, for example, in a gap between interconnects on the bottom side of the substrate 793. After such attachment, any of the packaging structures discussed herein (e.g., interconnects, molding, lids, etc.) can then be formed.

The exemplary methods and assemblies shown in FIGS. 8-16 and discussed herein are non-limiting examples only and are presented to illustrate various features of the disclosure. Such methods and assemblies may also share any or all features with the methods and assemblies shown and discussed in the following co-applied U.S. patent applications: U.S. Patent Application Serial No. 13/753,120 filed on January 29, 2013 and entitled “Semiconductor Device and Method of Making a Semiconductor Device”; U.S. Patent Application Serial No. 13/863,457 filed on April 16, 2013 and entitled “Semiconductor Device and Method of Making the Same”; U.S. Patent Application Serial No. 14/083,779, filed on November 19, 2013, and entitled "Semiconductor Device with Through Silicon Via - Less Deep Well"; U.S. Patent Application Serial No. 14/218,265, filed on March 18, 2014, and entitled "Semiconductor Device and Method of Making the Same"; U.S. Patent Application Serial No. 14/313,726, filed on June 24, 2014, and entitled "Semiconductor Device and Method of Making the Same" 4; U.S. Patent Application Serial No. 14/444,450, filed on July 28, 2014, and entitled "Semiconductor Device with Thin Redistribution Layer"; U.S. Patent Application Serial No. 14/524,443, filed on October 27, 2014, and entitled "Semiconductor Device with Reduced Thickness"; U.S. Patent Application Serial No. 14/524,443, filed on November 4, 2014, and entitled "Interposer, Method of Making Same, Semiconductor Package Using Same, and Method for Making Same" Serial No. 14/532,532, filed on November 18, 2014, and entitled "Semiconductor device with reduced warp"; U.S. Patent Application Serial No. 14/546,484, filed on November 18, 2014, and entitled "Semiconductor device and method of making the same"; and U.S. Patent Application Serial No. 14/671,095, filed on March 27, 2015, and entitled "Semiconductor device and method of making the same"; the contents of each of these U.S. Patent Applications are hereby incorporated by reference in their entirety.

The discussion herein includes many illustrative figures showing various portions of semiconductor package components. For purposes of illustration, these figures do not show all features of each exemplary component. Any of the exemplary components presented herein may share any or all features with any or all of the other exemplary components presented herein. For example and without limitation, any or a portion of the exemplary components shown and discussed with respect to FIGS. 1-7 may be incorporated into any of the exemplary components discussed with respect to FIGS. 8-16. Conversely, any of the exemplary components shown and discussed with respect to FIGS. 8-16 may be incorporated into the exemplary components shown and discussed with respect to FIGS. 1-7.

In summary, the various features of this disclosure provide a semiconductor device or package structure and a method for manufacturing the same. Although the previous content has been described with reference to certain features and examples, it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted without departing from the scope of the disclosure. In addition, many modifications can be made to adapt a particular situation or material to the teachings of the disclosure without departing from the scope thereof. Therefore, it is intended that the disclosure is not limited to the specific examples disclosed, but that the disclosure will include all examples that fall within the scope of the attached patent application.

100A: Redistributed structure (RD) wafer 100B: Assembly 100C: Molded assembly 100D: Assembly 100J: Package 105: Support layer 110: Redistributed structure (RD) 111: Base dielectric layer 112: First conductive line 113: First dielectric layer 114: Conductive via 115: Second conductive line 116: Second dielectric layer 117: Interconnect structure 119: Contact 121: Interconnect structure 125: First die 126: Second die 128: Underfill 130: Molding material 140: Via 150: Wafer support structure 171: first RDL dielectric layer 172: via 181: first portion of first RDL line 182: second portion of first RDL line 183: second RDL dielectric layer 184: via 185: third RDL layer 191: second RDL line 192: interconnect structure 200: method 205, 210, 215, 220, 225, 230, 235, 240, 245, 250, 255, 260, 265, 270, 275, 280, 285, 290, 295: block 300B: package 400C: assembly 400D: assembly 500A: assembly 500B: assembly 500C: assembly 500D: assembly 521: conductive pillar 532: redistribution layer (RDL) 533: first back dielectric layer 534: via 535: back wiring 536: second back dielectric layer 537: via 538: back interconnect pad 600B: assembly 621: interconnect structure 632: back substrate 700A: RD wafer 700B: assembly 700C: molded assembly 700D: assembly 700I: assembly 700J: assembly 700K: assembly 700L: assembly 705: support layer 710: redistribution (RD) structure 711: base dielectric layer 712: first conductive line 713: first dielectric layer 714: conductive via 715: second conductive line 716: second dielectric layer 717: interconnect structure 725: first semiconductor die 726: second semiconductor die 728: underfill 730: molding material 735: molding material 750: wafer support structure 771: RDL dielectric layer 772: via 781: first portion of first RDL line 782: second portion of first RDL line 791: plane 792: interconnect structure 793: substrate 794: underfill 795: interconnect structure 800: method 805, 810, 820, 825, 830, 835, 845, 850, 855, 860, 865, 885, 886, 890, 895, 896, 897, 898, 899: block 940: via 1000A: assembly 1000B: assembly 1100A: assembly 1100B: assembly 1100C: assembly 1121: conductive column 1132: redistribution layer (RDL) 1133: first back dielectric layer 1134: via 1135: back wiring 1136: second back dielectric layer 1137: via 1138: back interconnect pad 1200A: assembly 1232: back substrate 1310: lid 1315: gap 1427: semiconductor die 1500C: assembly 1527: third die 1528: fourth die 1699: third die

The attached drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The drawings depict examples of the present disclosure and are used together with the description to explain various principles of the present disclosure. In the drawings: [FIG. 1A]-[FIG. 1J] are cross-sectional views showing a semiconductor package according to various features of the present disclosure and a method for manufacturing a semiconductor package. [FIG. 2] is a flow chart of a method for manufacturing a semiconductor package according to various features of the present disclosure. [FIG. 3A]-[FIG. 3B] are cross-sectional views showing a semiconductor package according to various features of the present disclosure and a method for manufacturing a semiconductor package. [FIG. 4A]-[FIG. 4D] are cross-sectional views showing a semiconductor package of an example and a method for manufacturing a semiconductor package according to various features of the present disclosure. [FIG. 5A]-[FIG. 5F] are cross-sectional views showing a semiconductor package of an example and a method for manufacturing a semiconductor package according to various features of the present disclosure. [FIG. 6A]-[FIG. 6D] are cross-sectional views showing a semiconductor package of an example and a method for manufacturing a semiconductor package according to various features of the present disclosure. [FIG. 7A]-[FIG. 7L] are cross-sectional views showing a semiconductor package of an example and a method for manufacturing a semiconductor package according to various features of the present disclosure. [FIG. 8] is a flow chart of a method for manufacturing a semiconductor package according to various features of the present disclosure. [FIG. 9] is a cross-sectional view showing a semiconductor package according to various features of the present disclosure and a method for manufacturing a semiconductor package. [FIG. 10A]-[FIG. 10B] are cross-sectional views showing a semiconductor package according to various features of the present disclosure and a method for manufacturing a semiconductor package. [FIG. 11A]-[FIG. 11D] are cross-sectional views showing a semiconductor package according to various features of the present disclosure and a method for manufacturing a semiconductor package. [FIG. 12A]-[FIG. 12B] are cross-sectional views showing a semiconductor package according to various features of the present disclosure and a method for manufacturing a semiconductor package. [FIG. 13] is a cross-sectional view showing a semiconductor package according to various features of the present disclosure and a method for manufacturing a semiconductor package. [FIG. 14] is a cross-sectional view showing a semiconductor package according to various features of the present disclosure and a method for manufacturing a semiconductor package. [FIG. 15] is a cross-sectional view showing a semiconductor package according to various features of the present disclosure and a method for manufacturing a semiconductor package. [FIG. 16] is a cross-sectional view showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package depicting various features according to the present disclosure.

100J:Packaging

110: Redistribution (RD) structure

121: Interconnection structure

125: First grain

126: Second grain

191: Second RDL line

192: Interconnection structure

Claims (20)

A semiconductor device, comprising: a first redistribution structure, comprising a first redistribution structure first side and a first redistribution structure second side opposite to the first redistribution structure first side; a semiconductor die, comprising a die first side and a die second side, wherein the die first side is coupled to the first redistribution structure second side; an interconnection structure, comprising an interconnection structure first side and an interconnection structure second side connected to the interconnection structure a first side of the semiconductor die and a second side of the semiconductor die opposite to the first side of the semiconductor die; a first side of the semiconductor die and a second side of the semiconductor die opposite to the first side of the semiconductor die; a second side of the semiconductor die and a first side of the semiconductor die opposite to the first side of the semiconductor die; a second side of the semiconductor die and a second side of the semiconductor die opposite to the first side of the semiconductor die; a first side of the semiconductor die and a second side of the semiconductor die opposite to the first side of the semiconductor die; The second redistribution structure comprises: a first side of the second redistribution structure, the first side of the second redistribution structure is located on and contacts the second side of the encapsulation material; a second side of the second redistribution structure, the second side of the second redistribution structure is opposite to the first side of the second redistribution structure; a plurality of second redistribution structure dielectric layers and a plurality of second redistribution structure conductive layers, The plurality of second redistribution structure dielectric layers and the plurality of second redistribution structure conductive layers are between the first side of the second redistribution structure and the second side of the second redistribution structure; and a component connection pad, the component connection pad is at the second side of the second redistribution structure, wherein the component connection pad is coupled to the second side of the interconnect structure via the plurality of second redistribution structure conductive layers. A semiconductor device as described in claim 1, wherein the second redistribution structure comprises: a second redistribution structure first dielectric layer among the plurality of second redistribution structure dielectric layers, comprising a first side on the second side of the encapsulation material and contacting the second side of the encapsulation material; a second redistribution structure first conductive via, which passes through the second redistribution structure first dielectric layer and is coupled to the second side of the interconnect structure; a second redistribution structure first conductive line among the plurality of second redistribution structure conductive layers, comprising a first side on the second redistribution structure first dielectric layer; A second redistribution structure second dielectric layer in the device, comprising a first side on the second side of the second redistribution structure first dielectric layer, wherein the second redistribution structure second dielectric layer covers the lateral side and the second side of the second redistribution structure first conductive line; a second redistribution structure second conductive via, comprising a first side coupled to the second side of the second redistribution structure first conductive line and extending vertically from the second side of the second redistribution structure first conductive line to the second side of the second redistribution structure second dielectric layer; and a component connection pad coupled to the second redistribution structure second conductive via. A semiconductor device as described in claim 2, wherein the first conductive via of the second redistribution structure includes a metal plating layer that extends completely through the first dielectric layer of the second redistribution structure. A semiconductor device as described in claim 2, wherein the first conductive via of the second redistribution structure runs through the first dielectric layer of the second redistribution structure in a substantially vertical direction. A semiconductor device as described in claim 2, wherein in a vertical cross-section, the first dielectric layer of the second redistribution structure does not have any embedded circuits running in the horizontal direction. A semiconductor device as described in claim 1, wherein the interconnect structure includes a column, wherein the column includes a metal coating or a wire. A semiconductor device as described in claim 1, wherein the second redistribution structure is coreless. A semiconductor device as described in claim 1, wherein: the first redistribution structure includes a first redistribution structure first dielectric layer and a ball contact; the first redistribution structure first dielectric layer includes a first side and a second side opposite to the first side; the ball contact includes a plated pad layer embedded in the second side of the first redistribution structure first dielectric layer; the plated pad layer includes a first side of the plated pad layer facing the first side of the first redistribution structure first dielectric layer and a second side of the plated pad layer opposite to the first side of the plated pad layer; and the first side of the plated pad layer is higher than the first side of the first redistribution structure first dielectric layer. A semiconductor device as described in claim 2, wherein the first conductive line of the second redistribution structure is directly located on the first dielectric layer of the second redistribution structure. A semiconductor device as described in claim 1, wherein: the encapsulation material covers the second side of the die; and the second side of the encapsulation material is coplanar with two sides of the interconnect structure. A semiconductor device, comprising: a first redistribution structure, comprising a plurality of first redistribution structure dielectric layers and a plurality of first redistribution structure conductive layers, the plurality of first redistribution structure dielectric layers and the plurality of first redistribution structure conductive layers being between a first side of the first redistribution structure and a second side of the first redistribution structure, wherein the first redistribution structure is coreless, and the plurality of first redistribution structure dielectric layers laterally surround the plurality of first redistribution structure conductive layers; A first semiconductor die, comprising a first semiconductor die first side and a first semiconductor die second side, wherein the first semiconductor die first side is coupled to the first redistribution structure second side; a first interconnect structure, comprising a first interconnect structure first side and a first interconnect structure second side opposite to the first interconnect structure first side, wherein the first interconnect structure first side is coupled to the first redistribution structure second side; a second interconnect structure, comprising a second interconnect structure first side and a second interconnect structure second side opposite to the second interconnect structure first side a second interconnect structure second side opposite to the first redistribution structure first side, wherein the second interconnect structure first side is coupled to the first redistribution structure second side; an encapsulation material, comprising an encapsulation material first side and an encapsulation material second side opposite to the first encapsulation material first side, wherein the encapsulation material first side is on the first redistribution structure second side, and wherein the encapsulation material laterally surrounds the first semiconductor die; and a second redistribution structure, comprising: a second redistribution structure first side, the second The first side of the redistribution structure is located on the second side of the encapsulation material and contacts the second side of the encapsulation material; the second side of the second redistribution structure, the second side of the second redistribution structure is opposite to the first side of the second redistribution structure; a plurality of second redistribution structure dielectric layers and a plurality of second redistribution structure conductive layers, the plurality of second redistribution structure dielectric layers and the plurality of second redistribution structure conductive layers are between the first side of the second redistribution structure and the second side of the second redistribution structure. A semiconductor device as described in claim 11, wherein: the plurality of first redistributed structure dielectric layers include a first redistributed structure first dielectric layer, a first redistributed structure second dielectric layer, and a first redistributed structure third dielectric layer; and the first redistributed structure first dielectric layer, the first redistributed structure second dielectric layer, and the first redistributed structure third dielectric layer laterally surround the plurality of first redistributed structure conductive layers. The semiconductor device of claim 11, wherein: the second redistribution structure first dielectric layer of the plurality of second redistribution structure dielectric layers comprises a first side located on the second side of the encapsulation material; the second redistribution structure comprises a second redistribution structure first conductive via; the second redistribution structure first conductive via extends through the second redistribution structure first dielectric layer and is coupled to the first interconnect structure; the second redistribution structure first conductive line of the plurality of second redistribution structure conductive lines comprises a second redistribution structure first conductive via located on the second redistribution structure first conductive via; A first side on the second side of a dielectric layer; a second redistributed structure second dielectric layer among the plurality of second redistributed structure dielectric layers includes a first side located on the second side of the second redistributed structure first dielectric layer, wherein the second redistributed structure second dielectric layer covers the lateral side and the second side of the second redistributed structure first conductive line; and an upper conductive via extends from the second side of the second redistributed structure second dielectric layer through the second redistributed structure second dielectric layer to the second side of the second redistributed structure first conductive line. The semiconductor device of claim 11 comprises: a second semiconductor die, comprising a first side of the second semiconductor die and a second side of the second semiconductor die; wherein the first side of the second semiconductor die is coupled to the second side of the first redistribution structure; wherein the first semiconductor die is laterally positioned between the first interconnect structure and the second interconnect structure; and wherein the second semiconductor die is laterally positioned between the first semiconductor die and the second interconnect structure. A semiconductor device as claimed in claim 11, wherein the second side of the second redistribution structure includes an interconnect pad directly vertically above the first semiconductor die. A semiconductor device as described in claim 11, wherein the first interconnect structure includes an electroplated pillar. The semiconductor device as claimed in claim 14 comprises: an underfill between the first side of the first die and the second side of the first redistribution structure and between the first side of the second die and the second side of the first redistribution structure; and wherein the underfill extends laterally from the first semiconductor die to the second semiconductor die along the second side of the first redistribution structure. A semiconductor device as described in claim 13, wherein the first dielectric layer of the second redistribution structure contacts the second side of the encapsulation material. A semiconductor device as described in claim 18, wherein the first dielectric layer of the second redistribution structure covers the entire second side of the encapsulation material. A method for manufacturing a semiconductor device, the method comprising: providing a first redistribution structure, the first redistribution structure comprising a first redistribution structure first side and a first redistribution structure second side opposite to the first redistribution structure first side; providing a semiconductor die, the semiconductor die comprising a die first side and a die second side, wherein the die first side is coupled to the first redistribution structure second side; providing an interconnect The method further comprises providing an interconnect structure, the interconnect structure comprising an interconnect structure first side and an interconnect structure second side opposite to the interconnect structure first side, wherein the interconnect structure first side is coupled to the first redistribution structure second side; providing an encapsulation material, the encapsulation material comprising an encapsulation material first side and an encapsulation material second side opposite to the encapsulation material first side, wherein the encapsulation material first side is on the first redistribution structure second side, and wherein the encapsulation material The encapsulation material laterally surrounds the semiconductor die; and provides a second redistribution structure, including: a second redistribution structure first side, the second redistribution structure first side is located on and contacts the second side of the encapsulation material; a second redistribution structure second side, the second redistribution structure second side is opposite to the second redistribution structure first side; a plurality of second redistribution structure dielectric layers and a plurality of first redistribution structure dielectric layers; A second redistribution structure conductive layer, the plurality of second redistribution structure dielectric layers and the plurality of second redistribution structure conductive layers are between the first side of the second redistribution structure and the second side of the second redistribution structure; and a component connection pad, the component connection pad is at the second side of the second redistribution structure, wherein the component connection pad is coupled to the second side of the interconnect structure via the plurality of second redistribution structure conductive layers.