CN111211174A - SGT-MOSFET semiconductor device - Google Patents
SGT-MOSFET semiconductor device Download PDFInfo
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- CN111211174A CN111211174A CN202010203302.4A CN202010203302A CN111211174A CN 111211174 A CN111211174 A CN 111211174A CN 202010203302 A CN202010203302 A CN 202010203302A CN 111211174 A CN111211174 A CN 111211174A
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- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 13
- 238000005516 engineering process Methods 0.000 abstract description 2
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- 230000003071 parasitic effect Effects 0.000 description 2
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- 230000015556 catabolic process Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
本发明提供一种SGT‑MOSFET半导体器件，属于半导体技术领域，其结构包括N型重掺杂半导体衬底和位于N型重掺杂半导体衬底上表面的N型半导体漂移区；N型半导体漂移区的上表面设有P型区，P型区上表面设有N型重掺杂半导体源区，N型重掺杂半导体源区设有贯穿P型区并延伸至N型半导体漂移区中的控制栅；N型重掺杂半导体源区设有贯穿P型区并延伸至N型半导体漂移区中的屏蔽栅；控制栅设置有至少一个，屏蔽栅设置有至少两个，控制栅设置在相临的两个屏蔽栅之间。本发明利用分裂栅和浮置P阱技术极大改善了沟槽栅器件性能。本发明的浮置P阱配置、以及N‑漂移区的配置具有优化的电场分布结构，提高器件耐压，降低导通电阻，从而降低驱动损耗和开关损耗。
The invention provides an SGT-MOSFET semiconductor device, which belongs to the technical field of semiconductors. Its structure includes an N-type heavily doped semiconductor substrate and an N-type semiconductor drift region located on the upper surface of the N-type heavily doped semiconductor substrate; The upper surface of the region is provided with a P-type region, the upper surface of the P-type region is provided with an N-type heavily doped semiconductor source region, and the N-type heavily doped semiconductor source region is provided with a P-type region and extending into the N-type semiconductor drift region. The control gate; the N-type heavily doped semiconductor source region is provided with a shielding gate that penetrates the P-type region and extends into the N-type semiconductor drift region; between the two shielding grilles. The present invention greatly improves the performance of the trench gate device by utilizing the split gate and floating P well technology. The floating P-well configuration and the configuration of the N-drift region of the present invention have an optimized electric field distribution structure, improve the withstand voltage of the device, and reduce the on-resistance, thereby reducing the driving loss and switching loss.
Description
Technical Field
The invention relates to the technical field of power semiconductors, in particular to an SGT-MOSFET semiconductor device.
Background
The SGT-MOSFET is a novel power semiconductor device, has the advantages of low conduction loss of the traditional deep-groove MOSFET, and simultaneously has lower switching loss. The SGT-MOSFET is used as a switching device and applied to a motor driving system, an inverter system and a power management system in the fields of new energy electric vehicles, novel photovoltaic power generation, energy-saving household appliances and the like, and is a core power control component.
The SGT-MOSFET is an MOSFET with a deep groove longitudinal structure, an independent field plate between a drain end and a gate end is adopted, a shielding gate is connected with a source electrode potential, and source-drain parasitic capacitance formed between the shielding gate and a drain electrode does not obviously increase the switching time of a device. The SGT-MOSFET power device has smaller gate-drain parasitic capacitance, low switching loss, higher switching speed and better device performance.
The trench structure of a conventional SGT-MOSFET consists of two polysilicon portions: the upper half is the control gate and the lower half is the shield gate, which is located under the control gate, as shown in fig. 1. When the device is conducted, the drain current forms an inversion layer channel on the surface of the body region along the longitudinal side wall of the groove. When the source is forward biased, electrons travel from the source region to the drain region along the inversion layer channel. Electrons pass through the channel from the source region, enter the drift region at the bottom of the trench gate, and then the current spreads out over the entire cell cross-sectional width.
The electric field distribution structure of the traditional structure is single, the on-resistance is large, the voltage resistance of the device is poor, and the driving loss and the switching loss are too large.
Disclosure of Invention
The technical task of the invention is to solve the defects of the prior art and provide an SGT-MOSFET semiconductor device.
The technical scheme of the invention is realized in the following way, the SGT-MOSFET semiconductor device comprises an N-type heavily doped semiconductor substrate (1) and an N-type semiconductor drift region (2) positioned on the upper surface of the N-type heavily doped semiconductor substrate (1);
the upper surface of the N-type semiconductor drift region (2) is provided with a P-type region (3),
the upper surface of the P-type region (3) is provided with an N-type heavily doped semiconductor source region (4),
the N-type heavily doped semiconductor source region (4) is provided with a control gate (5) which penetrates through the P-type region (3) and extends into the N-type semiconductor drift region (2);
the N-type heavily doped semiconductor source region (4) is provided with a shielding grid (6) which penetrates through the P-type region (3) and extends into the N-type semiconductor drift region (2);
at least one control grid (5) is arranged, at least two shielding grids (6) are arranged,
the control grid (5) is arranged between two adjacent shielding grids (6);
the control grid (5) is provided with a control grid insulating medium (7) which is contacted with the N-type semiconductor drift region (2), the P-type region (3) and the N-type heavily doped semiconductor source region (4), and the control grid (5) is provided with a control grid conductive material (9) which is surrounded by the control grid insulating medium (7);
the shielding grid (6) is provided with a shielding grid insulating medium (77) which is in contact with the N-type semiconductor drift region (2), the P-type region (3) and the N-type heavily doped semiconductor source region (4) and a shielding grid conducting material (8) which is surrounded by the shielding grid insulating medium (77);
a source electrode (12) is led out from the upper surface of the N-type heavily doped semiconductor source region (4),
a shielding grid source electrode (13) is led out from the upper surface of the shielding grid conductive material (8);
a gate electrode (14) is led out from the upper surface of the control gate conductive material (9),
the drain electrode (15) is led out from the lower surface of the N-type heavily doped semiconductor substrate (1).
The device can be only provided with three polysilicon parts, wherein the three polysilicon parts are respectively a control gate and two shielding gates, and the control gate is arranged between the two shielding gates which are adjacent to each other at the left and the right.
The control gate (5) penetrates through the P-type region (3) layer from the surface of the N-type heavily doped semiconductor source region (4) layer downwards and extends into the N-type semiconductor drift region (2) layer;
the shielding grid (6) penetrates through the P-type region (3) layer from the surface of the N-type heavily doped semiconductor source region (4) layer downwards and extends into the N-type semiconductor drift region (2) layer.
The depth of the bottom end of the shielding grid (6) extending downwards into the N-type semiconductor drift region (2) is larger than the depth of the bottom end of the control grid (5) extending downwards into the N-type semiconductor drift region (2).
The adjacent control gate (5) and the shielding gate (6) are arranged with the separation distance of the N-type heavily doped semiconductor source region (4), the P-type region (3) and the N-type semiconductor drift region (2).
Design one with floating P-well (10):
the bottom end of the control gate (5) extending into the N-type semiconductor drift region (2) is provided with a floating P well (10) in the N-type semiconductor drift region (2), and the floating P well (10) at the bottom end of the control gate (5) and the N-type semiconductor drift region (2) form a PN junction.
Design scheme two with floating P well (10):
the bottom end of the shielding grid (6) extending into the N-type semiconductor drift region (2) layer is provided with a floating P well (10) in the N-type semiconductor drift region (2), and the floating P well (10) at the bottom end of the shielding grid (6) and the N-type semiconductor drift region (2) form a PN junction.
Design three with floating P well (10):
floating P wells (10) in the N-type semiconductor drift region (2) are arranged at the bottom ends of the control grid (5) and the shielding grid (6) which extend into the N-type semiconductor drift region (2);
a floating P trap (10) at the bottom end of the control grid (5) and the N-type semiconductor drift region (2) form a PN junction;
the floating P trap (10) at the bottom end of the shielding grid (6) and the N-type semiconductor drift region (2) form a PN junction.
Expanding the design scheme:
an N-drift region (11) layer is arranged between the bottom edge of the N-type semiconductor drift region (2) and the N-type heavily doped semiconductor substrate (1).
The optimization design scheme is as follows:
an N-drift region (11) layer is arranged between the bottom edge of the N-type semiconductor drift region (2) and the N-type heavily doped semiconductor substrate (1), and a floating P well (10) at the bottom end of the shielding grid (6) is arranged in the N-drift region (11) layer.
Compared with the prior art, the invention has the following beneficial effects:
the SGT-MOSFET semiconductor device provided by the invention has the advantages that the split gate and floating P well technology is utilized to obviously reduce the on resistance, the withstand voltage of the device is improved, and the performance of the trench gate device is greatly improved.
The floating P well configuration of the N-type semiconductor drift region and the configuration of the N-drift region have an optimized electric field distribution structure, the voltage resistance of the device is improved, and the on-resistance is reduced, so that the driving loss and the switching loss are reduced.
The SGT-MOSFET semiconductor device has the advantages of reasonable design, simple structure, safety, reliability, convenience in use, easiness in maintenance and good popularization and use values.
Drawings
FIG. 1 is a schematic diagram of a conventional SGT-MOSFET in the prior art;
FIG. 2 is a schematic structural diagram of a first embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a third embodiment of the present invention.
The reference numerals in the drawings denote:
1. n-type heavily doped semiconductor substrate, 2N-type semiconductor drift region, 3P-type region, 4N-type heavily doped semiconductor source region,
5. a control gate, 6, a shield gate,
7. a control gate insulating dielectric, 77, a shield gate insulating dielectric,
8. a shield gate conductive material, 9, a control gate conductive material,
10. the P-well is floated and the P-well,
11. an N-drift region is formed in the substrate,
12. source electrode, 13, shield gate source electrode, 14, gate electrode, 15, drain electrode.
Detailed Description
An SGT MOSFET semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
The SGT-MOSFET semiconductor device adopts a split gate structure and consists of three polysilicon parts: the device comprises an N-type heavily doped semiconductor substrate 1 and an N-type semiconductor drift region 2 positioned on the upper surface of the N-type heavily doped semiconductor substrate 1; the upper surface of the N-type semiconductor drift region 2 is provided with a P-type region 3; the upper surface of the P-type region 3 is provided with an N-type heavily doped semiconductor source region 4; the middle part of the N-type heavily doped semiconductor source region 4 is provided with a control gate 5 which penetrates through the P-type region 3 and extends into the N-type semiconductor drift region 2; the two sides of the N-type heavily doped semiconductor source region 4 are provided with shielding gates 6 which penetrate through the P-type region 3 and extend into the N-type semiconductor drift region 2; the shielding grid 6 is provided with a shielding grid insulating medium 77 which is contacted with the N-type semiconductor drift region 2, the P-type region 3 and the N-type heavily doped semiconductor source region 4 and a shielding grid conducting material 8 which is surrounded by the shielding grid insulating medium 77; the control gate 5 is provided with a control gate insulating medium 7 which is contacted with the N-type semiconductor drift region 2, the P-type region 3 and the N-type heavily doped semiconductor source region 4 and a control gate conductive material 9 which is surrounded by the control gate insulating medium 7; the bottom of the control gate 5 is provided with a floating P well 10 in an N-type semiconductor drift region 2; a source electrode 12 is led out from the upper surface of the N-type heavily doped semiconductor source region 4, a drain electrode 15 is led out from the lower surface of the N-type heavily doped semiconductor substrate 1, a gate electrode 14 is led out from the upper surface of the control gate conductive material 9, and a shielding gate source electrode 13 is led out from the upper surface of the shielding gate conductive material 8.
The first embodiment is as follows:
as shown in fig. 2, which is a schematic structural diagram of this example, compared with a conventional split gate structure, in the present invention, the floating P-well 10 is arranged at the bottom of the control gate 5 to adjust the electric field distribution at the upper part of the N-type drift region, the floating P-well 10 and the N-type semiconductor drift region form a PN junction and are mutually depleted, and meanwhile, a thick gate oxide layer is present at the bottom of the control gate, so that a large electric field cannot be concentrated, the withstand voltage of the device can be improved, and the on-resistance can be reduced; the shielding grid and the control grid are arranged in different grooves, the conducting channel density is increased, and a deep groove structure is adopted, so that the on-resistance of the device is obviously reduced, the increase of the resistivity of the adjacent N-type drift region caused by the floating P well is inhibited to a certain extent, and the device has smaller on-resistance.
Example two:
as shown in fig. 3, which is a schematic structural diagram of this example, compared with a conventional split gate structure, in the present invention, floating P-wells 10 are arranged at the bottoms of the shielding gates 6 on both sides to adjust the electric field distribution at the lower part of the N-type drift region, and the floating P-wells and the N-type semiconductor drift region form two PN junctions and are mutually depleted, so that the electric field at the bottom of the shielding gate in the N-type semiconductor drift region is weakened, thereby improving the withstand voltage of the device; the shielding grid and the control grid are arranged in different grooves, and the conducting resistance of the device is obviously reduced by increasing the density of the conducting channel and adopting a deep groove structure.
As shown in fig. 3, the difference between this example and embodiment 1 is that the floating P-well is disposed at the bottom of the shielding gates on both sides, so as to optimize the electric field distribution structure at the lower part of the N-type drift region and improve the withstand voltage of the device.
Example three:
expanding the optimized design, as shown in fig. 4, the difference between this example and embodiment 1 is that floating P-wells are respectively disposed at the bottom of a control gate and a shield gate, and two floating P-wells at the bottom of the shield gate are located in an N-drift region 11, so that the electric field distribution structures of an upper N-type drift region and a lower N-drift region are optimized, the withstand voltage of the device is improved, and the on-resistance is reduced.
As shown in fig. 4, which is a schematic structural diagram of this example, compared with a conventional split gate structure, floating P-wells are respectively disposed at the bottom of a control gate 5 and at the bottoms of shielding gates 6 on two sides at the same time to adjust electric field distribution of an N-type drift region at the upper portion and an N-drift region at the lower portion, the floating P-wells at the bottom of the control gate and the N-drift region form PN junctions and are mutually depleted, the floating P-wells at the bottom of the shielding gates and the N-drift region form two PN junctions and are mutually depleted, electric field distribution structures of the drift regions at the bottom of the control gate and the bottom of the shielding gates are optimized, voltage resistance of a device can be improved, and on; the shielding grid and the control grid are arranged in different grooves, and the conducting resistance of the device is obviously reduced by increasing the density of the conducting channel and adopting a deep groove structure.
Example four:
on the basis of the body structure of the above embodiment, the floating P-well is connected to the bottom of the control gate.
Example five:
on the basis of the body structure of the above embodiment, the floating P-well is connected to the bottom of the shield gate.
Embodiments one to three employ a floating P-well unconnected configuration. The fourth and fifth embodiments adopt the configuration that the floating P well is connected with the bottom of the control gate/shielding gate.
In the SGT-MOSFET structure existing in the prior art, a control gate and a shield gate are located in the same trench. The invention adopts the shielding grid and the control grid arranged in different grooves, and is an increased MOSFET structure.
In the prior art, a P-type floating layer is arranged at the bottom of each trench in a configuration structure, the discontinuity is illustrated by the distance between adjacent trenches, and the breakdown voltage is improved and the Rsp is reduced by changing the spike change of the electric field at the bottom of the trench. The invention utilizes the characteristic that the shielding grid and the control grid are positioned in different grooves and the difference of the depth of the grooves to optimize the electric field distribution of different parts in the drift region, thereby raising the withstand voltage of the device and reducing the on-resistance.
Claims (10)
1. An SGT-MOSFET semiconductor device is characterized by comprising an N-type heavily doped semiconductor substrate (1) and an N-type semiconductor drift region (2) located on the upper surface of the N-type heavily doped semiconductor substrate (1);
the upper surface of the N-type semiconductor drift region (2) is provided with a P-type region (3),
the upper surface of the P-type region (3) is provided with an N-type heavily doped semiconductor source region (4),
the N-type heavily doped semiconductor source region (4) is provided with a control gate (5) which penetrates through the P-type region (3) and extends into the N-type semiconductor drift region (2);
the N-type heavily doped semiconductor source region (4) is provided with a shielding grid (6) which penetrates through the P-type region (3) and extends into the N-type semiconductor drift region (2);
at least one control grid (5) is arranged, at least two shielding grids (6) are arranged,
the control grid (5) is arranged between two adjacent shielding grids (6);
the control grid (5) is provided with a control grid insulating medium (7) which is contacted with the N-type semiconductor drift region (2), the P-type region (3) and the N-type heavily doped semiconductor source region (4), and the control grid (5) is provided with a control grid conductive material (9) which is surrounded by the control grid insulating medium (7);
the shielding grid (6) is provided with a shielding grid insulating medium (77) which is in contact with the N-type semiconductor drift region (2), the P-type region (3) and the N-type heavily doped semiconductor source region (4) and a shielding grid conducting material (8) which is surrounded by the shielding grid insulating medium (77);
a source electrode (12) is led out from the upper surface of the N-type heavily doped semiconductor source region (4),
a shielding grid source electrode (13) is led out from the upper surface of the shielding grid conductive material (8);
a gate electrode (14) is led out from the upper surface of the control gate conductive material (9),
the drain electrode (15) is led out from the lower surface of the N-type heavily doped semiconductor substrate (1).
2. An SGT-MOSFET semiconductor device according to claim 1, wherein: the device adopts a split gate structure, three polysilicon parts are arranged in the device, the three polysilicon parts are respectively a control gate and two shielding gates, and the control gate is arranged between the two shielding gates which are adjacent left and right.
3. An SGT-MOSFET semiconductor device according to claim 1, wherein:
the control gate (5) penetrates through the P-type region (3) layer from the surface of the N-type heavily doped semiconductor source region (4) layer downwards and extends into the N-type semiconductor drift region (2) layer;
the shielding grid (6) penetrates through the P-type region (3) layer from the surface of the N-type heavily doped semiconductor source region (4) layer downwards and extends into the N-type semiconductor drift region (2) layer.
4. An SGT-MOSFET semiconductor device according to claim 1, wherein: the depth of the bottom end of the shielding grid (6) extending downwards into the N-type semiconductor drift region (2) is larger than the depth of the bottom end of the control grid (5) extending downwards into the N-type semiconductor drift region (2).
5. An SGT-MOSFET semiconductor device according to claim 1, wherein: the adjacent control gate (5) and the shielding gate (6) are arranged with the separation distance of the N-type heavily doped semiconductor source region (4), the P-type region (3) and the N-type semiconductor drift region (2).
6. An SGT-MOSFET semiconductor device according to any one of claims 1 to 5, wherein:
the bottom end of the control gate (5) extending into the N-type semiconductor drift region (2) is provided with a floating P well (10) in the N-type semiconductor drift region (2), and the floating P well (10) at the bottom end of the control gate (5) and the N-type semiconductor drift region (2) form a PN junction.
7. An SGT-MOSFET semiconductor device according to any one of claims 1 to 5, wherein:
the bottom end of the shielding grid (6) extending into the N-type semiconductor drift region (2) layer is provided with a floating P well (10) in the N-type semiconductor drift region (2), and the floating P well (10) at the bottom end of the shielding grid (6) and the N-type semiconductor drift region (2) form a PN junction.
8. An SGT-MOSFET semiconductor device according to any one of claims 1 to 5, wherein:
floating P wells (10) in the N-type semiconductor drift region (2) are arranged at the bottom ends of the control grid (5) and the shielding grid (6) which extend into the N-type semiconductor drift region (2);
a floating P trap (10) at the bottom end of the control grid (5) and the N-type semiconductor drift region (2) form a PN junction;
the floating P trap (10) at the bottom end of the shielding grid (6) and the N-type semiconductor drift region (2) form a PN junction.
9. An SGT-MOSFET semiconductor device according to any one of claims 1 to 5, wherein:
an N-drift region (11) layer is arranged between the bottom edge of the N-type semiconductor drift region (2) and the N-type heavily doped semiconductor substrate (1).
10. An SGT-MOSFET semiconductor device according to claim 4, wherein:
an N-drift region (11) layer is arranged between the bottom edge of the N-type semiconductor drift region (2) and the N-type heavily doped semiconductor substrate (1), and a floating P well (10) at the bottom end of the shielding grid (6) is arranged in the N-drift region (11) layer.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113809179A (en) * | 2021-10-20 | 2021-12-17 | 无锡橙芯微电子科技有限公司 | A SIC DMOS device structure |
| CN114792722A (en) * | 2021-01-25 | 2022-07-26 | 博盛半导体股份有限公司 | Shielded gate trench MOSFET |
| CN115799340A (en) * | 2023-01-09 | 2023-03-14 | 无锡先瞳半导体科技有限公司 | Shielded gate field effect transistor |
| CN118888596A (en) * | 2024-09-29 | 2024-11-01 | 深圳市港祥辉电子有限公司 | An enhanced lateral trench gate gallium oxide MOS device and its preparation method |
| CN119132960A (en) * | 2024-08-29 | 2024-12-13 | 深圳市至信微电子有限公司 | Field effect tube preparation method, field effect tube and integrated circuit |
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| CN115799340A (en) * | 2023-01-09 | 2023-03-14 | 无锡先瞳半导体科技有限公司 | Shielded gate field effect transistor |
| CN115799340B (en) * | 2023-01-09 | 2023-05-12 | 无锡先瞳半导体科技有限公司 | Shielded gate field effect transistor |
| CN119132960A (en) * | 2024-08-29 | 2024-12-13 | 深圳市至信微电子有限公司 | Field effect tube preparation method, field effect tube and integrated circuit |
| CN118888596A (en) * | 2024-09-29 | 2024-11-01 | 深圳市港祥辉电子有限公司 | An enhanced lateral trench gate gallium oxide MOS device and its preparation method |
| CN118888596B (en) * | 2024-09-29 | 2025-03-11 | 深圳市港祥辉电子有限公司 | An enhanced lateral trench gate gallium oxide MOS device and its preparation method |
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