CN102007584A - Semiconductor device structures and related processes - Google Patents

Abstract

The present invention discloses an improved, high-reliability power recessed field plate (RFP) structure, its fabrication process, and operational handling. The structure includes a plurality of localized dopant concentration regions located beneath the RFP trenches, which float or extend and merge with the MOSFET's body layer or connect to the source layer through vertically doped regions. These localized dopant regions reduce the device's body diode's minority carrier injection efficiency and alter the electric field distribution during the body diode's reverse recovery.

Description

Semiconductor device structures and related processes

Cross-references to related applications

This application claims priority to US Provisional Application Serial No. 61/065,759, filed February 14, 2008, which is hereby incorporated by reference in its entirety.

technical field

The present invention relates to a field effect transistor and a method, in particular to a highly reliable power insulated gate field effect transistor (MOSFET) with a recessed field plate (RFP, Recessed Field Plate) and related technologies.

Background technique

Power MOSFETs are widely used as switching devices in many electronic applications. In order to minimize conduction power loss, the MOSFET must have a low specific on-resistance, which is defined as the product of the on-resistance area (R _on *A), where R _on is the MOSFET resistance when the MOSFET is in the on state, and A is MOSFET area. Trench MOSFETs offer low specific on-resistance, especially in the 10-100 voltage range. As unit density increases, any associated capacitances such as gate-to-source capacitance Cgs, gate-to-drain capacitance Cgd, and/or drain-to-source capacitance Cds also increase. In many switching applications such as synchronous step-down DC-DC converters in mobile products, MOSFETs with a breakdown voltage of 30V typically operate at relatively high speeds close to 1MHz. Therefore, we want to minimize switching or dynamic power loss due to these capacitances. The magnitude of these capacitances is directly proportional to the gate charge Qg, the gate-drain charge Qgd, and the output charge Qoss. Furthermore, for devices operating in the third quadrant (ie, when the drain-body junction becomes forward biased), a small amount of charge is stored in the device during forward conduction. This stored charge causes a delay in switching from conduction to non-conduction. To overcome this delay, it is desirable to have a body diode with fast reverse recovery. However, fast recovery body diodes usually cause high Electromagnetic Interference (EMI), which means that during diode recovery, the ratio between the negative forward waveform (t _a ) and the positive forward waveform (t _b ) must be less than One, to avoid EMI problems.

As switching speed requirements for new applications increase to 1 MHz and beyond, state-of-the-art power MOSFETs are increasingly unable to operate satisfactorily at such high speeds. It is therefore desirable to have a power MOS transistor with low charges Qg, Qgd, Qoss and Qrr in addition to a low specific on-resistance (Ron*A).

There are currently two commonly used techniques to improve the switching performance of power MOSFETs. The first is trench-gate MOSFETs with thick bottom oxide, as shown in Figure 1 (US Patent No. 6,849,898), and the second is split polycrystalline Gate MOSFET structure in which the first polycrystalline gate is electrically shorted to the source electrode (US Pat. Nos. 5,998,833, 6,683,346), as shown in FIG. 2 .

As shown in Figure 3, the recent U.S. Patent Application No. 2008/0073707 filed by Darwish discloses a power MOSFET with a recessed field plate (RFP) structure to achieve a very short channel region (~0.25um) for further Reduces gate-source capacitance as well as gate-drain capacitance, thus reducing total gate charge (Qg) and "Miller" charge (Qgd). The RFP structure can additionally improve body diode reverse recovery speed by providing an additional current path and enhanced depletion of the drift region induced by the RFP.

Contents of the invention

The present application discloses improvements to power insulated gate field effect transistors having recessed field plates (RFPs) and similar structures. The inventors have realized that the performance of RFP-type power MOSFETs can be improved by performing compensating implants into the RFP trenches. This compensating implant helps to border the depletion region in the off state and thus helps to avoid punch through. Because of this, local enhancement can also be added to the doping between the channel and drain in the drift or extension region. This provides a synergistic combination in which the on-resistance can be improved without degrading the breakdown voltage.

In various embodiments, the disclosed innovations provide one or more of at least the following advantages. However, not all of these advantages are brought about by every innovative solution disclosed, and the list of these advantages does not limit the various inventions claimed.

● Improved (reduced) on-resistance;

● Improved (increased) breakdown voltage;

Reduce electrical stress on any dielectric layer on the bottom of the RFP trench;

● Higher reliability and longer operating life; and/or

• Improved ability to increase local doping concentration within the drift region.

Description of drawings

FIG. 1 is a cross-sectional view of a prior art MOSFET with a trenched gate having a thick bottom oxide structure.

FIG. 2 is a cross-sectional view of a prior art MOSFET with a split poly gate structure.

Figure 3 is a cross-sectional view of a prior art MOSFET with RFP parallel to the gate trench.

Figure 4(a) is a cross-sectional view of an RFP including a MOSFET structure with a floating deep compensation region.

Figure 4(b) is a cross-sectional view of an RFP comprising a MOSFET structure with a deep compensation region extending to and connected to the source electrode.

Figure 4(c) is a cross-sectional view of an RFP comprising a MOSFET structure with a deep compensation region extending into the P-body region.

Figure 5 shows a 2D voltage simulation comparison between the existing RFP-MOSFET structure and a MOSFET containing a deep compensation region.

Figures 6-18 show sequential steps in a sample process for fabricating the sample structure depicted in Figure 4(a).

19A is a cross-sectional view of a MOSFET structure including a P+ implanted region with a deep compensation region and extending beyond the P-N junction and into the N-drift region.

19B is a cross-sectional view of a MOSFET structure comprising a deep compensation region, which is a lightly doped p-region, and a P+ implanted region extending beyond the P-N junction and into the N-drift region.

19C is a cross-sectional view of a MOSFET structure including a deep compensation region, which is a lightly doped n-region, and a P+ implanted region extending beyond the P-N junction and into the N-drift region.

Figure 20 is a cross-sectional view of an RFP comprising a MOSFET structure with a deep compensation region and a N++ source region extending beyond the P-N junction and into the N drift region and fully recessed.

21-23 illustrate the fabrication process of one embodiment of the structure of FIG. 4(a) implemented in a split poly gate structure with a split poly layer structure within the RFP trench.

Figures 24A, 24B, 24C, 25A, 25B and 25C show RFPs comprising MOSFET structures with deep compensation regions (lightly doped p-regions in Figures 24B and 25B and lightly doped n-regions in Figures 24C and 25C). Implementing a cross-sectional view, the MOSFET structure has a split poly gate structure with a single polysilicon layer structure within the RFP trench.

Figure 26 shows a top view of the embodiment of Figure 4(a), where the RFP region is a continuous band in the horizontal direction.

Fig. 27 shows a top view of the embodiment in Fig. 4(a), where the RFP area is divided into several columns in the horizontal direction.

Figure 28 shows a schematic flow diagram of the sample fabrication process.

Detailed ways

The many innovative solutions of the present application will be described herein with particular reference to the presently preferred embodiments (as examples, not limitations). This application describes several embodiments, but the following statements should not generally be taken as limitations on the claims.

For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and descriptions and details of well-known features and techniques are omitted to avoid unnecessarily obscuring the present invention. In addition, components in the drawings are not necessarily drawn to scale, and certain areas or components may be enlarged to facilitate a further understanding of the embodiments of the present invention.

Words such as "first", "second", "third", "fourth" (if any) in the description and claims may be used to identify similar components and need not be used to describe a specific order or chronological order. It will be appreciated that these terms are used interchangeably. Further, "comprising", "including", "having" and any variations of these words are intended to cover a non-exclusive inclusion such that a process, method, article, apparatus or composition comprising a list of components need not be limited to those components, Instead, other components not expressly listed in or inherent in such processes, methods, articles, apparatus or compositions may be included.

We considered and intended that this design be applicable to both n-type and p-type MOSFETs; for clarity, the example is given based on an n-channel MOSFET structure, but those of ordinary skill in the art will know that many modifications can be made to this design to make a similar p-channel device.

The present application discloses improvements to power insulated gate field effect transistors having recessed field plates (RFPs) and similar structures. The inventors have realized that the performance of RFP-type power MOSFETs can be improved by performing compensating implants into the RFP trenches. This compensating implant helps the boundaries of the depletion region in the off state and thus helps avoid punchthrough. Because of this, local enhancement can also be added to the doping between the channel and drain in the drift or extension region. This provides a synergistic combination in which on-resistance can be improved without degrading breakdown voltage.

In one example embodiment, the RFP including the MOSFET has a buried depth compensation region floating in the N body region beneath the trench of the RFP. The deep compensation region lowers the voltage of the dielectric layer between the RFP and the N ^- epi layer when a high drain-source voltage is applied.

In one example embodiment, the RFP comprising MOSFET has a buried deep compensation region floating in the N body region under the trench of the RFP, and doping between the channel and the drain in the drift or extension region in the N epitaxial layer local enhancement.

In one embodiment, the RFP containing the MOSFET also has a deep P+ region within the P body in contact with the RFP trench walls extending from the P body into the N epitaxial layer.

In one embodiment, the deep compensation region beneath the RFP trench extends to and connects to the source electrode.

In one embodiment, the deep compensation region under the RFP trench extends to the P body region in contact with the sidewall of the RFP trench.

In one embodiment, the deep compensation region is a very lightly doped p-region, while in another embodiment, the deep compensation region is a very lightly doped n-region.

Referring now to FIG. 4( a ), the semiconductor device structure 100 includes a gate 102 located in a first trench 104 , which is also referred to as a gate trench 104 herein. The first trench 104 containing the gate 102 may be one of many gate trenches within the semiconductor device structure 100 . The semiconductor device structure 100 is capacitively coupled to control vertical conduction having a first conductivity type, adjacent to the first trench 104 , from the source region 106 through the semiconductor material 108 .

As shown in FIG. 4( a ), the gate 102 has a gate electrode comprising a gate conductive material having a width approximately equal to the width of the gate trench 104 . It will be appreciated that while the gate electrode width may be approximately equal to the width of the gate trench 104, wider gate trenches and smaller gate electrodes may also be used to contact the gate electrodes such that the gate trenches are in contact with the gate electrodes. pole conductor insulation.

The semiconductor device structure 100 also includes a recessed field plate 110 located adjacent to the semiconductor material 108 and capacitively coupled to the material. Recessed field plates 110 are located within respective second trenches 112 , also described herein as RFP trenches 112 . Each trench (ie, each second trench 112 and the gate trench) has trench walls coated with an insulating material such as silicon dioxide (SiO ₂ ). RFP trench 112 comprises an insulating material having a breakdown voltage that preferably exceeds the breakdown voltage of semiconductor device structure 100 . The gate trench 104 preferably contains insulating material up to the p-body-drain junction, minimizing any overlap of the gate electrode (connected to the gate 102 ) with the drain or drift region.

In one embodiment, the gate trenches comprise a thick insulating dielectric material such as silicon dioxide. In another embodiment, the insulating material in the RFP trench and/or the gate trench 104 has a stepped thickness. Providing a stepped thickness can help form the channel and can help control "hot" electron effects.

A conductive material, such as n-type doped polysilicon, forms a gate electrode electrically separated from the gate trench 104 by an insulating material. Conductive materials can be silicided to reduce their electrical resistance. Conductive material is also filled into the RFP trench 112 , electrically separated from the gate trench 104 by an insulating material, and extends above the RFP trench to form a plurality of RFP electrodes. Although the RFP electrode is deeper than the gate electrode and is independently biased or connected to the source electrode (i.e., source 106), and the source region (including the source electrode) may extend between the gate 106 and the RFP trench 112, it may Each trench is substantially equal or different in depth and can self-calibrate by etching on the same process step.

In a specific embodiment, the n-epitaxial drift region is uniformly doped. In another embodiment, the n-epitaxial drift region is not uniformly doped. Specifically, the doping is graded so that the doping concentration is higher at the interface with the substrate of the bottom layer 118 and decreases toward the surface. Inconsistent doping of the drain drift region allows the formation of larger channels and controlled "hot" electron junctions.

The source region can be doped with n+. The gate trenches 104 and RFP trenches may have thin layers of insulating material, which reduce on-resistance, or thick layers of insulating material, which provide greater electrical isolation to increase reverse bias breakdown voltage. In the depicted embodiment, the RFP electrodes have a consistent depth. In another embodiment, at least one of the RFP electrodes extends upward and contacts the source 106 .

Advantageously, the semiconductor device structure 100 further includes a p-type or n-type deep compensation region 114 at least partially under the individual RFP trenches 112 . The deep compensation region 114 can be a p-doped region (as shown in FIG. 4 a ) or a floating island of a lightly doped n-doped region in the N-drift region under the RFP trench. The figure shows the boundaries of the compensation region 114 when it has been fully back-doped, but one of ordinary skill will understand that it is similarly conceivable to use, for example, concentration contours (Concentration Contours) of a single doping species to compensate instead of the back-doping region. boundary.

The deep compensation region 114 also lowers the voltage of the dielectric layer between the RFP and the N-epitaxial layer when a high drain-source voltage is applied.

As shown in FIG. 4( b ), the device 100 also includes a deep p-body region 116 that is in contact with the sidewalls of the RFP trench 112 . Deep p-body region 116 with boundary 116a may be connected to the source electrode and may also be connected to deep compensation region 114 . Deep P-N junctions on edge terminations can be formed by deep compensation implants and their associated anneals without adding new masks. Therefore, the disclosed structures can provide more reliable edge endpoints.

Additionally, as shown in Figure 4(c), the deep compensation region 114 may extend vertically and merge with the p-body region.

The 2D voltage simulation shown in Fig. 5 reveals that under the same bias conditions, the conventional device with the structure shown in Fig. 3 shows about 19 V for the bottom dielectric layer between the RFP and the N-epitaxial layer, while Fig. 4(a ) to 4(c) show that the bottom dielectric layer between the RFP and the N epitaxial layer is only 7V due to the protection of the deep compensation region 114 .

With significantly lower electrical stress on the bottom dielectric layer between the RFP and the drain, the device structure of Figures 4(a) to 4(c) will provide higher reliability and longer operating lifetime. In addition, the deep compensation region 114 enhances the lateral and vertical depletion of the N- epitaxial layer, thus providing room for higher local doping concentrations in the epitaxial layer without reducing the breakdown voltage of the device.

The increase of the local doping concentration in the epitaxial layer further reduces the on-resistance of the drift region. By properly adjusting the doping concentration of the P and N regions in the N-epitaxial layer, the total on-resistance of the device can be reduced without reducing the breakdown voltage. Furthermore, the enhanced local doping of the N layer also reduces the minority carrier injection efficiency of the body diode in the device and changes the electric field distribution during the reverse recovery of the body diode. In this way, the reverse recovery of the body diode is improved, resulting in a device with lower reverse recovery charge and soft recovery characteristics.

Since the doping enhancement occurs only in the active region, the improved termination efficiency in the device edge junction termination region will not decrease.

The recessed field plates 110 may respectively be located in a plurality of trenches 112 separated from the gate trenches 104 . Thus, the semiconductor device structure 100 may be, for example, an n-channel MOSFET having a recessed field plate (RFP) trench 112 and a gate trench 104 formed on an N-type epitaxial layer grown on a heavily doped N+ substrate.

When operating in the third quadrant, where the drain 118 is negatively biased relative to the source body electrode (i.e., the source 106), and where diffusion currents result in minority carrier injection and high reverse recovery charge Qrr, the plurality of RFPs The electrodes form a majority carrier channel current path from drain to source in addition to that provided by the gate electrode in conventional structures. The combined effect of the RFP electrode and the gate electrode is to reduce both the minority carrier diffusion current and the recovery charge Qrr. Therefore, when operating in the third quadrant, the RFP electrode acts as an additional gate without any adverse consequences of adding gate-drain capacitance Cgd.

The RFP also reduces any electric field in the channel region when operated in reverse bias. Thus, the channel length can be shortened without significant risk of punch-through breakdown, further reducing Ron*A and Qg. Capacitive coupling between the gate trench 104, the RFP trench 112 and the drain region further depletes the drain drift region at the higher rate at which the drain-source voltage VDS increases in the off state. The low Cgd and its fast fall rate, combined with the increased drain-source voltage VDS, provides lower gate-drain charge.

The semiconductor device structure 100 can have a quasi-vertical or lateral configuration. Determining that the semiconductor device structure 100 has a quasi-vertical or lateral configuration can facilitate channel formation and can reduce hot electron effects.

Various variations of gate conductors and RFP conductors can be used. Various combinations are shown in US Patent Application No. 2008/0073707A1 filed by Darwish, the entire contents of which are hereby incorporated by reference. Polysilicon can be used as the conductive material. Exemplary variations in gate conductor and RFP conductor structure design include split poly and single poly configurations (FIGS. 21-25), thick bottom oxide, stepped bottom oxide, and combinations of many forms.

Referring to FIG. 26, each of the foregoing embodiments can be implemented in a single configuration, a multi-band configuration, a honeycomb layout configuration, or a combination of the foregoing. Furthermore, the positive and negative polarities and conductivity types can be reversed.

Referring to Figure 27, each of the preceding embodiments RFP can also be implemented in an interrupted manner, where the RFP trenches and conductors form columns in the source-body-drain layer of the device. Using this interruption method, more N++ surface area is provided, N++ resistance is reduced, and overall on-resistance is lowered.

在图7中，施加沟槽掩模207来形成用于沟槽蚀刻的硬掩模，并且蚀刻氧化物层。The fabrication process of the described embodiment is detailed in Figures 6-18. In FIG. 6 , starting with an N++ substrate 201 , the growth of an N− epitaxial layer 203 is followed by the formation of a thin layer of silicon oxide layer 205 . The substrate 201 may be doped with phosphorus or arsenic. A preferred thickness of oxide layer 205 may be, for example

In FIG. 7, a trench mask 207 is applied to form a hard mask for trench etching, and the oxide layer is etched.

Then, a standard silicon etching step is performed to form a plurality of trenches 209 according to the mask. In FIG. 8 , blanket implantation of phosphorous ions 211 (eg, P ³¹ ) across the device may be performed to locally increase the doping concentration of the N- epitaxial layer. Implantation is best performed with a tilt of 0 degrees. A trench mask (not shown in the figure) around the edge termination regions or gate bus regions prevents phosphorus dopants from entering these regions. Thus, only the active area of the device receives a doping-enhancing implant.

After implantation, a high temperature process in an oxygen containing environment is used to anneal and diffuse the phosphorus dopant. As a result, a doping enhanced N layer 213 is formed inside the N- epitaxial layer, as shown in FIG. 9 . The trench walls may then first be oxidized using sacrificial oxidation. After the sacrificial oxide is removed, a pad oxide is regenerated along the trench sidewalls. In FIG. 10 , the trenches are filled with high density oxide 217 . The oxide 217 may include silicon dioxide or other types of deposited oxides, such as LTO or TEOS or high density plasma (HDP, High Density Plasma) oxide. The oxide is then thinned using plasma dry etching or CMP techniques to planarize the oxide surface 219 as shown in FIG. 11 .

In FIG. 12 , after the active mask 223 is applied to open the trench 222 , the oxide is further etched down into the trench to form a bottom oxide layer (BOX, Bottom Oxide Layer) 221 . Then in FIG. 13, a BOX mask is used to protect the active gate trenches 225 and edge termination regions (not shown). Perform an oxide removal step to completely etch away the BOX inside the RFP trench. Before removing the BOX mask, boron-11 ions 229 are implanted into the N/N- epitaxial layer through the bottom 231 of the RFP trench, forming a P layer or insulating region 237 as shown in FIG. 14 .

In one embodiment, to implement the structure shown in Figure 4(c), an oblique angle implant is used to introduce boron along the RFP sidewalls. After removing the BOX photoresist 233, an optional high temperature anneal is used to diffuse boron, forming a P layer or insulating region 237 inside the N- epitaxial region. Gate oxide 235 is then grown along the trench sidewalls in FIG. 14 .

The remaining processing steps shown in Figures 15-17 are similar to those described in Figures 14-17 of US Patent Application No. 2008/0073707, which is hereby incorporated by reference. The final device structure is shown in FIG. 18 . It must be noted that by properly selecting the RFP poly recess depth combined with the implant energy for the P+ implant, the P+ region can be made deeper than the P body, as shown in Figure 19A. Depending on the doping concentration of the P-shielding region (or insulating region), the P-shielding region is a "π" region 260 (very lightly doped P region) shown in FIG. 19C or a "ν" region shown in FIG. 19B 250 (very lightly doped n-region). A deeper P+ region is desired here in order to improve device roughness and to connect the buried P region to the source electrode. In addition, the N++ source region can also be fully recessed, as shown in Figure 20, so that the N++ source photomask step can be eliminated.

Furthermore, the techniques proposed in this invention can also be implemented using split poly-gate device structures. One implementation is schematically illustrated in Figures 21-23. The process includes depositing a first poly layer in the trench, poly etch back and oxide removal, gate oxidation, second poly layer deposition, and CMP and/or poly etch back. Instead of the single poly layer in the active trench gate and RFP trench shown in FIG. 18, a split-gate double-layer poly configuration shown in FIGS. 21-23 is used. In this case, both the bottom poly and the top poly in the trench of the RFP are electrically shorted to the source metal. Additionally, the split poly layer in the RFP region of the device in Figure 23 can be directly replaced by a single RFP poly layer as demonstrated in Figures 24A and 25A. Depending on the doping concentration of the P-shielding region (or insulating region), at very light concentrations, the P-shielding region is a "π" region (very lightly doped p region) or a "ν" region (very lightly doped heterogeneous n region), as shown in Figures 24B, 24C, 25B and 25C.

Figure 28 is a flowchart depicting a fabrication process for fabricating a MOSFET according to one embodiment of the present invention. The fabrication process includes growing 302 an N- epitaxial layer on an N+ substrate. The fabrication process also includes locally increasing the doping concentration in the 304N-epitaxial layer. Locally increasing the doping concentration in the 304N-epitaxial layer includes blanket implanting phosphorus. Blanket implantation of phosphorous can be performed at zero tilt angles, or can be performed at other tilt angles. Locally increasing 304 the doping concentration within the N-epitaxial layer also includes excluding phosphorus dopants from the edge termination region and/or gate bus region, including leaving oxide in the edge termination region or gate bus region.

The fabrication process for making the MOSFET also includes creating a 306 doping-enhanced N layer inside the N-epi layer, including annealing and extending the phosphorus dopant using a high temperature heat treatment in an oxygen environment. The fabrication process for making the MOSFET also includes smoothing 308 the trench surface of the trench and reducing the trench surface roughness caused during the trench silicon etch, including oxidizing the trench sidewalls, removing 310 the sacrificial oxide layer, and along The trench sidewalls are regenerated 312 with pad oxide.

The fabrication process for making MOSFETs also includes filling 314 the trenches with a high density oxide, planarizing 316 the oxide surface, including etching back the oxide, forming a bottom oxide layer (BOX), including further etching down using an active mask The trenches are entered and the active gate trenches and edge terminations are protected 318 using a BOX mask. The manufacturing process of making MOSFET also includes implanting boron (B11) into the 320N- epitaxial layer through the bottom of the recessed field plate trench, including introducing boron along the side wall of the recessed field plate at an oblique angle, and completely etching away the inside of the 322 recessed field plate trench The BOX includes removing the oxide, optionally driving 324 boron forming the P layer into the N- epitaxial layer, including high temperature annealing and growing 324 a gate oxide along the trench sidewalls.

For the sample 40V embodiment, the preferred parameters are as follows. It must be understood, however, that these parameters can be scaled for different operating voltages, and of course adjusted for many other processes. In this sample embodiment, the grooves are 0.3 microns wide, approximately 1.0 microns deep, and are spaced one micron apart (since there are two types of grooves, the protocells are two microns apart). In this sample embodiment, the starting material is a 0.35 ohm-cm n-on-n+ epitaxial layer (epi), approximately 5.5 microns thick. A blanket n-enhanced implant is performed, for example with 3E12/cm ² (ie 3×10 ¹² cm ⁻² ) of phosphorus. The trenches are then etched. After the sacrificial oxidation and trench fill (preferably using the deposited oxide plus oxidation treatment), an etch back is preferably performed to clear the trench to about half the depth. The photoresist is then patterned to expose the RFP trenches but not the gate trenches, and the oxide plug is removed from the RFP trenches. A P-type implant is then performed to form a P-insulating region; in this example a combination of two boron implants, one of 2.5E12/ ^cm2 at 30keV plus the other of 2E12 at 120keV. This will result in a counter-doped or compensated insulating region 114 approximately 0.7 microns deep below the RFP trench. The remaining processing steps then continue in a conventional manner, forming gates, bodies, sources, contacts, and so on.

As noted above, in the various embodiments described above, locally enhanced n-doping connecting the gate to the drain reduces the on-resistance. However, it is this newly added insulating region that contributes to this enhanced n-doping that provides improved off-state behavior.

In alternative embodiments, the depth of the insulating region may be from, for example, 0.25 microns to 2.5 microns, and thus scaled for operating voltages other than 40V. Similarly, in alternative embodiments, insulation implants may use doses from 2E12 cm ⁻² to 1E13 at 20-320 keV, or even higher or lower doses and/or energies, plus allowable scaling.

It should be readily understood that the foregoing are descriptions of some particularly illustrated and exemplary embodiments of the present invention, and should not be considered a description of all embodiments within the scope of the present invention.

According to various embodiments, there is provided: a semiconductor device structure comprising a gate within a first trench and capacitively coupled to control vertical flow from a source of a first conductivity type through semiconductor material adjacent to said trench. a conductive; a recessed field plate located adjacent to and capacitively coupled to said semiconductor material; said recessed field plate located within each second trench; and a second conductive conductor located at least partially beneath said each second trench. type of diffusion.

According to various embodiments, there is provided: a semiconductor device structure comprising a semiconductor layer; a gate located in a first trench in said semiconductor layer and capacitively coupled to control a channel from a source of a first conductivity type through said trench vertical conduction of portions of the layer of the second conductivity type adjacent to the trenches; a recessed field plate located adjacent to and capacitively coupled to the semiconductor material; said recessed field plate located within each second trench; at least partially A diffusion component of the second conductivity type underlying said respective second trench; whereby said diffusion component reduces depletion of said second conductivity type portion of said layer in the off state.

According to various embodiments, there is provided: a semiconductor device structure comprising a semiconductor layer; a gate located in a first trench in said semiconductor layer and capacitively coupled to control a channel from a source of a first conductivity type through said trench vertical conduction of portions of the layer of the second conductivity type adjacent to the trenches; a recessed field plate located adjacent to and capacitively coupled to the semiconductor material; said recessed field plate located within each second trench; at least partially located a first additional diffusion member of a second conductivity type underlying each of said second trenches; and a second additional diffusion member of said first conductivity type at least partially within said second conductivity type portion of said layer; Thereby said first additional diffusion component reduces depletion of said second conductivity type portion of said layer in the off state; and thereby said second additional diffusion component reduces the contact of the device in the on state on-resistance.

According to various embodiments, there is provided: an improved RFP transistor structure having (a) low overall on-resistance, (b) reduced minority carrier injection efficiency (of the body diode), (c) improved (body diode) Diode's) reverse recovery, (c) reduced reverse recovery charge, (d) soft recovery characteristics, (e) as a reliable edge termination, neither reducing the breakdown voltage nor the termination efficiency in the device edge junction termination region , the improved structure comprises: an RFP transistor structure comprising at least one or more gate trenches adjacent to one or more recessed field plate trenches; district.

According to various embodiments, there is provided a method of operating a semiconductor device structure, comprising: controlling the position of a channel between first and second source/drain electrodes through a semiconductor material using a gate electrode located in a first trench conduction to provide at least on and off states; and use of one or more recessed field plates located near and capacitively coupled to the semiconductor material to avoid punching through the channel site; the recessed field plates located at Within each second trench, and at least partially beneath each second trench, is one or more diffusion elements of the second conductivity type; thereby said diffusion elements reduce depletion spread in the off state.

According to various embodiments, there is provided: a fabrication process for fabricating a MOSFET comprising the following sequence of actions: a) providing an n-type semiconductor layer; b) forming a p-type body within said layer; c) forming a p-type body within said layer an n-type source insulated from said body; d) forming an isolated gate trench within said layer; and forming a gate electrode within said gate trench; said gate electrode being capacitively coupled to said body at least a portion; e) forming a second insulating trench within said layer, providing an additional dose of acceptor dopant beneath said trench, and forming a recessed field plate electrode within said second trench; and f) Providing an additional dose of donor dopant atoms within said portion of said body, thereby reducing the on-resistance.

According to various embodiments, there are provided: improved high reliability power RFP structures and fabrication and operation processes. The structure includes a plurality of regions of localized dopant concentration beneath the RFP trench, which float or extend and meet the body layer of the MOSFET, or connect to the source layer through vertically doped regions. The locally doped region reduces the minority carrier injection efficiency of the body diode in the device and changes the electric field distribution during reverse recovery of the body diode.

Modifications and Variations

Those skilled in the art will appreciate that the innovative concepts described in this application are capable of modification and variation over a wide range of applications, and thus the scope of patented subject matter is not limited to any particular example approach presented. The intention is to embrace all such substitutions, modifications and changes that fall within the spirit and broad scope of the appended claims.

The device can be fabricated in a variety of layouts, including "straight" and "honeycomb" layouts. The layers of the source, body and drain regions can be arranged vertically, semi-vertically and horizontally. The epitaxial drift region can be uniformly or non-uniformly doped. While the above-described embodiments include an epitaxial layer grown on a substrate, the epitaxial layer may be omitted in certain applications. Many features of different embodiments can be combined and recombined for various applications.

For example, the region between the channel and drain need not be uniformly doped, nor vertically or laterally doped. The improvements in drift or extended region doping provided by the present invention can be combined with a wide variety of other device improvements and features.

As another example, the RFP and gate trenches do not have to be the same width.

This design is suitable for IGBTs or other devices involving bipolar conduction. The bottom of the gate trench can be modified with dopants; the design can also be changed on the source structure and the drain structure and alternative body structures can be used; contact trenches can be created first and then gate trenches can be cut And construct the source and drain structures.

Of course, the n-type dopant in silicon can be phosphorous, antimony or arsenic or a combination of these materials. Appropriate donor dopants can be used in other semiconductor materials.

As the disclosed process scales to other operating voltages, we expect the predicted scaling of dimensions and dopants to follow the same synergies, e.g., in the 200V embodiment, the inventors expect the trench depth to be slightly deeper (e.g., 1.5 to 2.5 microns ), and the compensation implant energy and dose will be about the same. Of course the epitaxial (epi) layer will be substantially less doped and the epitaxial (epi) layer thicker, as will be understood by those of ordinary skill. The n-enhanced doping (preferably blocked from the communication with the terminal) may have a distribution, after drive-in, to the upper boundary of the compensation implant, but preferably not to the lower boundary of the compensation implant.

The following applications contain additional information and alternative amendments: Attorney Docket No. MXP-14P, Serial No. 61/125,892, filed 04/29/2008; Attorney Docket No. MXP-15P, Serial No. 61/058,069, filed 6/2/2008 and titled " Edge Termination for Devices Containing Permanent Charge"; Attorney Docket No. MXP-16P, Serial No. 61/060,488, filed on 6/11/2008 and titled "MOSFET Switch"; Attorney Docket No. MXP-17P, Serial No. 61/074,162, 6/20 /2008 proposed and titled "MOSFET Switch"; Attorney Docket No. MXP-18P, Serial No. 61/076,767, proposed on 6/30/2008 and titled "Trench-Gate Power Device"; Attorney Docket No. MXP-19P, Serial No. 61/ 080,702, filed 7/15/2008 and titled "A MOSFET Switch"; Attorney Docket No. MXP-20P, Serial No. 61/084,639, filed 7/30/2008 and titled "Lateral Devices Containing Permanent Charge"; Attorney Docket No. MXP -21P, serial number 61/084,642, filed on 7/30/2008 and titled "Silicon on Insulator Devices Containing Permanent Charge"; attorney case file number MXP-22P, serial number 61/027,699, filed on 2/11/2008 and titled "Use of Permanent Charge in Trench Sidewalls to Fabricate Un-Gated Current Sources, Gate Current Sources, and Schottky Diodes"; Attorney Docket No. MXP-23P, Serial No. 61/028,790, filed 2/14/2008 and titled "Trench MOSFET Structure and Fabrication Technique that Uses Implantation Through the Trench Sidewall to Form the Active Body Region and the Source Region”; Attorney Docket No. MXP-24P, Serial No. 61/028,783, Filed 2/14/2008 and Titled “Te chniques for Introducing and Adjusting the Dopant Distribution in a Trench MOSFET to Obtain Improved Device Characteristics"; Attorney's Case File No. MXP-25P, Serial No. 61/091,442, filed on 8/25/2008 and titled "Devices Containing Permanent No. Charge"; Lawyer's Case MXP-27P, Serial No. 61/118,664, filed 12/1/2008 and titled "An Improved Power MOSFET and Its Edge Termination" and Attorney Docket No. MXP-28P, Serial No. 61/122,794, filed 12/16/2008 and titled "A Power MOSFET Transistor".

The description in the present application should not be read as implying that any particular component, step, or function is essential to inclusion in the claims: the scope of patented subject matter is defined only by the allowed claims. Further, these claims have no intent to invoke the sixth paragraph of 35 United States Code (USC) § 112 unless there is the exact wording "means for" plus the participle.

It is the intent of the filed claims to be as comprehensive as possible, with no subject matter to be withdrawn, monopolized or disclaimed.

Claims (33)

1. semiconductor device structure comprises:

Grid, it is positioned at first groove, and capacitive coupling is controlled from the vertical conduction by the semi-conducting material adjacent with described groove of the source electrode of first conduction type;

Recessed field plate, it is positioned near the described semi-conducting material and is capacitively coupled to this material; Described recessed field plate is positioned at each second groove; And

Be positioned at the diffusion of second conduction type under described each second trench bottom to small part.

2. semiconductor device structure as claimed in claim 1, wherein said device also comprise the concentration of dopant zone of one deck second conduction type, its from source layer extend to described diffusion at least one of them.

3. semiconductor device structure as claimed in claim 1, one of them vertical extension at least of wherein said diffusion, and converge with the body layer of second conduction type.

4. semiconductor device structure as claimed in claim 1, wherein said device also comprises the concentration of dopant zone of one deck second conduction type, its from source layer extend to described diffusion at least one of them, and one of them vertical extension at least of described diffusion, and converge with the body layer of second conduction type.

5. semiconductor device structure as claimed in claim 1, wherein this grid cording has division polycrystalline configuration.

6. semiconductor device structure as claimed in claim 1, wherein these recessed field plates one of them has division polycrystalline configuration at least.

7. semiconductor device structure as claimed in claim 1, wherein this grid and these recessed field plates one of them has division polycrystalline configuration at least.

8. semiconductor device structure as claimed in claim 1, wherein said first conduction type is the n type.

9. semiconductor device structure as claimed in claim 1, wherein said grid capacitance are coupled and control vertical conduction to the drain diffusion of described first conduction type.

10. semiconductor device structure comprises:

Semiconductor layer;

Grid, it is positioned at first groove of described semiconductor layer, and capacitive coupling is controlled from the vertical conduction by near second conduction type part of the described layer described groove of the source electrode of one first conduction type;

Recessed field plate, it is positioned near the described semi-conducting material and is capacitively coupled to this material; Described recessed field plate is positioned at each second groove;

Be positioned at the diffusion component of second conduction type under described each second trench bottom to small part;

Exhausting of described second conduction type part of described thus diffusion component minimizing described layer under dissengaged positions.

11. as the semiconductor device structure of claim 10, wherein said grid has division polycrystalline configuration.

12. as the semiconductor device structure of claim 10, wherein said recessed field plate one of them has division polycrystalline configuration at least.

13. as the semiconductor device structure of claim 10, wherein this grid and these recessed field plates one of them has division polycrystalline configuration at least.。

14. as the semiconductor device structure of claim 10, wherein said diffusion component concentration height must be enough to the described semiconductor layer of local contra-doping and produce second conductivity type regions that is lower than this second groove thus.

15. as the semiconductor device structure of claim 10, wherein said semiconductor layer is an epitaxial loayer.

16. a semiconductor device structure comprises:

Semiconductor layer;

Grid, it is positioned at first groove of described semiconductor layer, and capacitive coupling is controlled from the vertical conduction by near second conduction type part of the described layer described groove of the source electrode of first conduction type;

Recessed field plate, it is positioned near the described semi-conducting material and is capacitively coupled to this material; Described recessed field plate is positioned at each second groove;

Be positioned at the first extra diffusion component of second conduction type under described each second trench bottom to small part; And

Be positioned at the second extra diffusion component of described second conduction type described first conduction type partly of described layer to small part;

Exhausting of described second conduction type part of the described thus first extra diffusion component minimizing described layer under dissengaged positions;

And this connection resistance of the described thus second extra diffusion component minimizing this device under on-state.

17. as the semiconductor device structure of claim 16, wherein said grid has division polycrystalline configuration.

18. as the semiconductor device structure of claim 16, wherein said recessed field plate one of them has division polycrystalline configuration at least.

19. as the semiconductor device structure of claim 16, wherein this grid and these recessed field plates one of them has division polycrystalline configuration at least.

20. as the semiconductor device structure of claim 16, wherein said diffusion component concentration height must be enough to the described semiconductor layer of local contra-doping, produces second conductivity type regions that is lower than described second groove thus.

21. as the semiconductor device structure of claim 16, wherein said semiconductor layer is an epitaxial loayer.

22. Improvement type RFP transistor arrangement, it has (a) low total connection resistance, (b) (body diode) minority carrier injection efficiency of Jiang Diing, (c) Gai Liang (body diode) oppositely recovered, (c) QRR of Jian Shaoing, (d) soft recovery characteristics is (e) as reliable edge termination, neither reduce the end use efficiency that puncture voltage does not reduce joint terminal area, device edge again, the structure of this improvement comprises:

The RFP transistor arrangement comprises at least one or more gate trench adjacent with one or more recessed field plate groove; And

Be positioned at each the dark compensating basin under the described recessed field plate trench bottom.

23., wherein be positioned under this recessed field plate zone this and be embedded into insulation layer and floating as the Improvement type RFP transistor arrangement of claim 16.

24., wherein be positioned under this recessed field plate zone this and be embedded into insulation layer and be connected to this source electrode by dark P zone as the Improvement type RFP transistor arrangement of claim 16.

25., wherein be positioned under this recessed field plate zone this and be embedded into insulation layer and vertically extend and converge with this P body regions as the Improvement type RFP transistor arrangement of claim 16.

26. a method of operating semiconductor device structure comprises:

Use is positioned at the gate electrode of first groove, controls the conduction of passing through the raceway groove position in the semi-conducting material between first and second source/drain electrode, connects at least and dissengaged positions to provide; And

Use is positioned near the described semi-conducting material and is capacitively coupled to one or more recessed field plate of this material, avoids the described raceway groove of break-through position; Described recessed field plate is positioned at each second groove, and

One or more diffusion component to the small part of second conduction type is positioned under described each second trench bottom;

Described thus diffusion component reduces the expansion that exhausts under this dissengaged positions.

27. as the method for claim 26, wherein said device also comprises the concentration of dopant zone of one deck second conduction type, it extends at least one position of described diffusion component from source layer.

28. as the method for claim 26, wherein this grid has division polycrystalline configuration.

29. as the method for claim 26, wherein these recessed field plates one of them has division polycrystalline configuration at least.

30. as the method for claim 26, wherein this grid and these recessed field plates one of them has division polycrystalline configuration at least.

31. as the method for claim 26, wherein said first conduction type is the n type.

32. as the method for claim 26, wherein said grid capacitance is coupled and controls vertical conduction to the drain diffusion of described first conduction type.

33. a manufacturing process that is used to make MOSFET comprises the following action of order:

A) provide n type semiconductor layer;

B) in described layer, form p type body;

C) form n type source electrode in described layer, it is insulated by described body;

D) in described layer, form the insulated gate electrode groove, and in described gate trench, form gate electrode; Described gate electrode is capacitively coupled at least a portion of described body;

E) in described layer, form second insulated trench, the acceptor doped thing of extra dose is provided under described groove, and in described second groove, form the recessed field plate electrode; And

What f) provide extra dose in the described part of described body executes the body atoms of dopant, reduces this connection resistance thus.

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