CN111200014A

CN111200014A - Junction field effect transistor and method of making the same

Info

Publication number: CN111200014A
Application number: CN201811372629.3A
Authority: CN
Inventors: 雷天飞; 毛焜
Original assignee: Shanghai Bright Power Semiconductor Co Ltd
Current assignee: Shanghai Bright Power Semiconductor Co Ltd
Priority date: 2018-11-19
Filing date: 2018-11-19
Publication date: 2020-05-26

Abstract

The invention provides a junction field effect transistor and a manufacturing method thereof. The junction field effect transistor comprises: a substrate; a first conductivity type drift region; a first conductivity type source region; Surrounding the source region of the first conductivity type, the channel region of the junction field effect transistor includes a defined region surrounded by the gate region of the second conductivity type; and the drain region of the first conductivity type is spaced apart from the gate region of the second conductivity type. The channel opening and closing of the channel region of the present invention is realized by laterally depleting the channel region of the P-type gate region. Therefore, by adjusting the spacing between the P-type gate regions, the width of the channel region can be changed, thereby changing the pinch-off voltage. The invention can integrate a plurality of junction field effect transistors with different pinch-off voltages into the same circuit, can meet different circuit performance requirements, and effectively save the manufacturing cost.

Description

Junction field effect transistor and manufacturing method thereof

Technical Field

The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a junction field effect transistor and a manufacturing method thereof.

Background

With the continuous development of semiconductor technology, for example, computers and peripheral digital products are increasingly updated. In the application integrated circuit of computer and peripheral digital products, due to the rapid development of semiconductor process, the power supply of the integrated circuit is required to be more diversified, and voltage regulators with various combinations, such as voltage boosters, voltage reducers, etc., are used to realize different power supply requirements of various integrated circuits, and are also one of the important factors for providing various digital products.

Among various voltage regulation circuits, Junction Field Effect Transistors (JFETs) have become an excellent choice for a preceding-stage voltage regulator because of their extremely convenient voltage regulation performance. The junction field effect transistor has a larger gate current than the metal-oxide layer-semiconductor field effect transistor, but a smaller gate current than the bipolar transistor. Meanwhile, the transconductance of the junction field effect transistor is higher than that of the metal-oxide-semiconductor field effect transistor, so that the junction field effect transistor is used in some low-noise and high-input-impedance operational amplifiers.

The Junction Field Effect Transistor (JFET) adopts a PN junction as a grid of a device to control the opening and the closing of a channel, when negative bias of the PN junction is applied to the grid, two sides of the PN junction are exhausted, and when the channel is completely exhausted, the device is in a channel pinch-off state, and the device is closed. On the other hand, when no voltage is applied to the gate or a voltage for forward biasing the PN junction is applied to the gate, the depletion region is narrowed, the channel region is widened, and the device is in an on state.

High voltage Junction Field Effect Transistors (JFETs) need to withstand high voltages and therefore the drift region (distance between drain and gate) is long. Taking an N-channel high-voltage Junction Field Effect Transistor (JFET) as an example, applying negative voltage to the gate or positive voltage to the source can completely deplete the N-channel region, thereby pinching off the channel and allowing the device to enter the cut-off region. The depletion of the N channel of a Junction Field Effect Transistor (JFET) consists of two parts, a surface P-type gate region and a substrate P-type region.

The channel of the traditional Junction Field Effect Transistor (JFET) is longitudinally clamped, and the structure has the defect that the clamping voltage of the channel is only non-adjustable. If Junction Field Effect Transistors (JFETs) with different pinch-off voltages are integrated in the same circuit, the process needs to be adjusted, the number of layers of a photomask is increased, and the like, so that the production cost is increased.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a Junction Field Effect Transistor (JFET) and a method for manufacturing the same, which are used to solve the problem of single pinch-off voltage caused by longitudinal pinch-off of the channel of the JFET in the prior art.

To achieve the above and other related objects, the present invention provides a junction field effect transistor comprising: a substrate; a first conductive type drift region formed in the substrate; a first conductive type source region formed in the first conductive type drift region; a second conductive type gate region formed in the first conductive type drift region, the second conductive type gate region surrounding the first conductive type source region in a surrounding structure, and a channel region of the junction field effect transistor including a defined region surrounded by the second conductive type gate region; and a first conductive type drain region formed in the first conductive type drift region and spaced apart from the second conductive type gate region.

Optionally, the channel opening and closing of the channel region of the junction field effect transistor is realized by laterally depleting a defined region surrounded by the second conductivity type gate region through the second conductivity type gate region.

Optionally, the pinch-off voltage of the junction field effect transistor is adjusted by adjusting the lateral dimension of a defined region surrounded by the second conductivity type gate region, wherein the pinch-off voltage increases with the increase of the lateral dimension of the defined region and decreases with the decrease of the lateral dimension of the defined region.

Optionally, the lateral dimension ranges from 1 micron to 3 microns.

Optionally, the surrounding structure of the second conductive type gate region includes one of a closed ring structure, an interrupted ring structure and a two-sided clamping structure.

Optionally, the second conductive type gate region includes a plurality of second conductive type doping regions from top to bottom, and the ion doping concentration of the plurality of second conductive type doping regions is gradually reduced.

Optionally, the second conductive type gate region includes a doped contact region, a first doped region and a second doped region from top to bottom, the first doped region wraps the doped contact region, and an ion doping concentration of the doped contact region is between 1e19cm^-3～2e20cm^-3The ion doping concentration of the first doping region is between 5e17cm^-3～5e18cm^-3The ion doping concentration of the second doping region is between 5e17cm^-3～5e18cm^-3In the meantime.

Optionally, the ion doping concentration of the first conductive type source region is between 1e19cm^-3～2e20cm^-3The ion doping concentration of the first conduction type drain region is between 1e19cm^-3～2e20cm^-3The ion doping concentration of the drift region of the first conductivity type is between 5e16cm^-3～5e17cm^-3In the meantime.

Optionally, the first conductivity type drift region includes one of a deep well and an epitaxial layer.

Optionally, the junction field effect transistor further comprises a field oxide layer formed in the first conductivity type drift region, and located between the second conductivity type gate region and the drain region, the field oxide layer comprises one of a local field oxide layer and a shallow trench field oxide layer.

Optionally, the jfet is an N-type device, the first conductivity type is an N-type, and the second conductivity type is a P-type.

Optionally, the junction field effect transistor is a P-type device, the first conductivity type is a P-type, and the second conductivity type is an N-type.

The present invention also provides a semiconductor device including: the junction field effect transistor and the lateral diffusion metal oxide field effect transistor share the first conductive type drift region and the first conductive type drain region, the lateral diffusion metal oxide field effect transistor further comprises an LDMOS source region and an LDMOS gate of the first conductive type, the LDMOS source region is formed in the second conductive type gate region and is isolated from the first conductive type drift region by the second conductive type gate region, and the LDMOS gate covers between the LDMOS source region and the first conductive type drift region.

Optionally, the LDMOS source region of the first conductivity type and the drain region of the first conductivity type are formed in the first conductivity type drift region.

The invention also provides a manufacturing method of the junction field effect transistor, which comprises the following steps: 1) providing a substrate, and forming a first conductive type drift region on the substrate; 2) forming a second conductive type gate region in the first conductive type drift region; and 3) forming a first conductive type source region and a first conductive type drain region in the first conductive type drift region, wherein the second conductive type gate region surrounds the first conductive type source region in a surrounding structure, a channel region of the junction field effect transistor comprises a limited region surrounded by the second conductive type gate region, and the first conductive type drain region is separated from the second conductive type gate region.

Optionally, the step 2) adjusts a pinch-off voltage of the junction field effect transistor by adjusting a lateral dimension of a defined region surrounded by the second conductivity type gate region, wherein the pinch-off voltage increases with an increase in the lateral dimension of the defined region and decreases with a decrease in the lateral dimension of the defined region.

Optionally, the lateral dimension ranges from 1 micron to 3 microns.

Optionally, in step 2), the surrounding structure of the second conductive type gate region includes one of a closed ring structure, an interrupted ring structure, and a two-sided clamping structure.

Optionally, step 1) comprises: and forming the first conductive type drift region on the substrate by adopting a deep well process, or forming the first conductive type drift region on the substrate by adopting an epitaxial process.

Optionally, in the step 2), a plurality of second conductivity type doped regions from top to bottom are formed in the first conductivity type drift region by using an ion implantation process to serve as the first conductivity type gate region, and ion doping concentrations of the plurality of second conductivity type doped regions are gradually reduced.

Optionally, step 1) still include in form field oxide in the first conductivity type drift region, field oxide is located the second conductivity type gate region with between the drain region, field oxide includes one kind in local field oxide and the shallow trench field oxide.

Optionally, the junction field effect transistor is an N-type device, the second conductivity type is a P-type, and the first conductivity type is an N-type.

Optionally, the junction field effect transistor is a P-type device, the second conductivity type is an N-type, and the first conductivity type is a P-type.

As described above, the junction field effect transistor and the method for manufacturing the same according to the present invention have the following advantageous effects:

the P-type gate region with the surrounding structure is arranged on the peripheral side of the channel region, so that the channel region is changed from the traditional longitudinal pinch-off into the transverse pinch-off, and the channel opening and closing of the channel region are realized by transversely depleting the channel region through the P-type gate region. Therefore, by adjusting the spacing between the P-type gate regions, the width of the channel region can be changed, and thus the pinch-off voltage can be changed.

The invention can integrate a plurality of junction field effect transistors with different pinch-off voltages in the same circuit without adding a photomask or ion implantation, can meet different circuit performance requirements, and effectively saves the manufacturing cost.

Drawings

Fig. 1 is a schematic structural diagram of a junction field effect transistor according to embodiment 1 of the present invention.

Fig. 2 to 4 are schematic top views of several jfets with different P-type gates according to embodiment 1 of the present invention.

Fig. 5 is a schematic view showing the direction of current flow when the jfet of embodiment 1 of the invention is turned on.

Fig. 6 is a schematic diagram illustrating that when the jfet of embodiment 1 of the invention is turned off, the P-type gate region and the channel region are reversely biased, thereby widening the depletion region therebetween.

Fig. 7 is a graph showing the relationship between the channel width and the pinch-off voltage of the jfet in embodiment 1 of the invention.

Fig. 8 to 11 are schematic structural views showing steps of a method for manufacturing a junction field effect transistor according to embodiment 1 of the present invention.

Fig. 12 is a schematic structural view of a junction field effect transistor according to embodiment 2 of the present invention.

Fig. 13 is a schematic structural diagram of a semiconductor device integrating a junction field effect transistor and a ldmos transistor in embodiment 3 of the invention.

Description of the element reference numerals

101P type substrate

102N type drift region

103 field oxide layer

104 second doped region

105 first doped region

106 channel region

107 doped contact region

108N type source region

109N type drain region

110 depletion region

111 LDMOS source region

112 LDMOS gate

113 a field-reducing layer of a second conductivity type

201N type substrate

202P type drift region

203 field oxide layer

204 second doped region

205 first doped region

206 channel region

207 doped contact region

208P type source region

209P type drain region

211N type buried layer

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 13. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Example 1

As shown in fig. 1, the present embodiment provides a junction field effect transistor, which includes a substrate, a first conductivity type drift region, a first conductivity type source region, a second conductivity type gate region, and a first conductivity type drain region. In this embodiment, the device of this example is described by taking the junction field effect transistor as an N-type device as an example, that is, in this embodiment, the first conductivity type is an N-type, and the second conductivity type is a P-type. The corresponding junction field effect transistor includes a P-type substrate 101, an N-type drift region 102, an N-type source region 108, a P-type gate region, and an N-type drain region 109.

As shown in fig. 1, the substrate may be a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, a germanium substrate, or a silicon carbide substrate, the substrate is a P-type substrate 101, and the P-type ion doping concentration may be 5e17cm^-3～5e18cm^-3In the meantime.

As shown in fig. 1, the N-type drift region 102 is formed in the substrate, for example, optionally, the N-type drift region 102 includes one of a deep well and an epitaxial layer. The ion doping concentration of the N-type drift region 102 may be 5e16cm^-3～5e17cm^-3In the meantime.

As shown in fig. 1, the N-type source region 108 is formed in the N-type drift region 102, and the ion doping concentration of the N-type source region 108 may be 1e19cm^-3～2e20cm^-3In the meantime.

As shown in fig. 1, the P-type gate region is formed in the N-type drift region 102, the P-type gate region surrounds the N-type source region 108 in a surrounding structure, the channel region 106 of the junction field effect transistor includes a defined region surrounded by the P-type gate region, and the channel opening and closing of the channel region 106 of the junction field effect transistor is realized by laterally depleting the defined region surrounded by the P-type gate region through the P-type gate region. In the present invention, when a negative voltage is applied to the P-type gate region (or a positive voltage is applied to the N-type source region 108), the P-type gate region and the N-type channel region 106 are reversely biased, so that the depletion region 110 therebetween is widened, and when the depletion regions 110 on the left and right sides of the channel region 106 coincide, the channel of the device is pinched off, and the device is turned off.

Based on the above, the present embodiment can adjust the pinch-off voltage of the junction field effect transistor by adjusting the lateral dimension of the defined region surrounded by the P-type gate region, wherein the pinch-off voltage increases with the increase of the lateral dimension of the defined region and decreases with the decrease of the lateral dimension of the defined region. For example, the lateral dimension may range from 1 micron to 3 microns.

As shown in fig. 2 to 4, the surrounding structure of the P-type gate region includes one of a closed ring structure, an interrupted ring structure and a two-sided clamping structure. For example, when the surrounding structure of the P-type gate region is a closed ring structure, as shown in fig. 2, the channel region 106 of the device can be more effectively defined, and the pinch-off voltage of the device is greatly reduced while ensuring the effective width of the channel. When the surrounding structure of the P-type gate region is an interrupted ring structure, as shown in fig. 3, the on-resistance of the device can be effectively reduced while the device has a lower pinch-off voltage, and when the surrounding structure of the P-type gate region is a two-side clamping structure, as shown in fig. 4, the channel region 106 of the device can be effectively defined, the structure is simpler, and the process difficulty and the process cost are effectively reduced. Of course, the shapes of the closed loop structure and the discontinuous loop structure may be circular, elliptical, polygonal, etc., and are not limited to the examples listed herein.

As shown in FIG. 1, the P-type gate region comprises a plurality of P-type doped regions from top to bottom, and ions of the P-type doped regionsThe doping concentration is gradually reduced. In the present embodiment, the P-type gate region includes a doped contact region 107, a first doped region 105 and a second doped region 104 from top to bottom, the first doped region 105 wraps the doped contact region 107, and the ion doping concentration of the doped contact region 107 is between 1e19cm^-3～2e20cm^-3The ion doping concentration of the first doping region 105 is between 5e17cm^-3～5e18cm^-3The ion doping concentration of the second doping region 104 is between 5e17cm^-3～5e18cm^-3In the meantime. The ion doping concentration of the P-type doping regions is gradually reduced, so that the withstand voltage of the device can be improved, the pinch-off voltage of a channel is lower when the device is closed, and the on-resistance of the device is lower when the device is switched on.

As shown in fig. 1, the N-type drain region 109 is formed in the N-type drift region 102 and is spaced apart from the P-type gate region, and the ion doping concentration of the N-type drain region 109 may be between 1e19cm^-3～2e20cm^-3In the meantime.

As shown in fig. 1, the junction field effect transistor further includes a field oxide layer 103 formed in the N-type drift region 102, and located between the P-type gate region and the drain region, the field oxide layer 103 includes one of a local field oxide layer 103 and a shallow trench field oxide layer 103.

When the jfet of this embodiment is operating, the channel of the jfet is turned on when the source and the gate are grounded and the drain is connected to a high voltage, the device operates normally, and the current when the device is turned on is as shown by the scissor in fig. 5. Under normal operating conditions, when a negative voltage is applied to the gate (or a positive voltage is applied to the source), the P-type gate region and the N-type region of the channel region 106 are reversely biased, so that the depletion region 110 therebetween is widened, as shown in fig. 6, when the depletion regions 110 on the left and right sides of the channel region 106 coincide, the channel is pinched off, and the device is turned off.

Fig. 7 is a graph showing the relationship between the channel width (i.e., the lateral dimension of the defined region surrounded by the P-type gate region) and the pinch-off voltage of the jfet of the present embodiment, as can be seen from fig. 7, the pinch-off voltage of the jfet can be adjusted by setting the channel width, for example, the pinch-off voltage is approximately-3V, -5V, -7.5V, -11V, -15V, and-22V when the channel width is respectively 1 micron, 1.2 microns, 1.4 microns, 1.8 microns, and 2 microns, thereby fitting the relationship between the pinch-off voltage y and the channel width x, wherein the formula shown in fig. 7 is the relationship between the pinch-off voltage y and the channel width x fitted in the present embodiment.

As shown in fig. 8 to 11, this embodiment further provides a method for manufacturing a junction field effect transistor, where the method includes the following steps:

as shown in fig. 8 to 9, step 1) is first performed to provide a substrate, for example, a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, a germanium substrate, or a silicon carbide substrate, wherein the substrate is P-type doped and the doping concentration of P-type ions may be 5e17cm^-3～5e18cm^-3Then, an N-type drift region 102 is formed on the substrate, for example, the N-type drift region 102 may be formed on the substrate by a deep well process, or the N-type drift region 102 may be formed on the substrate by an epitaxial process.

As shown in fig. 9, then in form field oxide layer 103 in N type drift region 102, field oxide layer 103 is formed in N type drift region 102, field oxide layer 103 is located P type gate region with between the drain region, field oxide layer 103 includes one of local field oxide layer 103 and shallow trench field oxide layer 103.

As shown in fig. 10, step 2) is then performed to form a P-type gate region in the N-type drift region 102.

For example, an ion implantation process may be used to form a plurality of P-type doped regions from top to bottom in the N-type drift region 102 as the N-type gate region, and the ion doping concentration of the plurality of P-type doped regions is gradually decreased. In the present embodiment, the P-type gate region includes a doped contact region 107, a first doped region 105 and a second doped region 104 from top to bottom, the first doped region 105 wraps the doped contact region 107, and the ion doping concentration of the doped contact region 107 is between 1e19cm^-3～2e20cm^-3Ion doping concentration of the first doping region 105Degree between 5e17cm^-3～5e18cm^-3The ion doping concentration of the second doping region 104 is between 5e17cm^-3～5e18cm^-3In the meantime. The ion doping concentration of the P-type doping regions is gradually reduced, so that the pinch-off voltage of a channel is lower when the device is closed, and the on-resistance of the device is lower when the device is switched on.

As shown in fig. 11, step 3) is finally performed to form an N-type source region 108 and an N-type drain region 109 in the N-type drift region 102, the P-type gate region surrounds the N-type source region 108 in a surrounding structure, the channel region 106 of the junction field effect transistor includes a defined region surrounded by the P-type gate region, and the N-type drain region 109 is spaced apart from the P-type gate region. For example, the ion doping concentration of the N-type source region 108 may be between 1e19cm^-3～2e20cm^-3The ion doping concentration of the N-type drain region 109 may be between 1e19cm^-3～2e20cm^-3In the meantime.

The P-type gate region surrounds the N-type source region 108 in a surrounding structure, the channel region 106 of the junction field effect transistor includes a defined region surrounded by the P-type gate region, and the channel of the channel region 106 of the junction field effect transistor is opened and closed by performing lateral depletion on the defined region surrounded by the P-type gate region through the P-type gate region. In the present invention, when a negative voltage is applied to the P-type gate region (or a positive voltage is applied to the N-type source region 108), the P-type gate region and the N-type channel region 106 are reversely biased, so that the depletion region 110 therebetween is widened, and when the depletion regions 110 on the left and right sides of the channel region 106 coincide, the channel of the device is pinched off, and the device is turned off.

Example 2

As shown in fig. 12, the present embodiment provides a junction field effect transistor, whose basic structure is as in embodiment 1, wherein the difference from embodiment 1 is that the junction field effect transistor is a P-type device, the first conductivity type is a P-type, the second conductivity type is an N-type, the junction field effect transistor includes an N-type substrate 201, a P-type drift region 202, a field oxide layer 203, an N-type gate region (an N-type first doped region 205, an N-type second doped region 204, an N-type doped contact region 207), a channel region 206, a P-type source region 208, and a P-type drain region 209, and an N-type buried layer 211 is further disposed between the substrate and the drift region.

As shown in fig. 12, this embodiment further provides a junction field effect transistor, which has the basic steps as in embodiment 1, wherein the difference from embodiment 1 is that the junction field effect transistor is a P-type device, the second conductivity type is an N-type, the first conductivity type is a P-type, and before the drift region is formed, the method further includes a step of forming an N-type buried layer 211 on the substrate.

Example 3

As shown in fig. 13, the present embodiment provides a semiconductor device integrating a Junction Field Effect Transistor (JFET) and a laterally diffused metal oxide semiconductor transistor (LDMOS), and the present embodiment takes the first conductivity type as an N-type and the second conductivity type as a P-type as an example, but in other embodiments, the first conductivity type may be configured as a P-type and the second conductivity type may be configured as an N-type.

In this embodiment, the semiconductor device includes: the junction field effect transistor according to embodiment 1, and a lateral diffusion metal oxide field effect transistor, wherein the lateral diffusion metal oxide field effect transistor and the junction field effect transistor share the first conductive type drift region and the first conductive type drain region, the lateral diffusion metal oxide field effect transistor further includes a first conductive type LDMOS source region 111 and an LDMOS gate 112, the LDMOS source region 111 is formed in the second conductive type gate region and is isolated from the first conductive type drift region by the second conductive type gate region, and the LDMOS gate 112 covers between the LDMOS source region and the first conductive type drift region.

The LDMOS source region 111 of the first conductivity type and the drain region of the first conductivity type are connected to each other by a second conductivity type field reducing layer 113, and the second conductivity type field reducing layer 113 is formed in the drift region of the first conductivity type between the LDMOS source region 111 of the first conductivity type and the drain region of the first conductivity type. The second conductive type field-reducing layer 113 can effectively improve the surface electric field of the first conductive type drift region, and improve the voltage endurance capability of the semiconductor device.

In the embodiment, the Junction Field Effect Transistor (JFET) and the laterally diffused metal oxide semiconductor transistor (LDMOS) are integrated, so that the integrated device has high breakdown voltage characteristic while obtaining good pinch-off performance, and the application range of the device is greatly expanded.

Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A junction field effect transistor, wherein the junction field effect transistor comprises:

substrate;

a first conductivity type drift region formed in the substrate;

a first conductive type source region formed in the first conductive type drift region;

A second conductive type gate region is formed in the first conductive type drift region, the second conductive type gate region surrounds the first conductive type source region in a surrounding structure, and the junction field effect transistor a channel region comprising a defined area surrounded by the gate region of the second conductivity type; and

A first conductive type drain region is formed in the first conductive type drift region and is spaced apart from the second conductive type gate region.

2 . The junction field effect transistor according to claim 1 , wherein a channel of the channel region of the junction field effect transistor is turned on and off through the second conductivity type gate region to the second conductivity type gate region. 3 . The lateral depletion implementation is performed in a limited area surrounded by the conductive type gate region.

3 . The junction field effect transistor according to claim 1 , wherein: the pinch-off voltage of the junction field effect transistor is adjusted by adjusting the lateral size of the defined region surrounded by the gate region of the second conductivity type, Wherein, the pinch-off voltage increases as the lateral dimension of the defined area increases, and decreases as the lateral dimension of the defined area decreases.

4 . The junction field effect transistor of claim 3 , wherein the lateral dimension ranges from 1 μm to 3 μm. 5 .

5 . The junction field effect transistor according to claim 1 , wherein the surrounding structure of the gate region of the second conductivity type comprises one of a closed ring structure, a discontinuous ring structure and a two-sided clamping structure. 6 . .

6 . The junction field effect transistor of claim 1 , wherein the gate region of the second conductivity type comprises a plurality of doping regions of the second conductivity type from top to bottom, and the plurality of doped regions of the second conductivity type The ion doping concentration of the impurity region gradually decreases.

7 . The junction field effect transistor of claim 6 , wherein the gate region of the second conductivity type comprises a top-down doped contact region, a first doped region and a second doped region, 8 . The first doping region covers the doping contact region, the ion doping concentration of the doping contact region is between 1e19cm ⁻³ and 2e20cm ⁻³ , and the ion doping concentration of the first doping region is between 1e19cm −3 and 2e20cm −3 The concentration is between 5e17cm ^-3 and 5e18cm ^-3 , and the ion doping concentration of the second doping region is between 5e17cm ^-3 and 5e18cm ^-3 .

8 . The junction field effect transistor according to claim 1 , wherein the ion doping concentration of the source region of the first conductivity type is between 1e19 cm ⁻³ and 2e20 cm ⁻³ . The ion doping concentration of the drain region is between 1e19cm ⁻³ and 2e20cm ⁻³ , and the ion doping concentration of the first conductivity type drift region is between 5e16cm ⁻³ and 5e17cm ⁻³ .

9 . The junction field effect transistor of claim 1 , wherein the first conductivity type drift region comprises one of a deep well and an epitaxial layer. 10 .

10 . The junction field effect transistor according to claim 1 , wherein the junction field effect transistor further comprises a field oxide layer formed in the drift region of the first conductivity type and located in the second conductivity type drift region. 11 . Between the conductive type gate region and the drain region, the field oxide layer includes one of a local field oxide layer and a shallow trench field oxide layer.

11. The junction field effect transistor according to claim 1, wherein the junction field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type .

12. The junction field effect transistor according to claim 1, wherein the junction field effect transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type .

13. A semiconductor device, characterized in that, comprising:

The junction field effect transistor according to any one of claims 1 to 12; and

a laterally diffused metal oxide field effect transistor, the laterally diffused metal oxide field effect transistor and the junction field effect transistor share the first conductivity type drift region and the first conductivity type drain region, the lateral diffusion The metal oxide field effect transistor also includes a first conductivity type LDMOS source region and an LDMOS gate, the LDMOS source region is formed in the second conductivity type gate region, and is connected by the second conductivity type gate region and the LDMOS gate region. The first conductive type drift region is isolated, and the LDMOS gate covers between the LDMOS source region and the first conductive type drift region.

14 . The semiconductor device of claim 13 , wherein the laterally diffused metal oxide field effect transistor further comprises a second conductivity type drop field layer formed between the first conductivity type LDMOS source region and all the LDMOS source regions. 15 . in the drift region of the first conductivity type between the drain regions of the first conductivity type.

15. A method for fabricating a junction field effect transistor, comprising:

1) providing a substrate on which a drift region of the first conductivity type is formed;

2) forming a gate region of a second conductivity type in the drift region of the first conductivity type; and

3) forming a first conductivity type source region and a first conductivity type drain region in the first conductivity type drift region, the second conductivity type gate region surrounding the first conductivity type source region in a surrounding structure, The channel region of the junction field effect transistor includes a defined region surrounded by the second conductivity type gate region, and the first conductivity type drain region is spaced apart from the second conductivity type gate region.

16 . The method for fabricating a junction field effect transistor according to claim 15 , wherein the channel opening and closing of the channel region of the junction field effect transistor is controlled by the gate region of the second conductivity type. 17 . A lateral depletion implementation is performed in a limited area surrounded by the gate region of the second conductivity type.

17 . The method for fabricating a junction field effect transistor according to claim 15 , wherein step 2) adjusts the junction field effect by adjusting the lateral size of the limited area surrounded by the gate region of the second conductivity type. 18 . The pinch-off voltage of a transistor, wherein the pinch-off voltage increases as the lateral dimension of the defined region increases and decreases as the lateral dimension of the defined region decreases.

18 . The method for fabricating a junction field effect transistor according to claim 17 , wherein the lateral dimension ranges from 1 μm to 3 μm. 19 .

19 . The method for fabricating a junction field effect transistor according to claim 15 , wherein in step 2), the surrounding structure of the gate region of the second conductivity type comprises a closed ring structure, a discontinuous ring structure and two One of the side clamping structures.

20 . The method for manufacturing a junction field effect transistor according to claim 15 , wherein step 1) comprises: forming the drift region of the first conductivity type on the substrate using a deep well process, or using an epitaxial process. 21 . The first conductivity type drift region is formed on the substrate.

21 . The method for fabricating a junction field effect transistor according to claim 15 , wherein in step 2), an ion implantation process is used to form a plurality of second conductivity types from top to bottom in the drift region of the first conductivity type. 22 . The conductivity type doped region, as the first conductivity type gate region, the ion doping concentration of the plurality of second conductivity type doped regions gradually decreases.

22 . The method for fabricating a junction field effect transistor according to claim 21 , wherein the gate region of the second conductivity type comprises a top-down doped contact region, a first doped region and a second doped region. 23 . impurity region, the first doping region covers the doping contact region, the ion doping concentration of the doping contact region is between 1e19cm ⁻³ and 2e20cm ⁻³ , and the first doping region has The ion doping concentration is between 5e17cm ^-3 and 5e18cm ^-3 , and the ion doping concentration in the second doping region is between 5e17cm ^-3 and 5e18cm ^-3 .

23 . The method for fabricating a junction field effect transistor according to claim 15 , wherein the ion doping concentration of the first conductive type source region is between 1e19 cm −3 and 2e20 cm −3 , and the first conductivity type source region has a ion doping concentration between 1e19 cm ⁻³ and 2e20 cm ⁻³ . The ion doping concentration of the drain region of a conductivity type is between 1e19cm ^-3 and 2e20cm ^-3 , and the ion doping concentration of the first conductivity type drift region is between 5e16cm ^-3 and 5e17cm ^-3 .

24. The method for fabricating a junction field effect transistor according to claim 15, wherein step 1) further comprises forming a field oxide layer in the first conductivity type drift region, the field oxide layer being located in the first conductivity type drift region. Between the gate region of the second conductivity type and the drain region, the field oxide layer includes one of a local field oxide layer and a shallow trench field oxide layer.

25. The method for manufacturing a junction field effect transistor according to claim 15, wherein the junction field effect transistor is an N-type device, the second conductivity type is P-type, and the first conductivity type for the N type.

26. The method for fabricating a junction field effect transistor according to claim 15, wherein the junction field effect transistor is a P-type device, the second conductivity type is N-type, and the first conductivity type for the P type.