CN111164767A

CN111164767A - A semiconductor light-emitting element and light-emitting device

Info

Publication number: CN111164767A
Application number: CN201980004732.9A
Authority: CN
Inventors: 张东炎; 吴俊毅; 刘�文; 王晶; 郭桓邵; 李慧文; 王笃祥
Original assignee: Tianjin Sanan Optoelectronics Co Ltd
Current assignee: Tianjin Sanan Optoelectronics Co Ltd
Priority date: 2019-05-17
Filing date: 2019-05-17
Publication date: 2020-05-15
Anticipated expiration: 2039-05-17
Also published as: TWI728595B; TW202044620A; WO2020232586A1; CN111164767B

Abstract

A semiconductor light emitting element comprising: a semiconductor light emitting sequence including a first conductive type semiconductor layer, a light emitting layer, and a second conductive type semiconductor layer; the electric insulation layer covers a partial area on one side of the second conduction type semiconductor layer to form an electric insulation area, a partial area which is not covered on one side of the second conduction type semiconductor layer is an electric contact area, and the second conduction type semiconductor layer comprises a fluorine-containing area. The electric insulating layer is fluoride, fluorine ions of the fluoride enter the second conduction type semiconductor layer through high-temperature diffusion to form a fluorine-containing region, the fluorine-containing region is at least formed in the second conduction type semiconductor layer below the main pad electrode of the first electrode, the local square resistance can be improved, the current dispersion condition in the second conduction type semiconductor layer below the main pad electrode of the first electrode is improved, the current is promoted to transversely diffuse to the peripheral region of the main pad electrode far away from the first electrode, and therefore the light uniform dispersion is improved.

Description

Semiconductor light-emitting element and light-emitting device

Technical Field

The present invention relates to an LED light emitting element.

Background

At present, the LED light emitting device is widely used in a plurality of fields such as illumination, display, traffic signal, data storage, and medical equipment. The influence factors of the luminous efficiency of the LED light emitting element are many, including the heat dissipation of the substrate, the light extraction efficiency on the light extraction side, and the like, in addition to the internal quantum efficiency of the epitaxial structure.

In order to improve the heat dissipation of the substrate, on the one hand, the epitaxial growth substrate can be replaced to be a substrate with higher heat conduction, because the thermal conductivity of the silicon or silicon carbide or metal substrate is higher than that of gallium arsenide, and the current commercialized method is to use a bonding process to realize the substrate transfer to the silicon or silicon carbide or metal substrate. However, after the substrate is transferred, the N-type epitaxial layer is turned upwards, and a contact layer and an electrode layer need to be designed on the N-type GaAs epitaxial layer, which causes a problem of shading the electrode.

On the other hand, in order to improve the light extraction efficiency, a metal reflective layer may be provided. The improvement of the reflection effect is more pronounced in that a metallic reflective layer is used in combination with an electrically insulating layer of low refractive index. At present, the refractive index of a semiconductor sequence is about 2.5-3.0, a transparent electric insulating layer lower than the refractive index of the semiconductor sequence is usually arranged between a metal reflecting layer and the semiconductor sequence, light rays radiated from the semiconductor sequence can be subjected to large-angle total reflection at the interface of the electric insulating layer with the low refractive index and the semiconductor sequence and return to the semiconductor sequence, and light rays with small angles can continuously pass through the electric insulating layer to the metal reflecting layer to be reflected and return to the semiconductor sequence and emit light from the light emitting side of the semiconductor sequence. Therefore, the transparency and the refractive index value of the insulating layer are the main factors affecting the reflection effect. Preferably, the refractive index of the currently used electrically insulating layer is usually lower than 2.0, and at least one of silicon nitride, silicon oxide, magnesium fluoride, calcium fluoride, and the like is mainly used. Among them, fluorides such as calcium fluoride and magnesium fluoride have a lower refractive index, lower than 1.5, and have high light transmittance, so that the use of such fluorides can more significantly improve the light extraction efficiency.

Disclosure of Invention

In accordance with an object of the present invention, there is provided a semiconductor light emitting element including:

a semiconductor light emitting sequence including a first conductive type semiconductor layer, a light emitting layer, and a second conductive type semiconductor layer;

the electrically insulating layer covers a partial region on the second conductivity type semiconductor layer side to form an electrically insulating region, a partial region on the second conductivity type semiconductor layer side not covered is an electrical contact region,

the method is characterized in that: the second conductive type semiconductor layer includes a fluorine-containing region therein.

Preferably, the fluorine-containing region is located at an interface between the second conductive type semiconductor layer and the insulating layer, and extends into the second conductive type semiconductor layer.

Preferably, the electrically insulating layer is a fluoride.

Preferably, the fluorine-containing region is formed by diffusing fluorine in the electrical insulating layer.

Preferably, the thickness of the fluorine-containing region in the second conductive type semiconductor layer is 1 to 1000nm, and more preferably, the thickness of the fluorine-containing region is 10 to 100 nm.

Preferably, the fluorine-containing region has a fluorine-containing element concentration of 1E 17-1E 21/cm³。

Preferably, the second conductive type semiconductor layer includes a current spreading layer, and the fluorine-containing region is located at an interface between the current spreading layer and the electrically insulating layer and extends into the current spreading layer of the second conductive type semiconductor layer.

Preferably, the current spreading layer is GaP or GaAs or AlGaInP.

Preferably, the thickness of the fluorine-containing region is not higher than the thickness of the current spreading layer.

Preferably, the thickness of the fluorine-containing region is higher than that of the current spreading layer.

Preferably, the fluorine-containing region is a homogenous region with the laterally surrounding region.

Preferably, one side of the first conductivity type semiconductor layer is provided with a first electrode, the first electrode comprises a main pad electrode for external wire bonding, and the fluorine-containing region is at least positioned in the second conductivity type semiconductor layer in the vertical direction of the main pad electrode.

Preferably, one side of the first conductivity type semiconductor layer is provided with a first electrode, the first electrode comprises a main pad electrode for external wire bonding, and the fluorine-containing region is mainly located in the second conductivity type semiconductor layer in the vertical direction of the main pad electrode.

Preferably, the first conductive type semiconductor layer, the light emitting layer and the second conductive type semiconductor layer are made of AlxInyGa1-x-yP (0 ≦ x ≦ 1,0 ≦ y ≦ 1) and/or AlzGa1-zAs (0 ≦ z ≦ 1) respectively.

Preferably, the electrically insulating layer has a second electrode on a side thereof remote from the second conductivity type semiconductor layer.

Preferably, the electrically insulating layer has a plurality of openings through its thickness, within which are electrical contact areas.

Preferably, the second electrode is in electrical contact with one side of the second conductive type semiconductor layer through an ohmic contact layer, and the ohmic contact layer is made of a transparent conductive layer and covers at least an electrical contact area.

Preferably, the second electrode is in electrical contact with one side of the second conductive type semiconductor layer through an ohmic contact layer, which is a combination of at least two metals.

Preferably, a metal reflective layer is included between the second electrode and one side of the second conductive type semiconductor layer.

20. A semiconductor light emitting element according to claim 16, wherein: the side wall of the opening of the electric insulating layer is inclined relative to a side surface far away from the semiconductor light emitting sequence, and the inclined angle is larger than 90 degrees and smaller than or equal to 170 degrees.

The invention also provides a preparation method of the semiconductor light-emitting element, which comprises the following steps:

obtaining a semiconductor light emitting sequence comprising a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer;

forming an electric insulating layer which is partially covered on the surface side of the second conductive type semiconductor layer, wherein the electric insulating layer is fluoride;

high-temperature diffusion treatment, wherein fluorine is diffused into the second conductive type semiconductor layer to form a fluorine-containing region;

and manufacturing a first electrode which is electrically connected with the first conductive type semiconductor layer, and manufacturing a second electrode which is electrically connected with the second conductive type semiconductor layer.

Preferably, the temperature of the high-temperature diffusion treatment is 360-600 ℃, and the time is 0.01-60 min.

Preferably, after the high-temperature diffusion process, an ohmic contact is formed on the side of the second conductive type semiconductor layer not covered with the electrical insulating layer.

Preferably, the ohmic contact is a transparent conductive layer or a block formed by combining a plurality of metals.

Preferably, the first electrode is located on one side of the first conductive type semiconductor layer and comprises a main pad electrode for external wire bonding, and the high-temperature diffusion treatment enables the fluorine-containing region to be mainly formed in the second conductive type semiconductor layer of the first electrode in the vertical direction of the main pad electrode for external wire bonding.

Preferably, before the high temperature diffusion process, a material of an ohmic contact, which is a combination of at least two metals, is grown on the side of the second conductivity type semiconductor layer that is not covered with the electrical insulation layer.

Preferably, the step of forming the ohmic contact between the material of the ohmic contact and the second conductive type semiconductor layer is the same as the high temperature diffusion process.

Preferably, the second electrode comprises a metal reflective layer.

ohmic contact blocks are formed at a plurality of places on one side of the second conductive type semiconductor layer,

forming a partially covered electrical insulation layer on the surface side of the second conductivity type semiconductor layer, wherein the electrical insulation layer is a metal fluoride salt;

high-temperature diffusion treatment, wherein fluorine elements of the metal fluoride salt are diffused into the second conduction type semiconductor layer to form a fluorine-containing region;

and manufacturing a first electrode to be electrically connected with the first conductive type semiconductor layer, and manufacturing a second electrode to be connected with the second conductive type semiconductor layer.

Preferably, the step of fusing the ohmic contact pad and the second conductive type semiconductor layer at a high temperature is the same as the step of performing a high temperature diffusion process on the electrically insulating layer.

Preferably, the high temperature fusion step of the ohmic contact block to the side of the second conductive type semiconductor layer is earlier than the high temperature diffusion treatment step of the electrical insulating layer.

A light-emitting device obtained by the semiconductor light-emitting element according to the present invention is a package, or a lighting device or a display device.

The invention has the beneficial effects that:

(1) the fluorine-containing region is at least formed in the second conductive type semiconductor layer vertically below the main pad electrode of the first electrode, so that the local square resistance of the region is improved, the current dispersion condition in the second conductive type semiconductor layer below the main pad electrode of the first electrode is improved, the current is promoted to transversely diffuse to the peripheral region of the main pad electrode far away from the first electrode, the light emission below the first electrode can be reduced, the light shielding of the first electrode on the light emission is reduced, and the uniform light dispersion is improved.

(2) The fluorine-containing region is directly from the electric insulating layer and can be formed by high-temperature diffusion treatment, and the process is simple and has high feasibility.

(3) The fluorine-containing region is located at least vertically below the main pad electrode of the first electrode, and may be formed only in the current diffusion layer included in the second conductivity type semiconductor layer, effectively blocking current in the current spreading layer.

(4) The fluorine-containing region may be formed only vertically below or in the vicinity of the main pad electrode of the first electrode. Thereby avoiding concentration of current under the main pad electrode of the first electrode, promoting lateral diffusion of current to the peripheral region of the main pad electrode of the first electrode, and avoiding excessive rise in voltage.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a conventional semiconductor light emitting device.

Fig. 2 is a schematic structural view of a first electrode of a conventional semiconductor light emitting element.

Fig. 3 to 6 are schematic structural views of the semiconductor light emitting element according to the first embodiment.

Fig. 7 is a SIMS elemental analysis diagram of the semiconductor light emitting element according to the first embodiment.

Fig. 8 to 11 are schematic structural views of the semiconductor light emitting element of the first embodiment.

Fig. 12 is a flowchart illustrating steps of a method for fabricating a light emitting device according to a first embodiment.

Fig. 13 to 20 are schematic structural views of a semiconductor light emitting element of the second embodiment.

Fig. 21 is a flowchart of steps of a method for manufacturing a light-emitting element according to a second embodiment.

Fig. 22 to 26 are schematic structural views of a semiconductor light-emitting element of a third embodiment.

Fig. 27 is a flowchart of steps of a method of manufacturing a light-emitting element according to a third embodiment.

Detailed Description

The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.

Example one

As shown in fig. 1, a conventional semiconductor light emitting element as described in the background art includes:

a semiconductor light emitting sequence including a first conductive type semiconductor layer 10, a light emitting layer 9, and a second conductive type semiconductor layer 8;

a side partial region of the second conductivity type semiconductor layer 8 is covered with the electrical insulating layer 7 to form an electrical contact region, and a side partial region not covered with the electrical insulating layer 7 is an electrical contact region. The electrically insulating layer is typically silicon oxide or silicon nitride or calcium fluoride or magnesium fluoride. A plurality of openings are typically formed in the electrically insulating layer, with electrical contact areas within the openings.

The first electrode 11, which includes a main pad electrode (generally circular or oval) for external wire bonding and an extended electrode bar, is disposed on one side of the first conductivity type semiconductor layer 10, as shown in fig. 2.

In the electrical contact area there is usually arranged an ohmic contact layer 6 or an ohmic contact pad and the second electrode 1 is arranged on the side of the electrically insulating layer 7 and on the same side of the ohmic contact layer 6 or ohmic contact pad. Lines marked with arrows in fig. 1 indicate transmission paths of electric currents, external electric currents flow from the second electrode 1, through the ohmic contact region on one side of the second conductivity type semiconductor, into the semiconductor light emitting sequence, to the main pad electrode of the first electrode 11, and out.

Since the main pad electrode of the first electrode 11 is a current concentration region, in order to block current from vertically flowing through the semiconductor light emitting sequence to the second electrode 1 side below the main pad electrode of the first electrode, there is no opening design on the electrical insulation layer vertically below the main pad electrode of the first electrode, i.e. an electrical insulation blocking region is formed below the main pad electrode of the first electrode.

According to this conventional design, although the electrically insulating layer 7 is provided under the main pad electrode of the first electrode as a barrier, it still occurs that the current is partially concentrated under the main pad electrode of the first electrode on the current spreading layer side, resulting in a more significant concentration of the light emitting region under or around the main pad electrode.

Therefore, the present invention provides a semiconductor light emitting device, which can further improve current uniformity and dispersion compared to the conventional design, specifically as shown in fig. 3, comprising:

a partial region on the second conductivity type semiconductor layer 8 side is covered with the electrical insulating layer 7 to form an electrical insulating region, and an uncovered partial region is an electrical contact region. Specifically, the electrical insulating layer 7 is a fluoride, and the electrical insulating layer 7 partially covers one side of the second conductivity type semiconductor layer 8 through a plurality of openings.

The second conductivity type semiconductor layer 8 includes a fluorine-containing region 802 therein. The fluorine-containing region is formed by diffusing fluoride into the second conductivity type semiconductor layer 8 at a high temperature, and through tests, the fluorine-containing region can improve the local sheet resistance of the second conductivity type semiconductor layer 8 to form a high-resistance region.

The first electrode 11, including the main pad electrode for external wire bonding, is disposed on one side of the first conductive type semiconductor layer 10, and the fluorine-containing region 802 is at least located in the second conductive type semiconductor layer 8 vertically below the main pad electrode of the first electrode.

As the approximate current path indicated by the line marked with an arrow shown in fig. 3, since the fluorine-containing region 802 increases the local sheet resistance, the current flowing into the second conductivity type semiconductor layer 8 under the main pad electrode of the first electrode is further blocked, thereby preventing the current from concentrating under the main pad electrode of the first electrode, promoting the lateral diffusion of the current to the peripheral region of the main pad electrode of the first electrode, facilitating the uniform distribution of the current, and thus improving the uniform dispersion of light.

The following describes in detail the light emitting device provided in this embodiment, as shown in fig. 4, which includes a substrate 2; a conductive bonding layer 3 formed on the substrate; the metal reflecting layer 5 is positioned on the conductive bonding layer 3, the metal reflecting layer 5 is positioned on the barrier layer 4, and the electric insulating layer is positioned on the metal reflecting layer 5; a semiconductor sequence located on the electrically insulating layer, a first electrode 11 located on the semiconductor sequence; and a back metal layer 1 located under the substrate. The semiconductor layer sequence has a first conductivity-type semiconductor layer 10, a light-emitting layer 9 and a second conductivity-type semiconductor layer 8.

Wherein the first conductivity type is n-type or p-type, and the second conductivity type is p-type or n-type, wherein the first conductivity type is different from the second conductivity type.

As an optional implementation manner, in this embodiment, the first conductivity type is an n-type, and the second conductivity type is a p-type.

A light-emitting layer 9 which is formed of a semiconductor sequence in which a first conductivity type semiconductor layer 10 includes at least an n-type clad layer, a second conductivity type semiconductor layer 8 different from the first conductivity type semiconductor layer includes at least a p-type clad layer 81, and an active layer interposed between the p-type clad layer and the n-type clad layer and emitting light of a predetermined wavelength; the light-emitting layer, the n-type cladding layer and the p-type cladding layer are each formed of a III-V compound semiconductor. Specifically, the compound semiconductor can be formed by using a compound semiconductor such as GaAs, GaP, or InP, a ternary compound semiconductor such as InGaAs, AlInP, or AlGaAs, or a quaternary compound semiconductor such as AlGaInP. For example, the light-emitting layer 10 (which is formed of an undoped AlGaInP, AlInP, or AlGaAs compound semiconductor body) is sandwiched between an n-type cladding layer and a p-type cladding layer (which are formed by including p-type AlGaInP, AlInP, or AlGaAs, respectively), and a region whose emission wavelength is controlled by the composition of the light-emitting layer may be interposed between visible light such as red, yellow, and green light and invisible light such as infrared light.

Preferably, the semiconductor sequence further includes a current spreading layer 82, such as a p-GaP layer or p-GaAs layer, on the surface side of the second conductive semiconductor layer. The doping concentration is at least 8E17 or more, and the doping material can be Mg, Zn or C.

The substrate 2 may be used to support the semiconductor layer light emitting sequence and other layers or structures thereon, and the material thereof is a conductive material. Conductive materials include, but are not limited to, metals, metal alloys, silicon carbide, graphite, and the like.

The conductive bonding layer 3 is a gold-gold bonding layer, a gold-tin bonding layer or a gold-indium bonding layer and the like used in the conventional bonding process.

The metal reflective layer 5 may reflect light from the semiconductor sequence, and the material thereof may be a metal material including, but not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), or an alloy thereof. A barrier layer 4 may also be included between the reflective layer and the substrate, on the lower surface of the reflective layer. The barrier layer 4 can prevent the material of the reflective layer from diffusing to the electrode layer, damage the structure of the reflective layer, and prevent the reflectivity of the reflective layer from being reduced. In this embodiment, the reflective layer is selected from silver, and the thickness is 250 to 750 nm.

The electrical insulation layer 7 covers a partial region of one side of the second conductivity type semiconductor layer 8, forming an electrical insulation region.

The electrical insulating layer 7 is made of a material with a low refractive index, preferably 1.2-1.5, and such a material is specifically a fluoride, such as magnesium fluoride (MgF2) or calcium fluoride (GaF 2). It can be obtained by electron beam evaporation or high temperature evaporation methods. Wherein, different evaporation techniques, such as evaporation temperature, can obtain slightly different refractive indexes. The fluoride generally has a lower refractive index than an oxide or nitride, such as silicon oxide or silicon nitride, and the proportion of total reflection formed at the interface between the semiconductor sequence and the electrically insulating layer increases as light emitted by the semiconductor light-emitting sequence is directed toward the light-transmissive electrically insulating layer. The light which does not form total reflection at the interface between the semiconductor sequence and the electric insulating layer passes through the electric insulating layer to reach the metal reflecting layer 5 side, and is reflected back to the semiconductor sequence on the metal reflecting layer 5, and is emitted from the light emitting side of the semiconductor sequence or the side wall, so that the light emitting efficiency of the light emitting element is improved. The thickness of the electrically insulating layer is 0.1 to 500nm, more preferably 10 to 100 nm.

In order to form an electrical contact region and an electrical insulation region on the second conductivity type semiconductor layer 8 side, the electrical insulation layer 7 includes a plurality of through-holes penetrating in the thickness direction, the plurality of through-holes being independently, uniformly or non-uniformly distributed on the electrical insulation layer 7; the region on the side of the second conductivity type semiconductor layer exposed by the opening of the through-hole is an electrical contact region, and the region covered with the electrical insulating layer 7 is an electrical insulating region. Preferably, the opening of the through-hole on the side of the semiconductor sequence is smaller than or equal to the opening on the opposite side from the side of the semiconductor sequence. More preferably, the through-hole has an opening dimension on the side of the semiconductor sequence smaller than the opening dimension on the opposite side from the side of the semiconductor sequence, and in particular, as shown in fig. 3, the through-hole has a first opening dimension D1 on the side of the semiconductor sequence and a second opening dimension D2 on the opposite side from the side of the semiconductor sequence, the first opening dimension D1 and the second opening dimension D2 defining the diameter or width of the opening in longitudinal section, respectively. The first opening dimension D1 is smaller than the second opening dimension D2, and the first opening dimension D1 is 1-20 μm. Therefore, the side walls of the through holes of the electric insulating layer 7 are vertical or the side walls are relatively inclined planes or relatively inclined curved surfaces, and the included angle between the surface of the electric insulating layer 7 adjacent to the metal reflecting layer 5 and the surface of the side wall of the through hole is more than 90 degrees, more preferably more than 90 degrees and less than or equal to 170 degrees.

The ohmic contact layer 6 may be a transparent conductive layer such as a well-known inorganic metal oxide, ITO or IZO, etc., having a thickness of 0.0001 μm to 0.6 μm, 0.0001 μm to 0.5 μm, 0.0001 μm to 0.4 μm, 0.0001 μm to 0.3 μm, 0.0001 μm to 0.2 μm, 0.2 μm to 0.5 μm, 0.3 μm to 0.5 μm, 0.4 μm to 0.5 μm, 0.2 μm to 0.4 μm, or 0.2 μm to 0.3 μm.

As shown in fig. 4, the side walls of the hole of the electrically insulating layer 7 and the front surface close to the reflective layer are covered by a transparent conductive layer, which may act as an adhesion layer ensuring adhesion between the metallic reflective layer and the electrically insulating layer.

The first electrode 11 is formed on the semiconductor sequence in contact with and electrically connected to the first conductive type semiconductor layer 10, and the first electrode 11 includes a main pad electrode for external wire bonding and an extension electrode 1103 extending from the main pad electrode. The main pad electrode for external routing adopts multilayer metals, wherein the main pad electrode at least comprises an ohmic contact layer 1101 which forms ohmic contact with the first conduction type semiconductor layer 10 and is formed by at least one of gold germanium, gold beryllium, gold germanium nickel, gold zinc and the like, and a routing layer 1102 which is externally routed and provides metal fusion, the routing layer 1102 is formed by at least one of gold, aluminum, copper and the like, and the extension electrode is preferably formed by combining gold germanium nickel, gold germanium and the like. Other layers, such as a diffusion barrier layer, may be included between routing layer 1102 and ohmic contact layer 1101 to prevent elements in the ohmic contact layer from diffusing into the routing layer.

The back metal layer 1 of the substrate 2 may define a second electrode for external electrical connection, the first and second electrodes providing different electrode polarities forming current input and output terminals, respectively.

According to this embodiment, the hole of the electrically insulating layer 7 is not located vertically below the main pad electrode for external bonding.

According to the present embodiment. The electrically insulating layer 7 covers not only the region on the side of the second conductivity type semiconductor layer vertically below the main pad electrode of the first electrode but also other positions on the side of the second conductivity type semiconductor layer to provide electrical contact regions where openings are formed at a plurality of places, so that the fluorine-containing region 821 is formed not only vertically below the main pad electrode of the first electrode but also at the interface of the entire electrically insulating layer 7 and the second conductivity type semiconductor layer 8 and extends from the interface to a certain thickness in the second conductivity type semiconductor layer 8. Specifically, the fluorine element of the electrical insulation layer 7 diffuses into the second conductivity-type semiconductor layer 8 to form the fluorine-containing region 821. The fluorine-containing region 821 may have the electrical insulation layer 7 formed in the second conductive type semiconductor layer 9 through a high temperature treatment process. The temperature of the high-temperature treatment process is above 300 ℃, preferably 360-600 ℃, for 0.01-60 min, preferably above 420 ℃, preferably 460-500 ℃, for 1-30 min.

Through the above treatment, fluorine can be diffused into the second conductive type semiconductor layer, which results in an increase in the sheet resistance of the material of the second conductive type semiconductor layer, and a high-resistance region of a certain thickness is formed from the interface covered by the electrical insulating layer 7 and extends deep into the second conductive type semiconductor layer, which can block the lateral and longitudinal diffusion of current, especially, a blocking effect is formed vertically below the main pad electrode of the first electrode, which can improve the effect of blocking the current from diffusing to the lower side of the main pad electrode of the first electrode, promote the current from diffusing to the opening of the electrical insulating layer, and improve the uniform light dispersibility.

According to the present embodiment, the fluorine-containing region 821 formed from the side of the electrical insulation layer 7 is located at least in the current spreading layer 82 of the second conductivity type semiconductor layer 8. It is of course not excluded that the fluorine element may diffuse into other layers belonging to the second conductivity type semiconductor layer 8, such as to the transition layer algan or further to the p-type cladding layer. It is preferred that the fluorine containing region 821 has a thickness not exceeding that of the current spreading layer 82 or that the fluorine containing region 821 has a thickness less than that of the current spreading layer 82. Preferably, the current spreading layer is p-GaP. Wherein the thickness of the current spreading layer p-GaP is 5nm to 2 μm. The fluorine concentration in the fluorine-containing region is not less than 1E17/cm³More preferably, the fluorine concentration of the fluorine-containing region is 1E 17-1E 21/cm³。

The following provides a manufacturing method for obtaining the light emitting element of the present embodiment, as shown in fig. 5 to 11, which are schematic structural diagrams corresponding to the respective steps. Which comprises the following steps:

1. a semiconductor light emitting sequence is obtained on a growth substrate, including a first conductivity type semiconductor layer, a light emitting layer, and a second conductivity type semiconductor layer.

As shown in fig. 5, a semiconductor light emitting sequence is obtained on a growth substrate 101 by MOCVD epitaxial growth, the growth substrate 101 is gallium arsenide in this embodiment, and the substrate is not limited to gallium arsenide, and may be other substrates capable of performing growth of a semiconductor light emitting sequence. The semiconductor sequence on the gallium arsenide substrate includes a first conductivity type semiconductor layer 10, a light emitting layer 9, and a second conductivity type semiconductor layer 8 which are sequentially grown and stacked. The first conductive type semiconductor layer 10 includes an n-type clad layer, the second conductive type semiconductor layer includes a p-type clad layer, the n-type clad layer and the p-type clad layer may be specifically an al-in-p, and the light emitting layer is an al-ga-in-p. Optionally, a buffer layer, an excess layer, an etch stop layer, etc. may be further included between the growth substrate and the semiconductor sequence for the purpose of subsequently facilitating the removal of the growth substrate or ensuring the quality of the epitaxial growth. More preferably, the first conductive type semiconductor layer may further include n-type gallium arsenide as an ohmic contact layer for ohmic contact of the subsequent first electrode. More preferably, the second conductivity type semiconductor layer 8 includes a p-type current spreading layer 82, and the current spreading layer 82 is p-type gallium phosphide in the present embodiment due to current spreading and ohmic contact on the second conductivity type semiconductor layer side.

The functions and parameters for each layer can be referred to in the following table.

2. An electrically insulating layer is deposited and an opening is formed in the fluoride electrically insulating layer.

An electrical insulating layer is evaporated on the side of the second conductivity type semiconductor layer 8, and the electrical insulating layer 7 is preferably magnesium fluoride or calcium fluoride. The thickness of the electrically insulating layer 7 is in the range of 10 to 500 nm. The temperature of the evaporation is at least 20 ℃ or preferably 200 ℃. The higher the temperature, the higher the density of the evaporated fluoride.

The electrically insulating layer preferably has a plurality of openings formed therethrough, and the openings are not formed vertically below the main pad electrode of the first electrode. In order to form the openings, a plurality of mask patterns may be formed on the second conductivity type semiconductor layer side prior to the deposition of the electrically insulating layer 7, the mask patterns being block-shaped or preferably wide-top and narrow-bottom, and the mask patterns may be metal or insulating layers or a combination of both. After the electric insulating layer is evaporated on the surface of the mask pattern, the mask pattern is removed to form an opening. When the mask pattern is a pattern with a wide top and a narrow bottom, the sidewall of the opening can be inclined, so that the subsequent ohmic contact layer and the subsequent reflecting layer can be covered on the surface of the insulating layer as flat and uniform as possible, and particularly the included angle between the sidewall of the opening of the through hole and the surface of the insulating layer is as flat as possible.

Fig. 6 provides a schematic view from above of the electrically insulating layer 7 side. Wherein the shape of the opening is circular or oval or square or polygonal.

3. And (4) high-temperature treatment, wherein fluorine is diffused into the second conduction type semiconductor layer.

After the formation of the electrically insulating layer, a high-temperature treatment is performed under the following conditions: the gas atmosphere is preferably inert gas, the temperature is 460-500 ℃, and the time is 10-30 min. As schematically shown in fig. 7, the high temperature treatment effects diffusion of fluorine ions of the electrically insulating layer 7 into the current spreading layer 82 of the second conductive semiconductor layer 8. It should be noted that the thickness of the fluorine ion diffusion can be adjusted by controlling different temperatures and times.

Fig. 8 provides SIMS elemental analysis of the local thickness direction of the structure shown in fig. 7, including concentration analysis of Ga, P, F, C, and Mg elements, with the thickness on the abscissa and the concentration of the elements on the left ordinate. In the figure, 3 longitudinal straight lines indicate different thickness positions, the position indicated by the first straight line is the interface position of the electric insulation layer fluoride and GaP, the position indicated by the second straight line corresponds to the depth position of fluorine diffusion, and the position indicated by the third straight line corresponds to the other interface position where the interface of the GaP highly doped contact layer and the GaP non-highly doped contact layer is GaP. It can be seen that the thickness of GaP is not less than 500nm and the diffusion of elemental F into GaP is not more than 40 nm.

Meanwhile, CILM tests show that the fluoride on the surface side of the semiconductor light-emitting sequence is subjected to high-temperature treatment to increase the sheet resistance of the semiconductor light-emitting sequence. It can be seen that the diffusion of F causes an increase in the local sheet resistance of the GaP layer, improving the light uniformity.

4. And manufacturing an ohmic contact layer on the surface of the electric insulating layer.

As shown in fig. 9, the ohmic contact layer 6, such as ITO or IZO, is preferably formed by sputtering or evaporation. The ohmic contact layer 6 is covered into the opening of the electric insulation layer 7, is in contact with the second conduction type semiconductor layer, and is covered to the surface side of the electric insulation layer 7, and the thickness of the ohmic contact layer is 1-500 nm.

5. A metal reflective layer, a barrier layer, and a bonding layer.

As shown in fig. 9, the reflective layer 5 is deposited or plated by evaporation, and the material of the reflective layer 5 is silver. The barrier layer 4 is evaporated to prevent the metallic silver from diffusing into the bonding layer, and the material of the barrier layer 4 is preferably at least one of titanium, platinum, chromium, and the like.

And forming a bonding layer 3 by evaporation, wherein the bonding layer 3 can be made of materials such as gold, indium or tin.

6. And bonding the base plate, and removing the growth substrate.

As shown in fig. 10, a supporting substrate 2 is selected, and a bonding layer 3 on a semiconductor light emitting sequence on a growth substrate 101 is bonded to the supporting substrate 2 by high temperature and high pressure. The support substrate 2 in this embodiment is a silicon substrate.

Removing the growth substrate 101; the growth substrate 101 may be removed using grinding, wet etching.

7. And manufacturing a first electrode and a back electrode of the substrate.

The front surface forms a first electrode 11 and the support substrate 2 forms a back metal layer 1 as a second electrode. The first electrode 11 includes a main pad electrode including an ohmic contact layer 1101 and a bonding wire layer 1102, and includes an extension electrode 1103 extending from the periphery of the main pad electrode. The ohmic contact layer 1101 of the first conductivity type semiconductor layer 10 preferably remains under the extension electrode 1103 of the first electrode 11, and the remaining ohmic contact layer 101 is etched away. The back metal layer 1 is typically made of gold or platinum.

The surface and the back side wall of the semiconductor light-emitting sequence can be further etched to form a roughened surface or pattern so as to facilitate light extraction.

8. Separate to form a single light emitting element.

The semiconductor light emitting sequence is separated into a plurality of unit regions through a separation process, and an insulating protective layer is covered on the side wall and the surface of the semiconductor light emitting sequence. The reflective layer, the barrier layer and the bonding layer and the substrate are further separated to form a plurality of unitary light emitting elements.

Fig. 12 provides a flowchart of steps of a method for fabricating a light emitting device of the present embodiment.

Example two

As shown in fig. 13, in the present example, an alternative embodiment is provided, specifically a semiconductor light emitting element comprising a semiconductor light emitting sequence including a first conductivity type semiconductor layer 10, a light emitting layer 9 and a second conductivity type semiconductor layer 8;

wherein the electrical insulation layer 7 on the second conductivity type semiconductor layer 8 side has a plurality of openings, the second conductivity type semiconductor layer side is provided as an electrical contact region and an electrical insulation region.

The openings are filled with ohmic contact pads 14, and the ohmic contact pads 14 are formed in a plurality of places, but are not formed below the main pad electrode for injecting current outside the first electrode. The ohmic contact block 14 is in the shape of a block, and the metal material is at least one of gold germanium, gold germanium nickel, gold zinc, gold beryllium, and the like. The horizontal width of each ohmic contact block 14 is 1-10 μm, and the thickness of the ohmic contact block 14 is 1-500 nm.

The metal reflective layer 5 covers the ohmic contact pads 14 and one side of the electrically insulating layer 7.

The electrical insulation layer 7 is a fluoride, specifically magnesium fluoride, calcium fluoride.

The electric insulating layer 7 is subjected to high temperature treatment to promote fluorine ions to diffuse into the second conductivity type semiconductor layer 8 to form a fluorine-containing region, and the fluorine-containing region has a current blocking effect. Preferably, fluorine ions are diffused at most into the entire thickness direction of the current spreading layer 82 p-GaP included in the second conductivity type semiconductor layer.

The structure of this embodiment is described below in connection with a growth method, which includes the steps of:

1. a semiconductor light emitting sequence was obtained on the growth substrate, the procedure being the same as in the first embodiment.

As shown in fig. 14, a semiconductor layer sequence is obtained on a growth substrate 101 by an MOCVD epitaxial growth method. The semiconductor light emitting sequence includes a first conductive type semiconductor layer, a light emitting layer, and a second conductive type semiconductor layer. The growth substrate 101 in this embodiment is gallium arsenide, and the semiconductor sequence on the gallium arsenide substrate includes a first conductivity type semiconductor layer 10, a light emitting layer 9, and a second conductivity type semiconductor layer 8 which are grown and stacked in this order. The first conductive type semiconductor layer 10 includes an n-type cladding layer, which is an aunphos in this embodiment, and the second conductive type semiconductor layer includes a p-type cladding layer, which is an aunphos, and a light emitting layer, which is an algainphos. More preferably, the first conductive type semiconductor layer may further include n-type gallium arsenide as an ohmic contact layer for ohmic contact of the subsequent first electrode. More preferably, in the present embodiment, the second conductivity type semiconductor layer 8 includes a p-type current spreading layer, and the current spreading layer is p-type gallium phosphide for ohmic contact of the second electrode.

2. And manufacturing a plurality of ohmic contact blocks.

As shown in fig. 15, a layer for forming an ohmic contact block 141 is vapor-deposited on one side of the second conductive type semiconductor layer and a silicon oxide or silicon nitride layer 15 is formed by CVD. A photoresist pattern 16 is then formed.

As shown in fig. 16, the BOE etches the silicon oxide or silicon nitride layer 15 into a plurality of blocks using the photoresist pattern 16 as a mask. As shown in fig. 17, the etching solution is selected to etch the au-zn layer 141, and the etching time is controlled to form a residual au-zn block between each block of the silicon oxide or silicon nitride layer 15 and the second conductivity type semiconductor layer, and the au-zn block is used as the ohmic contact block 14. The ohmic contact bumps 14 have a horizontal width dimension that is at least 2 μm less than the horizontal width dimension of the bumps of the silicon oxide or silicon nitride layer 15. And removing the photoresist. The ohmic contact block is subjected to a high temperature fusion process to form an ohmic contact between the ohmic contact block 14 and the current spreading layer.

3. And evaporating the electric insulating layer to form a fluoride electric insulating layer opening.

As shown in fig. 18, the photoresist is removed. A pattern with a wide top and a narrow bottom is combined by the ohmic contact block 14 and the silicon oxide or silicon nitride layer 15 to form a mask, and a fluoride electrical insulation layer is evaporated, wherein the thickness of the fluoride electrical insulation layer is 50-500 μm, preferably 50-150 μm, and more preferably about 100 μm.

As shown in fig. 19, the BOE removes the bulk of the silicon oxide or silicon nitride layer 15, and the electrical fluoride insulating layer 7 on the surface and the sidewalls of the bulk of the silicon oxide or silicon nitride layer 15 is removed, leaving the ohmic contact blocks 14 and the electrical fluoride insulating layer 7 covering the second conductivity type semiconductor layer side. The fluoride electrical insulating layer 7 has a plurality of openings, ohmic contact blocks 14 are provided in the openings, and the side walls of the openings are inclined.

4. And (5) high-temperature treatment.

After the fluoride electric insulation layer is formed, high-temperature treatment is carried out, and the conditions of the high-temperature treatment are as follows: the gas atmosphere is preferably inert gas, the temperature is 460-500 ℃, and the time is 10-30 min. It should be noted that the thickness of the fluorine ion diffusion can be adjusted by controlling different temperatures and times.

As shown in fig. 20, fluorine ions of the electrically insulating layer 7 are diffused into the current spreading layer 82 of the second electrically conductive semiconductor layer 8 by the high temperature treatment.

Plating a metal reflecting layer, a barrier layer and a bonding layer; bonding the base plate, and removing the growth substrate; manufacturing a first electrode and a back metal layer of the substrate; separate to form a single light emitting element. These steps can be performed with reference to the corresponding steps of example one. Fig. 21 provides a flowchart of steps of a method for fabricating a light emitting device of the present embodiment.

The obtained single light-emitting element is shown in fig. 13.

As an alternative implementation, the high temperature fusing step is the same as the high temperature treatment step after the formation of the fluoride insulation layer.

EXAMPLE III

As shown in fig. 22, in the present embodiment, another semiconductor light emitting element is provided, and a semiconductor light emitting sequence includes a first conductivity type semiconductor layer 10, a light emitting layer 9, and a second conductivity type semiconductor layer 8;

wherein the second conductivity type semiconductor layer 8 side comprises an electrically insulating layer having a plurality of openings, and the second conductivity type semiconductor layer side is provided as an electrical contact region and an electrical insulation region.

The opening is filled with an ohmic contact block or an ohmic contact layer.

The electric insulating layer is fluoride, specifically at least one of magnesium fluoride and calcium fluoride.

Fluorine ions of the fluoride diffuse into the second conductive type semiconductor layer to form a current blocking region.

The first electrode is formed on one side of the first conductive type semiconductor layer and includes a main pad electrode for external wire bonding and an extension electrode horizontally extending from the periphery of the main pad electrode.

In the present embodiment, the fluorine-containing region is formed mainly below the main pad electrode of the first electrode, that is, vertically below the main pad electrode for the outside of the first electrode and in the second conductivity type semiconductor layer adjacent to the periphery, and the current blocking region is formed by diffusion of fluorine ions, and the electrically insulating layer around the extension electrode is free from diffusion of fluorine ions.

The second conductive type semiconductor layer is formed on the second conductive type semiconductor layer side, and the second conductive type semiconductor layer is formed on the second conductive type semiconductor layer side.

Specifically, as shown in fig. 22, the electrically insulating layer 7 includes two portions, wherein the electrically insulating layer 71 of the first portion is mainly located vertically below the main pad electrode of the first electrode 11, that is, vertically below the main pad electrode of the first electrode 11 and in the second conductivity type semiconductor layer in the vicinity of the periphery. Wherein the ratio of the area of the covered surface of the electric insulation layer 71 of the first portion to the area of the main pad electrode of the first electrode is 1 to 1.5, and more preferably 1.2 or 1.1. More preferably, the ratio of the horizontal width of the surface covered by the electrically insulating layer 71 of the first portion to the horizontal width of the main pad electrode of the first electrode is 1 to 1.25, and still more preferably 1.2 or less, or 1.1 or less.

The electrical insulation layer 7 further includes a second portion of the electrical insulation layer 72, the second portion of the electrical insulation layer 72 is not located under the main pad electrode of the first electrode 11, and the second portion of the electrical insulation layer 72 has a plurality of openings penetrating in the thickness direction, the openings providing electrical contact regions on the second conductivity-type semiconductor layer 8 side.

In one embodiment, the ohmic contact 6 is formed under the electrically insulating layer 7, the ohmic contact layer is a transparent conductive layer such as ITO or IZO, and the ohmic contact 6 contacts the second conductive type semiconductor layer through the opening of the electrically insulating layer 72 covering at least the second portion.

This structure can effectively stabilize the voltage relative to implementing one and two.

In order to obtain the light emitting element, the present embodiment provides a manufacturing method including:

1. as shown in fig. 23, a semiconductor light emitting sequence including a first conductivity type semiconductor layer 10, a light emitting layer 9, and a second conductivity type semiconductor layer 8 is obtained on a growth substrate 101. The growth substrate is gallium arsenide.

2. As shown in fig. 24 to 25, first partial electric insulation layer 71 is evaporated and treated at a high temperature, and fluorine element is diffused into second conductivity type semiconductor layer 8 to form fluorine-containing region 801.

3. As shown in fig. 25 to 26, second partial electrically insulating layer 72 is evaporated so as to cover the remaining surface of second conductivity type semiconductor layer 8, and a plurality of openings are formed in second partial electrically insulating layer 72 so as to form ohmic contacts so as to cover electrically insulating layer 7 and the openings.

4. The remaining steps are shown in the manufacturing process flow chart of fig. 27, and can be made by referring to the corresponding steps of the first to second embodiments, so as to obtain the structure of the light emitting element shown in fig. 22. Wherein the main pad electrode of the first electrode is vertically above the first portion of the electrically insulating layer.

The semiconductor light emitting elements according to the first to third embodiments may be packaged by a package support such as EMC or ceramic package. Further package structures may be arranged on the wiring substrate according to the application requirements, and optical members such as a light guide plate, a prism sheet, a diffusion sheet, and a fluorescent sheet may be arranged on the path of light emitted from the light emitting element. Further applications may include displays such as televisions or display screens, lighting devices such as interior lights, exterior street lights, indicators, etc. depending on the application.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A semiconductor light emitting element comprising:

2. A semiconductor light emitting element according to claim 1, wherein: the fluorine-containing region is located at an interface between the second conductive type semiconductor layer and the insulating layer, and extends into the second conductive type semiconductor layer.

3. A semiconductor light emitting element according to claim 1, wherein: the electrically insulating layer is a fluoride.

4. A semiconductor light emitting element according to claim 1, wherein: the fluorine-containing region is formed by diffusing fluorine element of the electric insulating layer.

5. A semiconductor light emitting element according to claim 4, wherein: the thickness of the fluorine-containing region in the second conductive type semiconductor layer is 1 to 1000nm, and more preferably, the thickness of the fluorine-containing region is 10 to 100 nm.

6. A semiconductor light emitting element according to claim 1, wherein: the fluorine-containing region has a fluorine-containing element concentration of 1E 17-1E 21/cm³。

7. A semiconductor light emitting element according to claim 1, wherein: the second conductive type semiconductor layer includes a current spreading layer, and the fluorine-containing region is located at an interface between the current spreading layer and the electrically insulating layer and extends into the current spreading layer of the second conductive type semiconductor layer.

8. A semiconductor light emitting element according to claim 7, wherein: the current extension layer is GaP or GaAs or AlGaInP.

9. A semiconductor light emitting element according to claim 7, wherein: the thickness of the fluorine-containing region is not higher than that of the current spreading layer.

10. A semiconductor light emitting element according to claim 7, wherein: the fluorine-containing region has a thickness higher than that of the current spreading layer.

11. A semiconductor light emitting element according to claim 7, wherein: the fluorine-containing region and the lateral peripheral region are homogeneous regions.

12. A semiconductor light emitting element according to claim 1, wherein: the first electrode is arranged on one side of the first conduction type semiconductor layer and comprises a main bonding pad electrode for external routing, and the fluorine-containing region is at least positioned in the second conduction type semiconductor layer in the vertical direction of the main bonding pad electrode.

13. A semiconductor light emitting element according to claim 1, wherein: the first electrode is arranged on one side of the first conduction type semiconductor layer and comprises a main bonding pad electrode for external routing, and the fluorine-containing region is mainly positioned in the second conduction type semiconductor layer in the vertical direction of the main bonding pad electrode.

14. A semiconductor light emitting element according to claim 1, wherein: the first conductive type semiconductor layer, the light-emitting layer and the second conductive type semiconductor layer are respectively made of AlxInyGa1-x-yP (x is more than or equal to 0 and less than or equal to 1, and y is more than or equal to 0 and less than or equal to 1) and/or AlzGa1-zAs (z is more than or equal to 0 and less than or equal to 1).

15. A semiconductor light emitting element according to claim 1, wherein: the electrically insulating layer has a second electrode on a side thereof remote from the second conductivity type semiconductor layer.

16. A semiconductor light emitting element according to claim 1, wherein: the electrically insulating layer has a plurality of openings through its thickness, within which are electrical contact areas.

17. A semiconductor light emitting element according to claim 15, wherein: and the second electrode forms electric contact with one side of the second conduction type semiconductor layer through an ohmic contact layer, and the ohmic contact layer is made of a transparent conductive layer and at least covers the electric contact area.

18. A semiconductor light emitting element according to claim 15, wherein: and the second electrode and one side of the second conduction type semiconductor layer form electric contact through an ohmic contact layer, and the material of the ohmic contact layer is a combination of at least two metals.

19. A semiconductor light emitting element according to claim 15, wherein: and a metal reflecting layer is arranged between the second electrode and one side of the second conductive type semiconductor layer.

21. A method for manufacturing a semiconductor light emitting element includes:

22. A method for manufacturing a semiconductor light emitting element according to claim 21, wherein: the temperature of the high-temperature diffusion treatment is 360-600 ℃, and the time is 0.01-60 min.

23. A method for manufacturing a semiconductor light emitting element according to claim 21, wherein: after the high-temperature diffusion treatment, an ohmic contact is formed on the side of the second conductivity-type semiconductor layer not covered with the electrically insulating layer.

24. A method for manufacturing a semiconductor light emitting element according to claim 23, wherein: the ohmic contact is a transparent conductive layer or a block formed by combining a plurality of metals.

25. A method for manufacturing a semiconductor light emitting element according to claim 21, wherein: the first electrode is positioned on one side of the first conductive type semiconductor layer and comprises a main bonding pad electrode for external routing, and the fluorine-containing region is mainly formed in the second conductive type semiconductor layer of the first electrode in the vertical direction of the main bonding pad electrode for external routing by high-temperature diffusion treatment.

26. A method for manufacturing a semiconductor light emitting element according to claim 21, wherein: and before the high-temperature diffusion treatment, growing a material of an ohmic contact on the side of the second conductivity type semiconductor layer which is not covered by the electric insulation layer, wherein the material of the ohmic contact is a combination of at least two metals.

27. A method for manufacturing a semiconductor light emitting element according to claim 21, wherein: the ohmic contact step formed by the ohmic contact material and one side of the second conductive type semiconductor layer and the high-temperature diffusion treatment are the same.

28. A method for manufacturing a semiconductor light emitting element according to claim 21, wherein: the second electrode includes a metal reflective layer.

29. A method for manufacturing a semiconductor light emitting element includes:

30. A method for manufacturing a semiconductor light-emitting element according to claim 29, wherein: the high-temperature fusion step of the ohmic contact block and one side of the second conductive type semiconductor layer and the high-temperature diffusion treatment step of the electric insulating layer are the same.

31. A method for manufacturing a semiconductor light-emitting element according to claim 29, wherein: the high-temperature fusion step of the ohmic contact block and one side of the second conductive type semiconductor layer is earlier than the high-temperature diffusion treatment step of the electric insulation layer.

32. A light-emitting device obtained from the semiconductor light-emitting element according to any one of claims 1 to 20.