TWI911541B - Light-emitting device - Google Patents
Light-emitting deviceInfo
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Abstract
Description
本發明係關於一種發光元件,且特別係關於一種包含金屬反射層及反射結構的覆晶式發光元件。This invention relates to a light-emitting element, and more particularly to a flip-chip light-emitting element comprising a metal reflective layer and a reflective structure.
發光二極體(Light-Emitting Diode, LED)為固態半導體發光元件,其優點為功耗低,產生的熱能低,工作壽命長,防震,體積小,反應速度快和具有良好的光電特性,例如穩定的發光波長。因此發光二極體被廣泛應用於家用電器,設備指示燈,及光電產品等。Light-emitting diodes (LEDs) are solid-state semiconductor light-emitting devices. Their advantages include low power consumption, low heat generation, long lifespan, shock resistance, small size, fast response speed, and excellent photoelectric characteristics, such as stable emission wavelength. Therefore, LEDs are widely used in household appliances, equipment indicator lights, and optoelectronic products.
一發光元件包含一第一半導體層包含一第一斜面;一半導體平台位於第一半導體層上,包含一活性層以及一第二半導體層,並包含一第二斜面與第一半導體層相接;一接觸電極位於第二半導體層上;一反射結構位於接觸電極上,包含複數個反射結構開口;以及一金屬反射層覆蓋反射結構開口,其中接觸電極包含複數個接觸開口與複數個反射結構開口形成一對一之配置,複數個接觸凹部與複數個反射結構開口形成一對一之配置,或複數個接觸凸部與複數個反射結構開口形成一對一之配置。A light-emitting element includes a first semiconductor layer including a first bevel; a semiconductor platform located on the first semiconductor layer, including an active layer and a second semiconductor layer, and including a second bevel connected to the first semiconductor layer; a contact electrode located on the second semiconductor layer; a reflective structure located on the contact electrode, including a plurality of reflective structure openings; and a metal reflective layer covering the reflective structure openings, wherein the contact electrode includes a plurality of contact openings and a plurality of reflective structure openings arranged in a one-to-one configuration, a plurality of contact recesses and a plurality of reflective structure openings arranged in a one-to-one configuration, or a plurality of contact protrusions and a plurality of reflective structure openings arranged in a one-to-one configuration.
以下的揭露內容提供許多不同的實施例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例,以簡化說明。當然,這些特定的範例並非用以限定。例如,若是本揭露實施例敘述了一第一特徵部件形成於一第二特徵部件之上或上方,即表示其可能包含上述第一特徵部件與上述第二特徵部件是直接接觸的實施例,亦可能包含了有附加特徵部件形成於上述第一特徵部件與上述第二特徵部件之間,而使上述第一特徵部件與第二特徵部件可能未直接接觸的實施例。The following disclosure provides many different embodiments to implement the different features of this application. The following disclosure describes specific examples of the components and their arrangement for simplification. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature component formed on or above a second feature component, it indicates that it may include embodiments where the first and second feature components are in direct contact, or embodiments where an additional feature component is formed between the first and second feature components, so that the first and second feature components may not be in direct contact.
應理解的是,額外的操作步驟可實施於所述方法之前、之間或之後,且在所述方法的其他實施例中,部分的操作步驟可被取代或省略。It should be understood that additional operation steps may be performed before, during, or after the method, and in other embodiments of the method, some operation steps may be replaced or omitted.
此外,其中可能用到與空間相關用詞,例如「在…下方」、「下方」、「較低的」、「在…上方」、「上方」、「較高的」及類似的用詞,這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵部件與另一個(些)元件或特徵部件之間的關係,這些空間相關用詞包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉45度或其他方位),則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。再者,當述及一第一材料層位於一第二材料層上或之上時,包括第一材料層與第二材料層直接接觸之情形,或者,其間亦可能間隔有一或更多其它材料層之情形,在此情形中,第一材料層與第二材料層之間可能不直接接觸。在本揭露一些實施例中,關於接合、連接之用語例如「連接」、「互連」等,除非特別定義,否則可指兩個結構係直接接觸,或者亦可指兩個結構並非直接接觸,其中有其它結構設於此兩個結構之間。且此關於接合、連接之用語亦可包括兩個結構都可移動,或者兩個結構都固定之情況。In addition, spatial terms may be used, such as "below," "lower," "above," "above," "higher," and similar terms. These spatial terms are used to facilitate the description of the relationship between one or more elements or features in the diagram and another element or feature(s). These spatial terms include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 45 degrees or other orientations), the spatial adjectives used will also be interpreted according to the orientation after the turn. Furthermore, when referring to a first material layer located on or above a second material layer, this includes situations where the first and second material layers are in direct contact, or situations where one or more other material layers may be present in between, in which case the first and second material layers may not be in direct contact. In some embodiments disclosed herein, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures being in direct contact, or they may refer to two structures not being in direct contact, with other structures disposed between them. Moreover, these terms regarding joining and connecting may also include situations where both structures are movable or both structures are fixed.
在說明書中,「約」、「大約」、「大抵」、「大致」、「實質上」、「相同」、「相似」之用語通常表示一特徵值在一給定值的正負15%之內,或正負10%之內,或正負5%之內,或正負3%之內,或正負2%之內,或正負1%之內,或正負0.5%之內的範圍。在此給定的數量為大約的數量,亦即在沒有特定說明「約」、「大約」、「大抵」、「大致」、「實質上」的情況下,仍可隱含「約」、「大約」、「大抵」、「大致」、「實質上」之含義。In the specification, the terms "approximately," "about," "roughly," "substantially," "same," and "similar" generally indicate a eigenvalue within ±15%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a given value. The quantities given here are approximate, meaning that even without specific mention of "approximately," "roughly," "substantially," or "substantially," these terms can still be implied.
應當理解的是,雖然本文使用術語「第一」、「第二」、「第三」等來描述不同的元件、部件、區域、層及/或區段,這些元件、部件、區域、層及/或區段不應當被這些術語所限制。這些術語可以僅被用於將一個元件、部件、區域、層或區段與另一元件、部件、區域、層或區段區分開來。因此,在不脫離本揭露的技術的前提下,以下討論的第一元件、部件、區域、層或區段可以被稱為第二元件、部件、區域、層或區段。It should be understood that although the terms "first," "second," "third," etc., are used herein to describe different elements, components, regions, layers, and/or segments, these elements, components, regions, layers, and/or segments should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or segment from another. Therefore, without departing from the art disclosed herein, the first element, component, region, layer, or segment discussed below may be referred to as a second element, component, region, layer, or segment.
除非另外定義,在此使用的全部用語(包括技術及科學用語)具有與此篇揭露所屬之一般技藝者所通常理解的相同涵義。能理解的是,這些用語,例如在通常使用的字典中定義的用語,應被解讀成具有與相關技術及本揭露的背景或上下文一致的意思,而不應以一理想化或過度正式的方式解讀,除非在本揭露實施例有特別定義。Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted in a manner consistent with the relevant technology and the context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.
第1圖係本發明一實施例所揭示之一發光元件1的俯視圖。第2圖係沿著第1圖之切線L-L’的剖面圖。第3圖係第1圖用虛線表示之區域A的部分放大圖。第4圖係沿著第3圖之切線X-X’的剖面圖。Figure 1 is a top view of a light-emitting element 1 disclosed in an embodiment of the present invention. Figure 2 is a cross-sectional view along the tangent L-L’ of Figure 1. Figure 3 is a partial enlarged view of the area A indicated by the dashed line in Figure 1. Figure 4 is a cross-sectional view along the tangent X-X’ of Figure 3.
參考第1圖、第2圖、第3圖以及第4圖,根據一實施例的發光元件1包含一基板10具有一上表面10s、一第一半導體層21位於基板10之上表面10s上並包含一第一斜面S1與基板10之上表面10s相接、以及一半導體平台M位於第一半導體層21上。半導體平台M包含一活性層22和一第二半導體層23,以及一第二斜面S2與第一半導體層21相接。Referring to Figures 1, 2, 3, and 4, a light-emitting element 1 according to an embodiment includes a substrate 10 having an upper surface 10s, a first semiconductor layer 21 located on the upper surface 10s of the substrate 10 and including a first inclined surface S1 in contact with the upper surface 10s of the substrate 10, and a semiconductor platform M located on the first semiconductor layer 21. The semiconductor platform M includes an active layer 22 and a second semiconductor layer 23, and a second inclined surface S2 in contact with the first semiconductor layer 21.
發光元件1更包含一接觸電極30位於第二半導體層23上。一反射結構40位於接觸電極30上,並包含複數個反射結構開口400位於第二半導體層23上。一連接層51覆蓋反射結構40並填入複數個反射結構開口400以與接觸電極30及/或第二半導體層23相接觸。一金屬反射層52位於連接層51上並填入複數個反射結構開口400中。The light-emitting element 1 further includes a contact electrode 30 located on the second semiconductor layer 23. A reflective structure 40 is located on the contact electrode 30 and includes a plurality of reflective structure openings 400 located on the second semiconductor layer 23. A connection layer 51 covers the reflective structure 40 and fills the plurality of reflective structure openings 400 to contact the contact electrode 30 and/or the second semiconductor layer 23. A metallic reflective layer 52 is located on the connection layer 51 and fills the plurality of reflective structure openings 400.
發光元件1更包含一第一絕緣結構60位於半導體平台M之上,覆蓋連接層51、金屬反射層52及反射結構40,並包含一第一絕緣結構第一開口601位於第一半導體層21上以及一第一絕緣結構第二開口602位於金屬反射層52上。The light-emitting element 1 further includes a first insulating structure 60 located on the semiconductor platform M, covering the interconnect layer 51, the metal reflective layer 52 and the reflective structure 40, and includes a first opening 601 of the first insulating structure located on the first semiconductor layer 21 and a second opening 602 of the first insulating structure located on the metal reflective layer 52.
發光元件1更包含一第一延伸電極71覆蓋半導體平台M並透過第一絕緣結構第一開口601與第一半導體層21形成電連結。一第二延伸電極72覆蓋半導體平台M並覆蓋第一絕緣結構第二開口602,再透過覆蓋反射結構開口400之金屬反射層52與第二半導體層23形成電連結。一第二絕緣結構80覆蓋第一延伸電極71以及第二延伸電極72,且包含一第二絕緣結構第一開口801位於第一延伸電極71上以及一第二絕緣結構第二開口802位於第二延伸電極72上。一第一電極墊91覆蓋第二絕緣結構第一開口801並通過第一延伸電極71與第一半導體層21形成電連接。一第二電極墊92覆蓋第二絕緣結構第二開口802並通過第二延伸電極72與第二半導體層23形成電連接。The light-emitting element 1 further includes a first extended electrode 71 covering the semiconductor platform M and electrically connected to the first semiconductor layer 21 through a first opening 601 of the first insulating structure. A second extended electrode 72 covers the semiconductor platform M and the second opening 602 of the first insulating structure, and is electrically connected to the second semiconductor layer 23 through a metal reflective layer 52 covering the reflective structure opening 400. A second insulating structure 80 covers the first extended electrode 71 and the second extended electrode 72, and includes a first opening 801 of the second insulating structure located on the first extended electrode 71 and a second opening 802 of the second insulating structure located on the second extended electrode 72. A first electrode pad 91 covers the first opening 801 of the second insulation structure and forms an electrical connection with the first semiconductor layer 21 through a first extended electrode 71. A second electrode pad 92 covers the second opening 802 of the second insulation structure and forms an electrical connection with the second semiconductor layer 23 through a second extended electrode 72.
基板10可以為一成長基板以磊晶成長一半導體結構20。於一實施例中,半導體結構20包含第一半導體層21、活性層22和第二半導體層23。基板10包括用以磊晶成長磷化鋁鎵銦(AlGaInP)之砷化鎵(GaAs)晶圓,或用以成長氮化鎵(GaN)、氮化銦鎵(InGaN)、或氮化鋁鎵(AlGaN)之藍寶石(Al2O3)晶圓、氮化鎵(GaN)晶圓、碳化矽(SiC)晶圓、或氮化鋁(AlN)晶圓。The substrate 10 may be a growth substrate epitaxially grown to form a semiconductor structure 20. In one embodiment, the semiconductor structure 20 includes a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23. The substrate 10 includes gallium arsenide (GaAs) wafers for epitaxial growth of aluminum gallium indium phosphide (AlGaInP), or sapphire ( Al₂O₃ ) wafers, gallium nitride (GaN) wafers, silicon carbide ( SiC ) wafers, or aluminum gallium nitride (AlN) wafers for growth of gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN).
於本發明之一實施例中,發光元件1可以不具有基板10。例如,基板10可為用於生長半導體結構20的成長基板,然後,可通過雷射剝離(laser lift off)或化學剝離等方法將基板10與半導體結構20分離。In one embodiment of the present invention, the light-emitting element 1 may not have a substrate 10. For example, the substrate 10 may be a growth substrate for growing a semiconductor structure 20, and then the substrate 10 may be separated from the semiconductor structure 20 by means of laser lift-off or chemical peeling.
於本發明之一實施例中,藉由金屬有機化學氣相沉積法(MOCVD)、分子束磊晶(MBE)、氫化物氣相沉積法(HVPE)、物理氣相沉積法(PVD)、或離子電鍍方法以於基板10上形成具有光電特性之半導體結構20,例如發光(light-emitting)疊層,其中物理氣象沉積法包含濺鍍 (Sputtering)或蒸鍍(Evaporation)法。In one embodiment of the present invention, a semiconductor structure 20 with optoelectronic properties, such as a light-emitting layer, is formed on a substrate 10 by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydrogen vapor deposition (HVPE), physical vapor deposition (PVD), or ion electroplating. The physical vapor deposition method includes sputtering or evaporation.
藉由改變半導體結構20中一層或多層的物理及化學組成以調整發光元件1發出光線的波長。半導體結構20包含第一半導體層21、活性層22、以及第二半導體層23。半導體結構20之材料包含Ⅲ-Ⅴ族半導體材料,例如AlxInyGa(1-x-y)N或AlxInyGa(1-x-y)P,其中0≦x,y≦1;(x+y)≦1。當半導體結構20之材料為AlInGaP系列材料時,可發出波長介於610 nm及650 nm之間的紅光。當半導體結構20之材料為InGaN系列材料時,可發出波長介於400 nm及490 nm之間的藍光,或波長介於530 nm及570 nm之間的綠光。當半導體結構20之材料為AlGaN系列或AlInGaN系列材料時,可發出波長介於250 nm及400 nm之間的紫外光。The wavelength of light emitted by the light-emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor structure 20. The semiconductor structure 20 includes a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23. The material of the semiconductor structure 20 includes group III-V semiconductor materials, such as Al <sub>x </sub>In<sub>y</sub>Ga<sub> (1-xy) </sub>N or Al <sub>x </sub> In<sub>y</sub>Ga<sub> (1-xy) </sub>P, where 0≦x, y≦1; (x+y)≦1. When the material of the semiconductor structure 20 is an AlInGaP series material, red light with a wavelength between 610 nm and 650 nm can be emitted. When the semiconductor structure 20 is made of InGaN series materials, it emits blue light with wavelengths between 400 nm and 490 nm, or green light with wavelengths between 530 nm and 570 nm. When the semiconductor structure 20 is made of AlGaN series or AlInGaN series materials, it emits ultraviolet light with wavelengths between 250 nm and 400 nm.
第一半導體層21和第二半導體層23可為包覆層(cladding layer)或侷限層(confinement layer),兩者具有不同的導電型態、電性、極性,或依摻雜的元素以提供電子或電洞,例如第一半導體層21為n型電性的半導體,第二半導體層23為p型電性的半導體。活性層22形成在第一半導體層21和第二半導體層23之間,電子與電洞於一電流驅動下在活性層22複合,將電能轉換成光能,以發出一光線。活性層22可為單異質結構(single heterostructure, SH),雙異質結構(double heterostructure, DH),雙側雙異質結構(double-side double heterostructure, DDH),或是多層量子井結構(multi-quantum well, MQW)。活性層22之材料可為中性、p型或n型電性的半導體。第一半導體層21、活性層22、或第二半導體層23可為一單層或包含複數子層的結構。The first semiconductor layer 21 and the second semiconductor layer 23 can be cladding layers or confinement layers, and they have different conduction types, electrical properties, and polarities, or they can be doped with elements to provide electrons or holes. For example, the first semiconductor layer 21 is an n-type semiconductor, and the second semiconductor layer 23 is a p-type semiconductor. An active layer 22 is formed between the first semiconductor layer 21 and the second semiconductor layer 23. Electrons and holes recombine in the active layer 22 under the drive of a current, converting electrical energy into light energy to emit light. The active layer 22 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the active layer 22 can be a neutral, p-type, or n-type semiconductor. The first semiconductor layer 21, the active layer 22, or the second semiconductor layer 23 can be a single layer or a structure containing multiple sublayers.
於本發明之一實施例中,半導體結構20還可包含一緩衝層(圖未示)位於第一半導體層21和基板10之間,用以釋放基板10和半導體結構20之間因材料晶格不匹配而產生的應力,以減少差排及晶格缺陷,進而提升磊晶品質。緩衝層可為一單層或包含複數子層的結構。於一實施例中,可選用PVD氮化鋁(AlN)做為緩衝層,形成於半導體結構20及基板10之間,用以改善半導體結構20的磊晶品質。在一實施例中,用以形成PVD氮化鋁(AlN)的靶材係由氮化鋁所組成。在另一實施例中,可使用由鋁組成的靶材,於氮源的環境下與鋁靶材反應性地形成氮化鋁。In one embodiment of the present invention, the semiconductor structure 20 may further include a buffer layer (not shown) located between the first semiconductor layer 21 and the substrate 10 to release the stress generated between the substrate 10 and the semiconductor structure 20 due to material lattice mismatch, thereby reducing misalignment and lattice defects and improving epitaxial quality. The buffer layer may be a single layer or a structure containing multiple sublayers. In one embodiment, PVD aluminum nitride (AlN) may be selected as the buffer layer and formed between the semiconductor structure 20 and the substrate 10 to improve the epitaxial quality of the semiconductor structure 20. In one embodiment, the target material used to form PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, an aluminum target can be used to reactively form aluminum nitride with the aluminum target in a nitrogen source environment.
如第2圖及第4圖所示,半導體結構20包含一第一凹陷區域E1、一第二凹陷區域E2、以及為第一凹陷區域E1所圍繞之半導體平台M。在一實施例中,可通過蝕刻移除第二半導體層23、活性層22和第一半導體層21的一部分以形成第一凹陷區域E1及第二凹陷區域E2。換言之,第一凹陷區域E1及第二凹陷區域E2露出第一半導體層21的第一上表面21t。在發光元件1之一俯視圖中,如第1圖所示,第一凹陷區域E1位於半導體平台M的至少一邊,第二凹陷區域E2位於半導體平台M的內側且為半導體平台M所圍繞。在第2圖中,標記“B1”表示第一凹陷區域E1和半導體平台M之間的第一邊界B1,在第4圖中,標記“B2”表示第二凹陷區域E2和半導體平台M之間的第二邊界B2。半導體平台M的上表面20t (第二半導體層23的第二上表面23t)可以高於第一凹陷區域E1的上表面20b(第一半導體層21的第一上表面21t)和第二凹陷區域E2的上表面20b’(第一半導體層21的第一上表面21t)。在一實施例中,半導體平台M可以朝向其頂部變窄。因此,半導體平台M的側表面可以是斜面,例如第2圖及第4圖例示之第二斜面S2。As shown in Figures 2 and 4, the semiconductor structure 20 includes a first recessed region E1, a second recessed region E2, and a semiconductor platform M surrounding the first recessed region E1. In one embodiment, the first recessed region E1 and the second recessed region E2 can be formed by etching away a portion of the second semiconductor layer 23, the active layer 22, and the first semiconductor layer 21. In other words, the first recessed region E1 and the second recessed region E2 expose the first upper surface 21t of the first semiconductor layer 21. In a top view of one of the light-emitting elements 1, as shown in Figure 1, the first recessed region E1 is located on at least one side of the semiconductor platform M, and the second recessed region E2 is located inside the semiconductor platform M and surrounded by the semiconductor platform M. In Figure 2, the designation "B1" indicates the first boundary B1 between the first recessed region E1 and the semiconductor platform M. In Figure 4, the designation "B2" indicates the second boundary B2 between the second recessed region E2 and the semiconductor platform M. The upper surface 20t of the semiconductor platform M (the second upper surface 23t of the second semiconductor layer 23) may be higher than the upper surface 20b of the first recessed region E1 (the first upper surface 21t of the first semiconductor layer 21) and the upper surface 20b' of the second recessed region E2 (the first upper surface 21t of the first semiconductor layer 21). In one embodiment, the semiconductor platform M may narrow towards its top. Therefore, the side surfaces of the semiconductor platform M may be sloped, such as the second slope S2 shown in Figures 2 and 4.
在一實施例中,如第2圖所示,第一凹陷區域E1的上表面20b的一部分可以為一第一接觸第一區域CT1。如第4圖所示,第二凹陷區域E2的上表面20b’的一部分可以為一第一接觸第二區域CT1’。在一實施例中,半導體平台M的上表面20t的至少一部分定義為一第二接觸區域CT2。第一絕緣結構60包含複數個第一絕緣結構第一開口601以露出第一接觸第一區域CT1和第一接觸第二區域CT1’。反射結構40包含複數個反射結構開口400位於第二接觸區域CT2上並露出接觸電極30及/或第二半導體層23。在一實施例中,複數個第一接觸第二區域CT1’之一第一總面積A1與複數個第一接觸第一區域CT1之一第二總面積A2之間具有一比值(A1/A2)介於1~2之間以改善發光元件1之電流分布。如果比值(A1/A2)小於1,發光元件1之亮度會下降;如果比值(A1/A2)大於2,發光元件1之電壓(Vf)會上升。In one embodiment, as shown in Figure 2, a portion of the upper surface 20b of the first recessed region E1 may be a first contact region CT1. As shown in Figure 4, a portion of the upper surface 20b' of the second recessed region E2 may be a first contact region CT1'. In one embodiment, at least a portion of the upper surface 20t of the semiconductor platform M is defined as a second contact region CT2. The first insulating structure 60 includes a plurality of first insulating structure first openings 601 to expose the first contact region CT1 and the first contact region CT1'. The reflective structure 40 includes a plurality of reflective structure openings 400 located on the second contact region CT2 and exposing the contact electrode 30 and/or the second semiconductor layer 23. In one embodiment, a ratio (A1/A2) between the first total area A1 of one of the plurality of first contact second regions CT1' and the second total area A2 of one of the plurality of first contact first regions CT1 is between 1 and 2 to improve the current distribution of the light-emitting element 1. If the ratio (A1/A2) is less than 1, the brightness of the light-emitting element 1 will decrease; if the ratio (A1/A2) is greater than 2, the voltage (Vf) of the light-emitting element 1 will increase.
如第1圖所示,基板10包含第一邊11、第二邊12、第三邊13和第四邊14,半導體平台M可以與第一邊11至第四邊14間隔開,並且第一凹陷區域E1可以分佈設置在半導體平台M與第一邊11至第四邊14的任一邊或任多邊之間。例如,第一凹陷區域E1可以設置在半導體平台M與第一邊11之間以及半導體平台M與第二邊12之間,或是設置在半導體平台M與第三邊13之間以及半導體平台M與第四邊14之間。第一邊11和第二邊12可彼此相對,並且第三邊13和第四邊14可彼此相對。在一實施例中,具有長條型、矩形、圓形或橢圓形形狀並且彼此間隔開的多個第二凹陷區域E2可以佈置在半導體平台M的內部。As shown in Figure 1, the substrate 10 includes a first side 11, a second side 12, a third side 13, and a fourth side 14. The semiconductor platform M can be spaced apart from the first side 11 to the fourth side 14, and the first recessed region E1 can be distributed between the semiconductor platform M and any one or more of the first side 11 to the fourth side 14. For example, the first recessed region E1 can be disposed between the semiconductor platform M and the first side 11 and between the semiconductor platform M and the second side 12, or between the semiconductor platform M and the third side 13 and between the semiconductor platform M and the fourth side 14. The first side 11 and the second side 12 can be opposite each other, and the third side 13 and the fourth side 14 can be opposite each other. In one embodiment, a plurality of second recessed regions E2, having an elongated, rectangular, circular, or elliptical shape and spaced apart from each other, can be disposed inside the semiconductor platform M.
如第2圖及第4圖所示,接觸電極30可以直接設置在第二半導體層23上,接觸電極30與第二半導體層23相接觸的區域構成第二接觸區域CT2,並電連接到第二半導體層23。接觸電極30用於將從外部注入的電流分散後再經由半導體平台M的上表面20t(第二半導體層23的第二上表面23t) 注入上到第二半導體層23。As shown in Figures 2 and 4, the contact electrode 30 can be directly disposed on the second semiconductor layer 23. The area where the contact electrode 30 contacts the second semiconductor layer 23 constitutes the second contact area CT2 and is electrically connected to the second semiconductor layer 23. The contact electrode 30 is used to disperse the current injected from the outside and then inject it onto the second semiconductor layer 23 through the upper surface 20t of the semiconductor platform M (the second upper surface 23t of the second semiconductor layer 23).
在一實施例中,反射結構40包含複數個反射結構開口400設置在半導體平台M上。如第1圖及第3圖所示,於發光元件1之一俯視圖中,反射結構開口400包含圓形、半圓形、橢圓形、三角形、矩形、多邊形、弧形或環形。複數個反射結構開口400可以以六邊形最密排列的格子圖案佈置在半導體平台M上,但不限於此。在另一實施例中,複數個反射結構開口400可以以各種圖案佈置。例如,矩形格子圖案。如第2圖及第4圖所示,反射結構40位於接觸電極30之上並覆蓋半導體平台M之第二斜面S2,且覆蓋第一半導體層21的一部分和第二半導體層23的一部分,例如,反射結構40可以覆蓋第一半導體層21的第一上表面21t的一部分和第二半導體層23的第二上表面23t的一部分。In one embodiment, the reflective structure 40 includes a plurality of reflective structure openings 400 disposed on the semiconductor platform M. As shown in Figures 1 and 3, in a top view of one of the light-emitting elements 1, the reflective structure openings 400 include circular, semi-circular, elliptical, triangular, rectangular, polygonal, arc-shaped, or annular shapes. The plurality of reflective structure openings 400 may be arranged on the semiconductor platform M in a hexagonal grid pattern with the closest possible arrangement, but is not limited thereto. In another embodiment, the plurality of reflective structure openings 400 may be arranged in various patterns. For example, a rectangular grid pattern. As shown in Figures 2 and 4, the reflective structure 40 is located above the contact electrode 30 and covers the second inclined surface S2 of the semiconductor platform M, and covers a portion of the first semiconductor layer 21 and a portion of the second semiconductor layer 23. For example, the reflective structure 40 may cover a portion of the first upper surface 21t of the first semiconductor layer 21 and a portion of the second upper surface 23t of the second semiconductor layer 23.
於發明之一實施例中,反射結構40包含一絕緣反射鏡41及/或一絕緣層42。反射結構開口400包含一第一反射結構開口410穿過絕緣反射鏡41。如第2圖及第4圖所示,反射結構40之絕緣反射鏡41覆蓋半導體平台M之第二斜面S2以反射來自活性層22之一光線並增加發光元件1之光取出效率。In one embodiment of the invention, the reflective structure 40 includes an insulating mirror 41 and/or an insulating layer 42. The reflective structure opening 400 includes a first reflective structure opening 410 extending through the insulating mirror 41. As shown in Figures 2 and 4, the insulating mirror 41 of the reflective structure 40 covers the second inclined surface S2 of the semiconductor platform M to reflect light from the active layer 22 and increase the light extraction efficiency of the light-emitting element 1.
於發明之一實施例中,反射結構40之絕緣層42位於接觸電極30與絕緣反射鏡41之間。反射結構開口400包含一第二反射結構開口420穿過絕緣層42。如第3圖所示,於發光元件1之俯視圖中,第一反射結構開口410與第二反射結構開口420構成一同心圓的圖案。於一實施例中,如第3圖所示,第一反射結構開口410包含一第一開口寬度W1大於第二反射結構開口420所包含之一第二開口寬度W2。於發光元件1之一側視圖中,第一開口寬度W1係介於9微米(μm)~15微米之間,第二開口寬度W2係介於3微米~9微米之間。In one embodiment of the invention, the insulating layer 42 of the reflective structure 40 is located between the contact electrode 30 and the insulating mirror 41. The reflective structure opening 400 includes a second reflective structure opening 420 passing through the insulating layer 42. As shown in Figure 3, in the top view of the light-emitting element 1, the first reflective structure opening 410 and the second reflective structure opening 420 form a concentric circle pattern. In one embodiment, as shown in Figure 3, the first reflective structure opening 410 includes a first opening width W1 that is greater than a second opening width W2 included in the second reflective structure opening 420. In a side view of the light-emitting element 1, the first aperture width W1 is between 9 micrometers (μm) and 15 micrometers, and the second aperture width W2 is between 3 micrometers and 9 micrometers.
如第1圖及第3圖所示,連接層51覆蓋反射結構40並填入第一反射結構開口410以與接觸電極30相接觸,其中連接層51包含氧化鈦(TiOx)、氮化鈦(TiNx)、氧化鋁(Al2O3)、氧化銦錫 (ITO)、鋅摻雜氧化銦錫(ZITO)、氧化鋅銦(ZIO)、氧化鎵銦(GIO)、氧化鋅錫(ZTO)、氟摻雜氧化錫(FTO)、鋁摻雜氧化鋅(AZO)、鎵摻雜的氧化鋅(GZO)、或氧化鋅鎂(Zn(1-x)MgxO,0≤x ≤1)。接觸電極30包含氧化銦錫 (ITO)、鋅摻雜氧化銦錫(ZITO)、氧化鋅銦(ZIO)、氧化鎵銦(GIO)、氧化鋅錫(ZTO)、氟摻雜氧化錫(FTO)、鋁摻雜氧化鋅(AZO)、鎵摻雜的氧化鋅(GZO)、或氧化鋅鎂(Zn(1-x)MgxO,0≤x ≤1)。於發明之一實施例中,連接層51包含一厚度小於接觸電極30所包含之一厚度,例如,連接層51包含一厚度介於10埃(Å)~60埃之間,接觸電極30包含一厚度介於100埃~400埃之間。於發明之一實施例中,接觸電極30與連接層51包含相同的材料例如,接觸電極30與連接層51包含氧化銦錫(ITO)。於發明之一實施例中,接觸電極30與連接層51包含不相同的材料,例如接觸電極30包含氧化銦錫(ITO),連接層51包含氧化鋁。As shown in Figures 1 and 3, the connecting layer 51 covers the reflective structure 40 and fills the first reflective structure opening 410 to contact the contact electrode 30. The connecting layer 51 includes titanium oxide (TiO x ), titanium nitride (TiN x ), aluminum oxide (Al 2 O 3 ), indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or zinc magnesium oxide (Zn (1-x) Mg x O, 0≤x ≤1). The contact electrode 30 comprises indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc-doped indium oxide (ZIO), gallium-doped indium oxide (GIO), zinc-doped tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or zinc-magnesium oxide (Zn (1-x) MgxO , 0≤x≤1). In one embodiment of the invention, the interconnect layer 51 has a thickness less than that of the contact electrode 30. For example, the interconnect layer 51 has a thickness between 10 Å and 60 Å, and the contact electrode 30 has a thickness between 100 Å and 400 Å. In one embodiment of the invention, the contact electrode 30 and the interconnect layer 51 contain the same material; for example, the contact electrode 30 and the interconnect layer 51 contain indium tin oxide (ITO). In one embodiment of the invention, the contact electrode 30 and the interconnect layer 51 contain different materials; for example, the contact electrode 30 contains indium tin oxide (ITO), and the interconnect layer 51 contains aluminum oxide.
金屬反射層52通過連接層51填入反射結構40之反射結構開口400,其中連接層51可以提高反射結構40與金屬反射層52之間的黏合性。於發光元件1之側視圖中,於一實施例中,金屬反射層52可以設置在連接層51上且與連接層51共形。例如,金屬反射層52和連接層51可以彼此完全重疊或部分重疊。The metal reflective layer 52 fills the reflective structure opening 400 of the reflective structure 40 through the connecting layer 51, wherein the connecting layer 51 can improve the adhesion between the reflective structure 40 and the metal reflective layer 52. In a side view of the light-emitting element 1, in one embodiment, the metal reflective layer 52 can be disposed on the connecting layer 51 and conformally to the connecting layer 51. For example, the metal reflective layer 52 and the connecting layer 51 can completely overlap or partially overlap each other.
於一實施例中,金屬反射層52包含銀(Ag)、鉻(Cr)、鎳(Ni)、鈦(Ti)、鋁(Al)、銠(Rh)、釕(Ru)或前述材料之組合。In one embodiment, the metal reflective layer 52 comprises silver (Ag), chromium (Cr), nickel (Ni), titanium (Ti), aluminum (Al), rhodium (Rh), ruthenium (Ru), or a combination of the foregoing materials.
於一實施例中,發光元件1更包含設置在金屬反射層52上的阻障層(圖未示)。阻障層具有多層結構,例如,Ti和Ni交替堆疊的多層結構。In one embodiment, the light-emitting element 1 further includes a barrier layer (not shown) disposed on the metal reflective layer 52. The barrier layer has a multilayer structure, for example, a multilayer structure of alternating Ti and Ni layers.
反射結構40、連接層51和金屬反射層52可以配置成全向反射器(Omni-Directional reflector, ODR)。全向反射器可以增加從活性層22發射的光的反射率,從而提高發光元件1之光摘出效率。The reflective structure 40, the connecting layer 51, and the metal reflective layer 52 can be configured as an omni-directional reflector (ODR). The omni-directional reflector can increase the reflectivity of light emitted from the active layer 22, thereby improving the light extraction efficiency of the light-emitting element 1.
於一實施例中,反射結構40之絕緣層42係作為絕緣膜並具有一單層結構,包含氧化物或氮化物,例如選自由矽(Si)、或鈦(Ti)、鋯(Zr)、鈮(Nb)、鉭(Ta)、鋁(Al)等金屬構成的組中的至少一種氧化物或氮化物。於另一實施例中,絕緣層42亦可以為多層結構,例如由上述任兩種或兩種以上之氧化物或氮化物構成之疊層,例如SiO2、TiO2及Al2O3構成的多層結構。In one embodiment, the insulating layer 42 of the reflective structure 40 is an insulating film and has a single-layer structure comprising oxides or nitrides, such as at least one oxide or nitride selected from the group consisting of silicon (Si), titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), and aluminum (Al). In another embodiment, the insulating layer 42 may also be a multilayer structure, such as a stack composed of any two or more of the above-mentioned oxides or nitrides, for example , a multilayer structure composed of SiO2 , TiO2 , and Al2O3 .
於一實施例中,參考第2圖及第4圖,絕緣反射鏡41可以由折射率低於第二半導體層23的折射率的材料形成。絕緣反射鏡41的材料包含SiO2、SiN、SiOxNy、TiO2、Si3N4、Al2O3、TiN、AlN、ZrO2、TiAlN、TiSiN、HfO、TaO2、Nb2O5、或MgF2。在一實施例中,絕緣反射鏡41具有不同折射率的絕緣子層交替地堆疊的多層膜結構,例如分布式布拉格反射鏡(DBR)。分散式布拉格反射器結構係由具有一第一折射率之複數個第一子層和具有一第二折射率之複數個第二子層交替地堆疊所形成,且第一折射率係小於第二折射率。例如,可通過SiO2/TiO2或SiO2/Nb2O5等層疊。In one embodiment, referring to Figures 2 and 4, the insulating mirror 41 may be formed of a material with a refractive index lower than that of the second semiconductor layer 23. The material of the insulating mirror 41 includes SiO₂ , SiN , SiOₓNy , TiO₂ , Si₃N₄ , Al₂O₃ , TiN , AlN, ZrO₂ , TiAlN, TiSiN , HfO, TaO₂ , Nb₂O₅ , or MgF₂ . In one embodiment, the insulating mirror 41 is a multilayer film structure in which insulating sublayers with different refractive indices are alternately stacked, such as a distributed Bragg mirror (DBR). A distributed Bragg reflector structure is formed by alternatingly stacking a plurality of first sublayers having a first refractive index and a plurality of second sublayers having a second refractive index, wherein the first refractive index is less than the second refractive index. For example, it can be formed by stacking SiO2 / TiO2 or SiO2 / Nb2O5 .
於發明之一實施例中,當絕緣反射鏡41包含具有層疊SiO2/TiO2或SiO2/Nb2O5之分布式布拉格反射鏡結構時,絕緣層42具有一厚度大於絕緣反射鏡41所包含之各子層之一厚度。於發明之一實施例中,絕緣層42之厚度係介於3000埃~7000埃之間。In one embodiment of the invention, when the insulating mirror 41 comprises a distributed Bragg reflector structure having stacked SiO2 / TiO2 or SiO2 / Nb2O5 , the insulating layer 42 has a thickness greater than the thickness of any of the sublayers comprised of the insulating mirror 41. In one embodiment of the invention, the thickness of the insulating layer 42 is between 3000 angstroms and 7000 angstroms.
絕緣反射鏡41的最底層或最頂層可使用選自由矽(Si)、鈦(Ti)、鋯(Zr)、鈮(Nb)、鉭(Ta)、鋁(Al)構成的群組中的至少一種氧化物或氮化物。於一實施例中,絕緣反射鏡41的最底層和最頂層包含不同於位於兩者之間的中間層的材料及/或不同於中間層的的厚度及/或不同於中間層的形成工藝。The bottom or top layer of the insulating reflector 41 may be an oxide or nitride selected from the group consisting of silicon (Si), titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), and aluminum (Al). In one embodiment, the bottom and top layers of the insulating reflector 41 comprise a material and/or a thickness and/or a forming process different from that of the intermediate layer located between them.
於一實施例中,絕緣層42可包括與絕緣反射鏡41之複數個第一子層相同的材料。例如,當絕緣反射鏡41由包括SiO2/TiO2或SiO2/Nb2O5的分布式布拉格反射鏡形成時,絕緣層42可由SiO2形成。雖然絕緣層42由與絕緣反射鏡41的至少一部分相同的材料形成,但是不要求具有諸如DBR的絕緣膜那樣的高膜品質,因此,可通過不同工藝形成絕緣反射鏡41和絕緣層42。可在視覺上(例如,SEM照片或TEM照片)區分絕緣層42相對於絕緣反射鏡41的介面。於一實施例中,絕緣反射鏡41之複數個第一子層所包含之一總厚度小於絕緣層42所包含之一總厚度。In one embodiment, the insulating layer 42 may comprise the same material as a plurality of the first sublayers of the insulating mirror 41. For example, when the insulating mirror 41 is formed of a distributed Bragg reflector comprising SiO2 / TiO2 or SiO2 / Nb2O5 , the insulating layer 42 may be formed of SiO2 . Although the insulating layer 42 is formed of at least a portion of the same material as the insulating mirror 41, it is not required to have the high film quality of an insulating film such as a DBR; therefore, the insulating mirror 41 and the insulating layer 42 may be formed by different processes. The interface of the insulating layer 42 relative to the insulating mirror 41 can be visually distinguished (e.g., by SEM or TEM images). In one embodiment, the total thickness of one of the plurality of first sublayers of the insulating mirror 41 is less than the total thickness of one of the insulating layers 42.
第3圖係第1圖用虛線表示之區域A內的反射結構開口400與第二凹陷區域E2的俯視圖。第4圖係沿著第3圖之切線X-X’的剖面圖。Figure 3 is a top view of the reflective structure opening 400 and the second recessed area E2 within region A, which is indicated by dashed lines in Figure 1. Figure 4 is a cross-sectional view along the tangent X-X’ in Figure 3.
如第3圖所示,複數個反射結構開口400沿著第二凹陷區域E2和半導體平台M之間的第二邊界B2排列成一環形。複數個反射結構開口400彼此以第一最短距離D1均勻地間隔以使注入於發光元件1之電流可以均勻地分布。於一實施例中,反射結構開口400和第二邊界B2以第二最短距離D2間隔,其中第一最短距離D1可以大於第二最短距離D2。於一實施例中,第一最短距離D1及/或第二最短距離D2可以小於第二凹陷區域E2所包含之一最小寬度w。第一最短距離D1及/或第二最短距離D2可以大於第一反射結構開口410之第一開口寬度W1及第二反射結構開口420之第二開口寬度W2。As shown in Figure 3, a plurality of reflective structure openings 400 are arranged in a ring along the second boundary B2 between the second recessed region E2 and the semiconductor platform M. The plurality of reflective structure openings 400 are uniformly spaced from each other by a first shortest distance D1 so that the current injected into the light-emitting element 1 can be uniformly distributed. In one embodiment, the reflective structure openings 400 and the second boundary B2 are spaced by a second shortest distance D2, wherein the first shortest distance D1 may be greater than the second shortest distance D2. In one embodiment, the first shortest distance D1 and/or the second shortest distance D2 may be less than a minimum width w encompassed by the second recessed region E2. The first shortest distance D1 and/or the second shortest distance D2 can be greater than the first opening width W1 of the first reflective structure opening 410 and the second opening width W2 of the second reflective structure opening 420.
第5A圖~第5D圖係本發明一實施例所揭示之製造發光元件1之反射結構開口400的方法的剖視圖。Figures 5A to 5D are cross-sectional views of a method for manufacturing a reflective structure opening 400 of a light-emitting element 1, as disclosed in an embodiment of the present invention.
如第5A圖所示,首先於第二半導體層23上形成接觸電極30,接觸電極30可與第二半導體層23之間形成低阻值接觸,例如歐姆接觸。接著在接觸電極30上形成絕緣層42,並且在絕緣層42上形成絕緣反射鏡41。參考第2圖及第4圖,當絕緣反射鏡41覆蓋於半導體平台M之第二斜面S2上,第二斜面S2端點的角度會影響絕緣反射鏡41的鍍膜品質。例如,當絕緣反射鏡41覆蓋於半導體平台M上時,一斷裂面(圖未示)容易形成於半導體平台M的第二斜面S2與第一半導體層21之第一上表面21t的相接處或半導體平台M的第二斜面S2與第二半導體層23之第二上表面23t的相接處。外部水氣易沿著斷裂面侵入半導體結構20而降低發光元件1的可靠性。為了改善上述斷裂面的問題,於本實施例中,於形成絕緣反射鏡41之前,先形成絕緣層42。絕緣層42具有較絕緣反射鏡41緻密的膜質,及/或披覆較均勻的膜層厚度。當絕緣反射鏡41由多個子層構成時,絕緣層42的膜厚較絕緣反射鏡41的子層來得厚。絕緣層42可選用和絕緣反射鏡41相同或不同的形成方法。於一實施例中,可利用化學氣相沉積(CVD)或電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)方法形成具有較佳披覆性的鍍膜特性的絕緣層42。於一實施例中,可利用原子層沉積(Atomic layer deposition, ALD)之高階梯覆蓋率的特性來形成厚度均勻的絕緣反射鏡41或絕緣層42。當絕緣反射鏡41包含分布式布拉格反射鏡(DBR)結構時,分布式布拉格反射鏡(DBR)結構的每一個子層的厚度會影響到絕緣反射鏡41的反射率,於本實施例中,可以通過電子束蒸鍍(E-beam evaporation)來形成絕緣反射鏡41以穩定的控制分布式布拉格反射鏡(DBR)結構的每一個子層的厚度。As shown in Figure 5A, a contact electrode 30 is first formed on the second semiconductor layer 23. The contact electrode 30 can form a low-resistance contact with the second semiconductor layer 23, such as an ohmic contact. Next, an insulating layer 42 is formed on the contact electrode 30, and an insulating mirror 41 is formed on the insulating layer 42. Referring to Figures 2 and 4, when the insulating mirror 41 covers the second inclined surface S2 of the semiconductor platform M, the angle of the endpoint of the second inclined surface S2 will affect the coating quality of the insulating mirror 41. For example, when the insulating mirror 41 covers the semiconductor platform M, a fracture surface (not shown) is easily formed at the junction of the second inclined surface S2 of the semiconductor platform M and the first upper surface 21t of the first semiconductor layer 21, or at the junction of the second inclined surface S2 of the semiconductor platform M and the second upper surface 23t of the second semiconductor layer 23. External moisture can easily penetrate the semiconductor structure 20 along the fracture surface, reducing the reliability of the light-emitting element 1. To improve the above-mentioned fracture surface problem, in this embodiment, an insulating layer 42 is formed before forming the insulating mirror 41. The insulating layer 42 has a denser film than the insulating mirror 41 and/or a more uniform film thickness. When the insulating mirror 41 is composed of multiple sublayers, the insulating layer 42 is thicker than the sublayers of the insulating mirror 41. The insulating layer 42 can be formed using the same or different methods as the insulating mirror 41. In one embodiment, the insulating layer 42 with better coating properties can be formed using chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). In one embodiment, the high gradient coverage of atomic layer deposition (ALD) can be used to form a uniformly thick insulating mirror 41 or insulating layer 42. When the insulating mirror 41 includes a distributed Bragg reflector (DBR) structure, the thickness of each sublayer of the DBR structure affects the reflectivity of the insulating mirror 41. In this embodiment, the insulating mirror 41 can be formed by electron beam evaporation to stably control the thickness of each sublayer of the DBR structure.
如第5B圖所示,藉由旋塗、曝光、顯影等步驟在絕緣反射鏡41上形成罩幕層900。As shown in Figure 5B, a mask layer 900 is formed on the insulating reflector 41 through steps such as spin coating, exposure, and development.
如第5C圖所示,通過第一蝕刻移除未被罩幕層900覆蓋的絕緣反射鏡41,其中移除第一絕緣反射鏡41的方法包含乾蝕刻或濕蝕刻。於一實施例中,可以具有第一直徑之開孔的罩幕層900進行絕緣反射鏡41的乾蝕刻以形成之第一反射結構開口410。絕緣層42可以作為乾蝕刻的防護層或停止層,避免乾蝕刻過程中的電漿離子源損傷發光元件1的接觸電極30與第二半導體層23。為防止絕緣反射鏡41殘餘,可以於第一蝕刻來執行過度蝕刻5%至30%絕緣層42以形成第一反射結構開口410並露出一絕緣層上表面42s,確保沒有殘餘的絕緣反射鏡41。於另一實施例中,於形成第一反射結構開口410製程中,可以通過第一蝕刻來蝕刻整個絕緣層42深度直到露出第二接觸電極30之一上表面30s,使第二反射結構開口420之一側壁與第一反射結構開口410之一側壁位於同一斜面上。As shown in Figure 5C, the insulating mirror 41 not covered by the mask layer 900 is removed by a first etching process, wherein the method for removing the first insulating mirror 41 includes dry etching or wet etching. In one embodiment, the insulating mirror 41 can be dry-etched on the mask layer 900 having an opening of a first diameter to form a first reflective structure opening 410. The insulating layer 42 can serve as a protective layer or stop layer for dry etching, preventing the plasma ion source from damaging the contact electrode 30 and the second semiconductor layer 23 of the light-emitting element 1 during the dry etching process. To prevent residue from the insulating reflector 41, an over-etching of 5% to 30% of the insulating layer 42 can be performed during the first etching step to form the first reflective structure opening 410 and expose an upper surface 42s of the insulating layer, ensuring that there is no residual insulating reflector 41. In another embodiment, during the process of forming the first reflective structure opening 410, the entire depth of the insulating layer 42 can be etched through the first etching step until the upper surface 30s of one of the second contact electrodes 30 are exposed, so that one sidewall of the second reflective structure opening 420 and one sidewall of the first reflective structure opening 410 are located on the same inclined plane.
如第5D圖所示,通過第二蝕刻來移除絕緣層42直至露出接觸電極30。於一實施例中,可以具有第二直徑之開孔的罩幕層(圖未示) 進行絕緣層42的移除以形成第二反射結構開口420,於第二蝕刻中移除絕緣層42的方法可以和第一蝕刻移除絕緣反射鏡41相同或不同。於本實施例中,第一蝕刻是以乾蝕刻執行,第二蝕刻是以與第一蝕刻前述不同方法之濕蝕刻執行。於一實施例中,第二蝕刻過程中之罩幕層之開孔的第二直徑可以小於或等於第一蝕刻過程中之罩幕層之開孔的第一直徑。罩幕層900優選為易於被去除的材料,例如聚醯亞胺或光阻。當罩幕層900的材料為聚醯亞胺或光阻時,可採用電漿蝕刻的方法去除。於一實施例中,在造成較小物理損壞的條件下,可以通過調整蝕刻氣體或液體來進行第二蝕刻以減少第二蝕刻對接觸電極30的損壞。於另一實施例中,可以通過減少蝕刻時間來減少第二蝕刻對接觸電極30的損壞。As shown in Figure 5D, the insulating layer 42 is removed by a second etching process until the contact electrode 30 is exposed. In one embodiment, the insulating layer 42 can be removed from a mask layer (not shown) having an opening of a second diameter to form a second reflective structure opening 420. The method for removing the insulating layer 42 in the second etching process can be the same as or different from the method for removing the insulating reflector 41 in the first etching process. In this embodiment, the first etching process is performed by dry etching, and the second etching process is performed by wet etching, which is a different method than the first etching process described above. In one embodiment, the second diameter of the opening in the mask layer during the second etching process can be less than or equal to the first diameter of the opening in the mask layer during the first etching process. The mask layer 900 is preferably made of a material that is easily removed, such as polyimide or photoresist. When the material of the mask layer 900 is polyimide or photoresist, it can be removed by plasma etching. In one embodiment, the second etching can be performed by adjusting the etching gas or liquid to reduce damage to the contact electrode 30, while causing minimal physical damage. In another embodiment, the damage to the contact electrode 30 caused by the second etching can be reduced by reducing the etching time.
第6圖係本發明一實施例所揭示之反射結構開口400的剖面圖。當外部注入之電流於金屬反射層52中經由反射結構開口400注入於接觸電極30時,由於金屬反射層52與接觸電極30之接觸面積受限於反射結構開口400之開口大小,所以金屬反射層52與接觸電極30之間無法有較大的接觸面積。此外電流在接觸電極30中的縱向擴散能力較強,電流在接觸電極30中的橫向擴散能力較弱,使得電流較易聚積於反射結構開口400或其附近之區域。於本實施例中,為了改善反射結構開口400或其附近區域之電流橫向擴散,接觸電極30可包含複數個接觸開口300與複數個反射結構開口400形成一對一之配置。於發光元件1之俯視圖中(圖未示),接觸開口300可以與反射結構開口400包含相同或不相同之形狀,及/或形成為例如圓形或多邊形的形狀。如第6圖所示,絕緣反射鏡41包含一第一頂部41t,且第一反射結構開口410穿過絕緣反射鏡41並包含一第一側邊e1。絕緣層42包含絕緣層上表面42s,且第二反射結構開口420穿過絕緣層42並包含一第二側邊e2。接觸開口300穿過接觸電極30並包含一第三側邊e3。第一反射結構開口410包含之第一開口寬度W1大於第二反射結構開口420包含之第二開口寬度W2,使得第一側邊e1與第二側邊e2分別連接至絕緣層上表面42s上及絕緣層上表面42s之端部不同位置。在第6圖中,標記“C1”表示第一頂部41t和第一側邊e1之間的第一邊緣C1,標記“C2”表示絕緣層上表面42s和第二側邊e2之間的第二邊緣C2,標記“C3”表示第二側邊e2和第三側邊e3之間的第三邊緣C3。第一反射結構開口410為第一邊緣C1所環繞,係藉由第一邊緣C1、第一側邊e1、絕緣層上表面42s及其水平延伸線42s’所定義。第二反射結構開口420為第二邊緣C2所環繞,係藉由第二邊緣C2以及第二側邊e2所定義。接觸開口300為第三側邊e3所環繞,係藉由第三側邊e3及第二半導體層23之第二上表面23t所定義。Figure 6 is a cross-sectional view of the reflective structure opening 400 disclosed in an embodiment of the present invention. When an externally injected current is injected into the contact electrode 30 through the reflective structure opening 400 in the metal reflective layer 52, the contact area between the metal reflective layer 52 and the contact electrode 30 is limited by the size of the reflective structure opening 400, so there cannot be a large contact area between the metal reflective layer 52 and the contact electrode 30. In addition, the longitudinal diffusion ability of the current in the contact electrode 30 is strong, while the lateral diffusion ability of the current in the contact electrode 30 is weak, making it easier for the current to accumulate in or near the reflective structure opening 400. In this embodiment, to improve the lateral current diffusion in or around the reflective structure opening 400, the contact electrode 30 may include a plurality of contact openings 300 and a plurality of reflective structure openings 400 in a one-to-one configuration. In a top view of the light-emitting element 1 (not shown), the contact openings 300 may have the same or different shapes as the reflective structure openings 400, and/or be formed in, for example, circular or polygonal shapes. As shown in Figure 6, the insulating reflector 41 includes a first top portion 41t, and the first reflective structure opening 410 passes through the insulating reflector 41 and includes a first side e1. The insulating layer 42 includes an upper surface 42s, and the second reflective structure opening 420 passes through the insulating layer 42 and includes a second side e2. The contact opening 300 passes through the contact electrode 30 and includes a third side e3. The first opening width W1 of the first reflective structure opening 410 is greater than the second opening width W2 of the second reflective structure opening 420, such that the first side e1 and the second side e2 are respectively connected to different positions on the upper surface 42s of the insulating layer and at the end of the upper surface 42s of the insulating layer. In Figure 6, the designation "C1" indicates the first edge C1 between the first top portion 41t and the first side e1; the designation "C2" indicates the second edge C2 between the upper surface 42s of the insulation layer and the second side e2; and the designation "C3" indicates the third edge C3 between the second side e2 and the third side e3. The first reflective structure opening 410 is surrounded by the first edge C1 and is defined by the first edge C1, the first side e1, the upper surface 42s of the insulation layer, and its horizontal extension line 42s'. The second reflective structure opening 420 is surrounded by the second edge C2 and is defined by the second edge C2 and the second side e2. The contact opening 300 is surrounded by the third side e3 and is defined by the third side e3 and the second upper surface 23t of the second semiconductor layer 23.
連接層51及金屬反射層52分別形成於反射結構40上並填入第一反射結構開口410及第二反射結構開口420中。第二半導體層23的第二上表面23t之一第一區域包含一高阻值區23H,第二半導體層23的第二上表面23t之第二區域包含一低阻值區23L。低阻值區23L可以跟接觸電極30形成低阻值接觸,例如歐姆接觸。於一實施例中,可藉由選擇低阻值材料構成第二半導體層23之第二區域,低阻值材料可包含具有高摻雜的n型或p型雜質的Ⅲ-Ⅴ族半導體材料,以形成低阻值區23L。高阻值區23H與連接層51相接形成高阻值接觸,例如絕緣接觸或蕭特基接觸。於一實施例中,可藉由選擇高阻值材料構成第二半導體層23之第一區域,高阻值材料可包含具有低摻雜的Ⅲ-Ⅴ族半導體材料,使得第一區域的第二半導體層23與連接層51之間形成高阻值接觸,其中高阻值區23H可以為低阻值區23L所環繞。當外部電流注入時,電流經由金屬反射層52向第二半導體層23傳導時,由於連接層51與第二半導體層23之第一區域之間具有高阻值區23H,因此無電流或極少電流會透過高阻值區23H向下傳導至第二半導體層23。電流是通過連接層51與接觸電極30之接觸開口300的第三側邊e3來傳導,改善橫向電流之傳導散布,減少電流壅塞於反射結構開口400及/或接觸開口300附近。低阻值區23L包含n型雜質或p型雜質,n型雜質包含矽(Si)、碳(C)、或鍺(Ge)。p型雜質包含鎂(Mg)。n型雜質或p型雜質濃度大於51019cm-3,或是大於或等於11020cm-3。低阻值區23L包含AlxInyGa(1-x-y)N(0x1,0y1)或AlxGa(1-x)N(0x1)。於一實施例中,低阻值區23L包含的Al組成可以為0.03x0.3。高阻值區23H包含p型雜質例如為鎂(Mg),但並不特別限於鎂(Mg)。於一實施例中,高阻值區23H的p型雜質濃度大於或等於l1019cm-3,但小於低阻值區23L的n型雜質或p型雜質濃度。高阻值區23H包含AlsIntGa(1-s-t)N(0s1,0t1)或AlsGa(1-s)N(0s0.2或0s1) 。於一實施例中,高阻值區23H包含的Al組成可以為0.01s0.05。於一實施例中,當發光元件1可發出波長介於250 nm及400 nm的紫外光時,高阻值區23H包含的Al組成可以為0.3s0.8或是0.4s0.6。A bonding layer 51 and a metal reflective layer 52 are formed on the reflective structure 40 and filled into the first reflective structure opening 410 and the second reflective structure opening 420, respectively. A first region of the second upper surface 23t of the second semiconductor layer 23 includes a high-resistance region 23H, and a second region of the second upper surface 23t of the second semiconductor layer 23 includes a low-resistance region 23L. The low-resistance region 23L can form a low-resistance contact with the contact electrode 30, such as an ohmic contact. In one embodiment, the second region of the second semiconductor layer 23 can be formed by selecting a low-resistance material, which may include a III-V group semiconductor material with highly doped n-type or p-type impurities, to form the low-resistance region 23L. The high-resistance region 23H is connected to the interconnect layer 51 to form a high-resistance contact, such as an insulating contact or a Schottky contact. In one embodiment, the first region of the second semiconductor layer 23 can be formed by selecting a high-resistance material, which may include a low-doped III-V group semiconductor material, so that a high-resistance contact is formed between the second semiconductor layer 23 in the first region and the interconnect layer 51, wherein the high-resistance region 23H may be surrounded by the low-resistance region 23L. When an external current is injected, as the current is conducted from the metal reflective layer 52 to the second semiconductor layer 23, due to the high-resistivity region 23H between the interconnect layer 51 and the first region of the second semiconductor layer 23, very little or no current is conducted downwards through the high-resistivity region 23H to the second semiconductor layer 23. The current is conducted through the third side e3 of the contact opening 300 between the interconnect layer 51 and the contact electrode 30, improving the lateral current conduction and reducing current congestion near the reflective structure opening 400 and/or the contact opening 300. The low-resistivity region 23L contains n-type or p-type impurities, with n-type impurities including silicon (Si), carbon (C), or germanium (Ge). p-type impurities include magnesium (Mg). n-type or p-type impurities with a concentration greater than 5... 10 19 cm -3 , or greater than or equal to 1 10 20 cm -3 . Low resistance region 23L contains Al x In y Ga (1-xy) N(0 x 1,0 y 1) or Al x Ga (1-x) N (0 x 1) In one embodiment, the Al composition of the low-resistivity region 23L can be 0.03. x 0.3. The high-resistivity region 23H contains p-type impurities such as magnesium (Mg), but is not particularly limited to magnesium (Mg). In one embodiment, the p-type impurity concentration in the high-resistivity region 23H is greater than or equal to 1. 10 19 cm⁻³ , but less than the concentration of n-type or p-type impurities in the low-resistivity region 23L. The high- resistivity region 23H contains Al₂S₃In₃tGa₂ ( 1-st) N(0). s 1,0 t 1) or Al s Ga (1-s) N (0 s 0.2 or 0 s 1). In one embodiment, the Al composition of the high-resistivity region 23H can be 0.01. s 0.05. In one embodiment, when the light-emitting element 1 can emit ultraviolet light with wavelengths between 250 nm and 400 nm, the Al composition of the high-resistivity region 23H can be 0.3. s 0.8 or 0.4 s 0.6.
參考第5A圖~第5D圖揭示之反射結構開口400的方法,形成可與第二半導體層23歐姆接觸的接觸電極30之後,在接觸電極30上依序形成絕緣層42以及絕緣反射鏡41。如第6圖所示,以具有第一直徑之開孔的罩幕層(圖未示)進行絕緣反射鏡41的蝕刻以形成第一反射結構開口410,再以具有第二直徑之開孔的罩幕層(圖未示)進行絕緣層42的蝕刻以形成第二反射結構開口420,其中第二直徑可以小於第一直徑。於本實施例中,通過在不同製程中形成第一反射結構開口410與第二反射結構開口420,使得絕緣反射鏡41之第一側邊e1與絕緣層42之第二側邊e2不位於同一斜面上。於本實施例中,可以於同一製程中形成第二反射結構開口420與接觸開口300,使得接觸開口300之第三側邊e3與第二側邊e2具有相同之斜率而位於同一斜面上。於形成接觸開口300之過程中,第一區域上包含低阻值材料的第二半導體層23(低阻值區23L)被蝕刻移除而露出高阻值區23H,使得第二半導體層23之第二上表面23t的低阻值區23L與高阻值區23H之間包含一階差h。於一實施例中,階差h包含小於或等於20 nm的厚度,但至少大於0.1 nm。Referring to the method of the reflective structure opening 400 shown in Figures 5A to 5D, after forming a contact electrode 30 that can make ohmic contact with the second semiconductor layer 23, an insulating layer 42 and an insulating mirror 41 are sequentially formed on the contact electrode 30. As shown in Figure 6, the insulating mirror 41 is etched with a mask layer (not shown) having an opening of a first diameter to form the first reflective structure opening 410, and then the insulating layer 42 is etched with a mask layer (not shown) having an opening of a second diameter to form the second reflective structure opening 420, wherein the second diameter may be smaller than the first diameter. In this embodiment, by forming the first reflective structure opening 410 and the second reflective structure opening 420 in different processes, the first side e1 of the insulating reflector 41 and the second side e2 of the insulating layer 42 are not located on the same inclined plane. In this embodiment, the second reflective structure opening 420 and the contact opening 300 can be formed in the same process, so that the third side e3 of the contact opening 300 and the second side e2 have the same slope and are located on the same inclined plane. During the formation of the contact opening 300, the second semiconductor layer 23 (low-resistance region 23L) containing low-resistance material in the first region is etched away to expose the high-resistance region 23H, such that there is a step difference h between the low-resistance region 23L and the high-resistance region 23H on the second upper surface 23t of the second semiconductor layer 23. In one embodiment, the step difference h includes a thickness of less than or equal to 20 nm, but at least greater than 0.1 nm.
第7圖係本發明另一實施例所揭示之反射結構開口400的剖面圖。在第7圖所揭露的實施例中,高阻值區23H及低阻值區23L的材料組成類似於第6圖所揭露的實施例,此處不再贅述。參考第5A圖~第5D圖揭示之反射結構開口400的方法,形成可與第二半導體層23歐姆接觸的接觸電極30之後,在接觸電極30上依序形成絕緣層42以及絕緣反射鏡41。如第7圖所示,以具有第一直徑之開孔的罩幕層(圖未示)進行絕緣反射鏡41的蝕刻以形成第一反射結構開口410,再以具有第二直徑之開孔的罩幕層(圖未示)進行絕緣層42的蝕刻以形成第二反射結構開口420,並以具有一第三直徑之開孔的罩幕層(圖未示)進行接觸電極30的蝕刻以形成接觸開口300,其中第二直徑可以小於第一直徑且第三直徑可以小於第二直徑。於本實施例中,如第7圖所示,絕緣反射鏡41包含第一頂部41t,且第一反射結構開口410穿過絕緣反射鏡41並包含第一側邊e1。絕緣層42包含絕緣層上表面42s,且第二反射結構開口420穿過絕緣層42並包含第二側邊e2。接觸開口300穿過接觸電極30並包含第三側邊e3。於本實施例中,通過在不同製程中形成第一反射結構開口410,第二反射結構開口420與接觸開口300,使得絕緣反射鏡41之第一側邊e1與絕緣層42之第二側邊e2不位於同一斜面上,且接觸開口300之第三側邊e3與絕緣層42之第二側邊e2不位於同一斜面上。第一反射結構開口410所包含之第一開口寬度W1大於第二反射結構開口420所包含之第二開口寬度W2,使得第一側邊e1與第二側邊e2分別連接至絕緣層上表面42s上及絕緣層上表面42s之端部不同位置。第二反射結構開口420所包含之第二開口寬度W2大於接觸開口300所包含之第三開口寬度W3,使得第二側邊e2與第三側邊e3分別連接至接觸電極30之一上表面30s上及上表面30s之端部不同位置。在第7圖中,標記“C1”表示第一頂部41t和第一側邊e1之間的第一邊緣C1,標記“C2”表示絕緣層上表面42s和第二側邊e2之間的第二邊緣C2,標記“C3”表示接觸電極30之上表面30s和第三側邊e3之間的第三邊緣C3。第一反射結構開口410為第一邊緣C1所環繞,係藉由第一邊緣C1、第一側邊e1、絕緣層上表面42s及其水平延伸線42s’所定義。第二反射結構開口420為第二邊緣C2所環繞,係藉由第二邊緣C2、第二側邊e2、接觸電極30之上表面30s及其水平延伸線30s’所定義。接觸開口300為第三邊緣C3所環繞,係藉由第三邊緣C3、第三側邊e3、以及第二半導體層23之第二上表面23t所定義。於形成接觸開口300之過程中,第一區域上包含低阻值材料的第二半導體層23(低阻值區23L)被蝕刻移除而露出高阻值區23H,使得第二半導體層23之第二上表面23t的低阻值區23L與高阻值區23H之間包含一階差h。於一實施例中,階差h包含小於或等於20 nm的厚度,但至少大於0.1 nm。當外部電流注入時,電流經由金屬反射層52向第二半導體層23傳導時,由於連接層51與第二半導體層23之第一區域之間具有高阻值區23H,因此無電流或極少電流會透過高阻值區23H向下傳導至第二半導體層23。電流是通過連接層51與接觸電極30之接觸開口300的第三側邊e3來傳導,改善橫向電流之傳導散布,減少電流壅塞於反射結構開口400及/或接觸開口300附近。Figure 7 is a cross-sectional view of the reflective structure opening 400 disclosed in another embodiment of the present invention. In the embodiment disclosed in Figure 7, the material composition of the high-resistivity region 23H and the low-resistivity region 23L is similar to that disclosed in Figure 6, and will not be described again here. Referring to the method of the reflective structure opening 400 disclosed in Figures 5A to 5D, after forming a contact electrode 30 that can make ohmic contact with the second semiconductor layer 23, an insulating layer 42 and an insulating mirror 41 are sequentially formed on the contact electrode 30. As shown in Figure 7, an insulating mirror 41 is etched with a mask layer (not shown) having an opening of a first diameter to form a first reflective structure opening 410. An insulating layer 42 is etched with a mask layer (not shown) having an opening of a second diameter to form a second reflective structure opening 420. A contact electrode 30 is etched with a mask layer (not shown) having an opening of a third diameter to form a contact opening 300. The second diameter may be smaller than the first diameter and the third diameter may be smaller than the second diameter. In this embodiment, as shown in Figure 7, the insulating reflector 41 includes a first top portion 41t, and a first reflective structure opening 410 extends through the insulating reflector 41 and includes a first side e1. The insulating layer 42 includes an upper surface 42s, and a second reflective structure opening 420 extends through the insulating layer 42 and includes a second side e2. The contact opening 300 extends through the contact electrode 30 and includes a third side e3. In this embodiment, by forming the first reflective structure opening 410, the second reflective structure opening 420, and the contact opening 300 in different manufacturing processes, the first side e1 of the insulating reflector 41 and the second side e2 of the insulating layer 42 are not located on the same inclined plane, and the third side e3 of the contact opening 300 and the second side e2 of the insulating layer 42 are not located on the same inclined plane. The width W1 of the first opening included in the first reflective structure opening 410 is greater than the width W2 of the second opening included in the second reflective structure opening 420, so that the first side e1 and the second side e2 are respectively connected to different positions on the upper surface 42s of the insulating layer and at the end of the upper surface 42s of the insulating layer. The width W2 of the second opening included in the second reflective structure opening 420 is greater than the width W3 of the third opening included in the contact opening 300, such that the second side e2 and the third side e3 are respectively connected to different positions on the upper surface 30s of one of the contact electrodes 30 and at the end of the upper surface 30s. In Figure 7, the mark "C1" indicates the first edge C1 between the first top 41t and the first side e1, the mark "C2" indicates the second edge C2 between the upper surface 42s of the insulating layer and the second side e2, and the mark "C3" indicates the third edge C3 between the upper surface 30s of the contact electrode 30 and the third side e3. The first reflective structure opening 410 is surrounded by the first edge C1 and is defined by the first edge C1, the first side e1, the upper surface 42s of the insulating layer, and its horizontal extension line 42s'. The second reflective structure opening 420 is surrounded by the second edge C2 and is defined by the second edge C2, the second side e2, the upper surface 30s of the contact electrode 30, and its horizontal extension line 30s'. The contact opening 300 is surrounded by the third edge C3 and is defined by the third edge C3, the third side e3, and the second upper surface 23t of the second semiconductor layer 23. During the formation of the contact opening 300, the second semiconductor layer 23 (low-resistance region 23L) containing low-resistance material in the first region is etched away to expose the high-resistance region 23H, such that there is a step difference h between the low-resistance region 23L and the high-resistance region 23H on the second upper surface 23t of the second semiconductor layer 23. In one embodiment, the step difference h includes a thickness of less than or equal to 20 nm, but at least greater than 0.1 nm. When an external current is injected, as the current is conducted to the second semiconductor layer 23 through the metal reflective layer 52, because there is a high-resistance region 23H between the connecting layer 51 and the first region of the second semiconductor layer 23, no or very little current is conducted downward through the high-resistance region 23H to the second semiconductor layer 23. The current is conducted through the third side e3 of the contact opening 300 of the contact layer 51 and the contact electrode 30, which improves the conduction and distribution of the lateral current and reduces current congestion in the vicinity of the reflective structure opening 400 and/or the contact opening 300.
第8圖係本發明一實施例所揭示之反射結構開口400的剖面圖。在第8圖所揭露的實施例中,高阻值區23H及低阻值區23L的材料組成類似於第6圖所揭露的實施例,此處不再贅述。於本實施例中,可先以具有一第四直徑之開孔的罩幕層(圖未示)進行第二半導體層23的蝕刻至第二半導體層23之一深度並暴露出第二上表面23t之第一區域,以形成具有高阻值區23H之一第二半導體層凹部231。且第二半導體層23第二區域之第二上表面23t為低阻值區23L與接觸電極30形成歐姆接觸。第一區域上包含低阻值材料的第二半導體層23被蝕刻移除而露出具有高阻值區23H的第二半導體層凹部231後,當接觸電極30填入第二半導體層凹部231時,接觸電極30包含一具有一第三側面e3’之接觸凹部302對應於第二半導體層凹部231。接觸電極30與第二半導體層23之低阻值區23L形成歐姆接觸,位於第二半導體層凹部231之接觸電極30與高阻值區23H相接形成高阻值接觸。參考第5A圖~第5D圖揭示之反射結構開口400的方法,於第二半導體層23上形成接觸電極30之後,在接觸電極30上依序形成絕緣層42以及絕緣反射鏡41。如第8圖所示,以具有第一直徑之開孔的罩幕層(圖未示)進行絕緣反射鏡41的蝕刻以形成第一反射結構開口410,再以具有第二直徑之開孔的罩幕層(圖未示)進行絕緣層42的蝕刻以形成第二反射結構開口420。後續於接觸電極30上形成連接層51及金屬反射層52,連接層51與接觸電極30之接觸凹部302之間具有低阻值之接觸,當外部電流透過金屬反射層52經由連接層51注入時,由於接觸電極30之接觸凹部302與高阻值區23H之間存在高阻值接觸,使得電流無法向下傳導至第二半導體層23,因此電流透過接觸電極30橫向分散後再注入第二半導體層23中,減少電流壅塞於反射結構開口400附近。Figure 8 is a cross-sectional view of the reflective structure opening 400 disclosed in an embodiment of the present invention. In the embodiment disclosed in Figure 8, the material composition of the high-resistivity region 23H and the low-resistivity region 23L is similar to that disclosed in Figure 6, and will not be repeated here. In this embodiment, the second semiconductor layer 23 can be etched to a depth of the second semiconductor layer 23 using a mask layer (not shown) with an opening of a fourth diameter, exposing a first region of the second upper surface 23t to form a second semiconductor layer recess 231 with a high-resistivity region 23H. The second upper surface 23t of the second region of the second semiconductor layer 23 is the low-resistivity region 23L, which forms an ohmic contact with the contact electrode 30. After the second semiconductor layer 23 containing low-resistivity material in the first region is etched away to expose the second semiconductor layer recess 231 having a high-resistivity region 23H, when the contact electrode 30 is filled into the second semiconductor layer recess 231, the contact electrode 30 includes a contact recess 302 with a third side surface e3' corresponding to the second semiconductor layer recess 231. The contact electrode 30 forms an ohmic contact with the low-resistivity region 23L of the second semiconductor layer 23, and the contact electrode 30 located in the second semiconductor layer recess 231 is connected to the high-resistivity region 23H to form a high-resistivity contact. Referring to the method of the reflective structure opening 400 shown in Figures 5A to 5D, after forming the contact electrode 30 on the second semiconductor layer 23, an insulating layer 42 and an insulating mirror 41 are sequentially formed on the contact electrode 30. As shown in Figure 8, the insulating mirror 41 is etched with a mask layer (not shown) having an opening of a first diameter to form the first reflective structure opening 410, and then the insulating layer 42 is etched with a mask layer (not shown) having an opening of a second diameter to form the second reflective structure opening 420. Subsequently, a connection layer 51 and a metal reflective layer 52 are formed on the contact electrode 30. The connection layer 51 and the contact recess 302 of the contact electrode 30 have a low resistance contact. When an external current is injected through the metal reflective layer 52 and the connection layer 51, the current cannot be conducted downward to the second semiconductor layer 23 because there is a high resistance contact between the contact recess 302 of the contact electrode 30 and the high resistance region 23H. Therefore, the current is laterally dispersed through the contact electrode 30 and then injected into the second semiconductor layer 23, reducing current congestion near the opening 400 of the reflective structure.
相較於第二半導體層23之低阻值區23L,位於高阻值區23H的第二半導體層凹部231包含一階差H。於一實施例中,階差H包含小於或等於20 nm的深度,但至少大於0.1 nm。當接觸電極30填入第二半導體層凹部231時,接觸凹部302包含一階差h大致與第二半導體層凹部231之階差H相同,或是接觸凹部302之階差h與第二半導體層凹部231之階差H之間包含一差值小於第二半導體層凹部231之階差H或是接觸凹部302之階差h的10%。於本實施例中,如第8圖所示,絕緣反射鏡41包含第一頂部41t,且第一反射結構開口410穿過絕緣反射鏡41並包含第一側邊e1。絕緣層42包含絕緣層上表面42s,且第二反射結構開口420穿過絕緣層42並包含第二側邊e2。接觸電極30之接觸凹部302包含第三側面e3’。第一反射結構開口410所包含之第一開口寬度W1大於第二反射結構開口420所包含之第二開口寬度W2,使得第一側邊e1與第二側邊e2分別連接至絕緣層上表面42s上及絕緣層上表面42s之端部不同位置。第二反射結構開口420所包含之第二開口寬度W2大於接觸凹部302所包含之一第三凹部寬度W3’,使得第二側邊e2與第三側面e3’分別連接至接觸電極30上表面30s上及接觸電極30上表面30s之端部不同位置。在第8圖中,標記“C1”表示第一頂部41t和第一側邊e1之間的第一邊緣C1,標記“C2”表示絕緣層上表面42s和第二側邊e2之間的第二邊緣C2。第一反射結構開口410為第一邊緣C1所環繞,係藉由第一邊緣C1、第一側邊e1、絕緣層上表面42s及其水平延伸線42s’所定義。第二反射結構開口420為第二邊緣C2所環繞,係藉由第二邊緣C2、第二側邊e2、接觸電極30之上表面30s、第三側面e3’及第二半導體層23之第二上表面23t所定義。Compared to the low-resistivity region 23L of the second semiconductor layer 23, the second semiconductor layer recess 231 located in the high-resistivity region 23H includes a step difference H. In one embodiment, the step difference H includes a depth less than or equal to 20 nm, but at least greater than 0.1 nm. When the contact electrode 30 is filled into the second semiconductor layer recess 231, the contact recess 302 includes a step difference h that is substantially the same as the step difference H of the second semiconductor layer recess 231, or the step difference h of the contact recess 302 and the step difference H of the second semiconductor layer recess 231 include a difference less than 10% of the step difference H of the second semiconductor layer recess 231 or the step difference h of the contact recess 302. In this embodiment, as shown in Figure 8, the insulating reflector 41 includes a first top portion 41t, and a first reflective structure opening 410 extends through the insulating reflector 41 and includes a first side e1. The insulating layer 42 includes an upper surface 42s, and a second reflective structure opening 420 extends through the insulating layer 42 and includes a second side e2. The contact recess 302 of the contact electrode 30 includes a third side e3'. The width W1 of the first opening of the first reflective structure opening 410 is greater than the width W2 of the second opening of the second reflective structure opening 420, such that the first side e1 and the second side e2 are respectively connected to different positions on the upper surface 42s of the insulation layer and at the end of the upper surface 42s of the insulation layer. The width W2 of the second opening of the second reflective structure opening 420 is greater than the width W3' of a third recess included in the contact recess 302, such that the second side e2 and the third side e3' are respectively connected to different positions on the upper surface 30s of the contact electrode 30 and at the end of the upper surface 30s of the contact electrode 30. In Figure 8, the designation "C1" indicates the first edge C1 between the first top portion 41t and the first side e1, and the designation "C2" indicates the second edge C2 between the upper surface 42s of the insulating layer and the second side e2. The first reflective structure opening 410 is surrounded by the first edge C1 and is defined by the first edge C1, the first side e1, the upper surface 42s of the insulating layer, and its horizontal extension line 42s'. The second reflective structure opening 420 is surrounded by the second edge C2 and is defined by the second edge C2, the second side e2, the upper surface 30s of the contact electrode 30, the third side e3', and the second upper surface 23t of the second semiconductor layer 23.
於發光元件1之俯視圖(圖未示)觀之,第二半導體層凹部231與複數個反射結構開口400形成一對一之配置。當接觸電極30形成於第二半導體層23之第二上表面23t時,接觸電極30包含平面部301位於低阻值區23L上以及接觸凹部302位於高阻值區23H上。於發光元件1之俯視圖(圖未示)觀之,接觸電極30之複數個接觸凹部302與複數個反射結構開口400形成一對一之配置,且平面部301環繞複數個接觸凹部302。於一實施例中,接觸電極30之平面部301所包含之一厚度與接觸電極30之接觸凹部302所包含之一厚度之間的厚度差小於平面部301或接觸凹部302所包含之厚度的10%。Viewed from a top view (not shown) of the light-emitting element 1, the second semiconductor layer recess 231 and the plurality of reflective structure openings 400 are configured in a one-to-one manner. When the contact electrode 30 is formed on the second upper surface 23t of the second semiconductor layer 23, the contact electrode 30 includes a planar portion 301 located on the low resistance region 23L and a contact recess 302 located on the high resistance region 23H. Viewed from a top view (not shown) of the light-emitting element 1, the plurality of contact recesses 302 of the contact electrode 30 and the plurality of reflective structure openings 400 are configured in a one-to-one manner, and the planar portion 301 surrounds the plurality of contact recesses 302. In one embodiment, the thickness difference between the thickness of the planar portion 301 of the contact electrode 30 and the thickness of the contact recess 302 of the contact electrode 30 is less than 10% of the thickness of the planar portion 301 or the contact recess 302.
第9圖係本發明一實施例所揭示之反射結構開口400的剖面圖。在第9圖所揭露的實施例中,第二半導體層23之第二上表面23t包含低阻值區23L可以跟接觸電極30形成歐姆接觸。低阻值區23L的材料組成類似於第6圖所揭露的實施例,此處不再贅述。於本實施例中,複數個電流阻擋部33形成於第二半導體層23之第二上表面23t上,且接觸電極30覆蓋第二半導體層23之第二上表面23t以及複數個電流阻擋部33。參考第5A圖~第5D圖揭示之反射結構開口400的方法,形成可與第二半導體層23歐姆接觸的接觸電極30之後,在接觸電極30上依序形成絕緣層42以及絕緣反射鏡41。如第9圖所示,以具有第一直徑之開孔的罩幕層(圖未示)進行絕緣反射鏡41的蝕刻以形成第一反射結構開口410,再以具有第二直徑之開孔的罩幕層(圖未示)進行絕緣層42的蝕刻以形成第二反射結構開口420。Figure 9 is a cross-sectional view of the reflective structure opening 400 disclosed in an embodiment of the present invention. In the embodiment disclosed in Figure 9, the second upper surface 23t of the second semiconductor layer 23 includes a low-resistance region 23L that can form an ohmic contact with the contact electrode 30. The material composition of the low-resistance region 23L is similar to that of the embodiment disclosed in Figure 6, and will not be described again here. In this embodiment, a plurality of current blocking portions 33 are formed on the second upper surface 23t of the second semiconductor layer 23, and the contact electrode 30 covers the second upper surface 23t of the second semiconductor layer 23 and the plurality of current blocking portions 33. Referring to the method of the reflective structure opening 400 shown in Figures 5A to 5D, after forming a contact electrode 30 that can make ohmic contact with the second semiconductor layer 23, an insulating layer 42 and an insulating mirror 41 are sequentially formed on the contact electrode 30. As shown in Figure 9, the insulating mirror 41 is etched with a mask layer (not shown) having an opening of a first diameter to form the first reflective structure opening 410, and then the insulating layer 42 is etched with a mask layer (not shown) having an opening of a second diameter to form the second reflective structure opening 420.
於發光元件1之上視圖中(圖未示),複數個電流阻擋部33與複數個反射結構開口400形成一對一之配置。當接觸電極30形成於第二半導體層23之第二上表面23t時,接觸電極30包含平面部301位於低阻值區23L上以及接觸凸部303位於電流阻擋部33上。於一實施例中,接觸電極30包含複數個接觸凸部303分別位於複數個電流阻擋部33上,並與複數個反射結構開口400形成一對一之配置。如第9圖所示,絕緣反射鏡41包含第一頂部41t,且第一反射結構開口410穿過絕緣反射鏡41並包含第一側邊e1。絕緣層42包含絕緣層上表面42s,且第二反射結構開口420穿過絕緣層42並包含第二側邊e2。第一反射結構開口410包含第一開口寬度W1大於第二反射結構開口420包含之第二開口寬度W2,使得第一側邊e1與第二側邊e2分別連接至絕緣層上表面42s上及絕緣層上表面42s之端部不同位置。在第9圖中,標記“C1”表示第一頂部41t和第一側邊e1之間的第一邊緣C1,標記“C2”表示絕緣層上表面42s和第二側邊e2之間的第二邊緣C2。第一反射結構開口410為第一邊緣C1所環繞,係藉由第一邊緣C1、第一側邊e1、絕緣層上表面42s及其水平延伸線42s’所定義。第二反射結構開口420為第二邊緣C2所環繞,係藉由第二邊緣C2、第二側邊e2、接觸電極30之上表面30s以及接觸凸部303之表面所定義。當外部電流透過金屬反射層52經由連接層51注入時,由於接觸凸部303與第二半導體層23之間具有電流阻擋部33而存在高阻值接觸,使得電流無法向下傳導至第二半導體層23,因此電流透過接觸電極30橫向分散後再注入第二半導體層23中,減少電流壅塞於反射結構開口400附近。In a top view of the light-emitting element 1 (not shown), a plurality of current-blocking portions 33 and a plurality of reflective structure openings 400 are configured one-to-one. When a contact electrode 30 is formed on the second upper surface 23t of the second semiconductor layer 23, the contact electrode 30 includes a planar portion 301 located on the low-resistance region 23L and a contact protrusion 303 located on the current-blocking portion 33. In one embodiment, the contact electrode 30 includes a plurality of contact protrusions 303 respectively located on the plurality of current-blocking portions 33, and configured one-to-one with the plurality of reflective structure openings 400. As shown in Figure 9, the insulating mirror 41 includes a first top portion 41t, and a first reflective structure opening 410 passes through the insulating mirror 41 and includes a first side e1. The insulating layer 42 includes an upper surface 42s, and a second reflective structure opening 420 passes through the insulating layer 42 and includes a second side e2. The first reflective structure opening 410 has a first opening width W1 that is greater than the second opening width W2 of the second reflective structure opening 420, such that the first side e1 and the second side e2 are respectively connected to different positions on the upper surface 42s and at the end of the upper surface 42s. In Figure 9, the designation "C1" indicates the first edge C1 between the first top portion 41t and the first side edge e1, and the designation "C2" indicates the second edge C2 between the upper surface 42s of the insulation layer and the second side edge e2. The first reflective structure opening 410 is surrounded by the first edge C1 and is defined by the first edge C1, the first side edge e1, the upper surface 42s of the insulation layer, and its horizontal extension line 42s'. The second reflective structure opening 420 is surrounded by the second edge C2 and is defined by the second edge C2, the second side edge e2, the upper surface 30s of the contact electrode 30, and the surface of the contact protrusion 303. When an external current is injected through the metal reflective layer 52 and the connecting layer 51, a high-resistance contact exists between the contact protrusion 303 and the second semiconductor layer 23 due to the current blocking portion 33. This prevents the current from being conducted downwards to the second semiconductor layer 23. Therefore, the current is laterally dispersed through the contact electrode 30 and then injected into the second semiconductor layer 23, reducing current congestion near the reflective structure opening 400.
複數個電流阻擋部33係位於接觸電極30之複數個接觸凸部303與第二半導體層23之間。電流阻擋部33可設置在反射結構開口400下方,同時具有與反射結構開口400的形狀相同或不同的形狀,並且與反射結構開口400相比,電流阻擋部33可具有較小的尺寸,因此接觸電極30可形成在電流阻擋部33之一側面33e上。例如,電流阻擋部33包含一第四寬度W4小於第二反射結構開口420所包含之第二開口寬度W2。電流阻擋部33可包括絕緣材料,例如可包括SiO2、SiN、A12O3、HfO、TiO2和ZrO之一。由於電流阻擋部33設置在反射結構開口400下,施加至金屬反射層52的電流可經由反射結構開口400橫向散佈於接觸電極30,而不會聚集於反射結構開口400。於一實施例中,電流阻擋部33可具有不同折射率的絕緣子層交替地堆疊的多層膜結構,例如分布式布拉格反射鏡(DBR)。分散式布拉格反射器(DBR)結構係由具有一第一折射率之複數個第一子層和具有一第二折射率之複數個第二子層交替地堆疊所形成,且第一折射率係小於第二折射率。例如,可通過SiO2/TiO2或SiO2/Nb2O5等層疊。A plurality of current blocking portions 33 are located between a plurality of contact protrusions 303 of the contact electrode 30 and the second semiconductor layer 23. The current blocking portions 33 may be disposed below the reflective structure opening 400 and have the same or different shape as the reflective structure opening 400. Compared with the reflective structure opening 400, the current blocking portions 33 may have a smaller size, so the contact electrode 30 may be formed on one side 33e of the current blocking portion 33. For example, the current blocking portion 33 includes a fourth width W4 that is smaller than the second opening width W2 included in the second reflective structure opening 420. The current blocking portion 33 may include an insulating material, such as one of SiO2 , SiN, Al2O3 , HfO , TiO2 , and ZrO. Since the current blocking portion 33 is disposed below the reflective structure opening 400, the current applied to the metal reflective layer 52 can be laterally distributed to the contact electrode 30 through the reflective structure opening 400, without accumulating at the reflective structure opening 400. In one embodiment, the current blocking portion 33 may be a multilayer film structure with alternating layers of insulators with different refractive indices, such as a distributed Bragg reflector (DBR). A distributed Bragg reflector (DBR) structure is formed by alternatingly stacking a plurality of first sublayers having a first refractive index and a plurality of second sublayers having a second refractive index, wherein the first refractive index is less than the second refractive index. For example, it can be formed by stacking SiO2 / TiO2 or SiO2 / Nb2O5 .
於一實施例中,電流阻擋部33包含小於或等於1000 nm的厚度T,但至少大於100 nm。當接觸電極30覆蓋電流阻擋部33時,接觸凸部303包含一階差h突出於接觸電極30之上表面30s,接觸凸部303之階差h大致與電流阻擋部33之厚度T相同,或是接觸凸部303之階差h與電流阻擋部33之厚度T之間包含一差值小於電流阻擋部33之厚度T的10%。於一實施例中,接觸電極30之平面部301所包含之一厚度與接觸電極30之接觸凸部303所包含之一厚度之間的厚度差小於平面部301所包含之厚度的10%。In one embodiment, the current blocking portion 33 includes a thickness T of less than or equal to 1000 nm, but at least greater than 100 nm. When the contact electrode 30 covers the current blocking portion 33, the contact protrusion 303 includes a step difference h protruding from the upper surface 30s of the contact electrode 30. The step difference h of the contact protrusion 303 is approximately the same as the thickness T of the current blocking portion 33, or the difference between the step difference h of the contact protrusion 303 and the thickness T of the current blocking portion 33 includes a value less than 10% of the thickness T of the current blocking portion 33. In one embodiment, the thickness difference between the thickness of the planar portion 301 of the contact electrode 30 and the thickness of the contact protrusion 303 of the contact electrode 30 is less than 10% of the thickness of the planar portion 301.
如第2圖及第4圖所示,第一絕緣結構60包含第一絕緣結構第一開口601位於第一凹陷區域E1以及第二凹陷區域E2上。第一絕緣結構60可以露出反射結構40之一側壁40s。於另一實施例中(圖未示),第一絕緣結構60可以包覆反射結構40之側壁40s。於另一實施例中,第一絕緣結構第一開口601所包含之一第一側壁601s與半導體平台M之第二斜面S2之間具有一最小距離Smax大於10微米以確保第一絕緣結構60包含一厚度以包覆反射結構40,避免蝕刻移除第一絕緣結構60以形成第一絕緣結構第一開口601時損傷反射結構40而降低反射結構40之反射率。第一延伸電極71通過第一絕緣結構第一開口601與露出於第一凹陷區域E1以及第二凹陷區域E2的第一半導體層21相接。As shown in Figures 2 and 4, the first insulating structure 60 includes a first opening 601 located in a first recessed region E1 and a second recessed region E2. The first insulating structure 60 may expose one sidewall 40s of the reflective structure 40. In another embodiment (not shown), the first insulating structure 60 may cover the sidewall 40s of the reflective structure 40. In another embodiment, a minimum distance Smax greater than 10 micrometers exists between a first sidewall 601s included in the first opening 601 of the first insulating structure and the second inclined surface S2 of the semiconductor platform M. This ensures that the first insulating structure 60 includes a thickness to cover the reflective structure 40, preventing damage to the reflective structure 40 and a reduction in the reflectivity of the reflective structure 40 when the first insulating structure 60 is etched away to form the first opening 601. The first extended electrode 71 is connected to the first semiconductor layer 21 exposed in the first recessed region E1 and the second recessed region E2 through the first opening 601 of the first insulating structure.
如第2圖所示,第一絕緣結構60連續地覆蓋金屬反射層52及連接層51的所有暴露的表面以保護金屬反射層52,例如金屬反射層52及連接層51的上表面和側表面。金屬反射層52及連接層51可以被封裝在第一絕緣結構60和反射結構40之間。於發明之一實施例中,通過形成第一絕緣結構60,可以避免金屬反射層52的反射率因為後續製程而劣化,並且可以抑制金屬反射層52中所包含的金屬元素的遷移。As shown in Figure 2, the first insulating structure 60 continuously covers all exposed surfaces of the metal reflective layer 52 and the connecting layer 51 to protect the metal reflective layer 52, such as the upper and side surfaces of the metal reflective layer 52 and the connecting layer 51. The metal reflective layer 52 and the connecting layer 51 can be encapsulated between the first insulating structure 60 and the reflective structure 40. In one embodiment of the invention, by forming the first insulating structure 60, the reflectivity of the metal reflective layer 52 can be prevented from deteriorating due to subsequent processes, and the migration of metal elements contained in the metal reflective layer 52 can be suppressed.
如第2圖所示,第一絕緣結構60包含第一絕緣結構第一開口601和第一絕緣結構第二開口602。第一絕緣結構第一開口601穿過反射結構40以暴露第一接觸第一區域CT1和第一接觸第二區域CT1’的第一半導體層21。第一絕緣結構第一開口601可以設置在第一凹陷區域 E1以及第二凹陷區域E2上,並且第一絕緣結構第二開口602位於第二接觸區域CT2的金屬反射層52之上。於發明之一實施例中,為了增加發光元件1之光取出效率,第一絕緣結構60包含一第一分散式布拉格反射器(DBR)結構,係由具有複數個非金屬氧化層和複數個金屬氧化層交替地堆疊所形成。非金屬氧化層的材料包含SiO2、SiN、SiOxNy、Si3N4。金屬氧化層的材料包含TiO2、Si3N4、Al2O3、TiN、AlN、ZrO2、TiAlN、TiSiN、HfO、TaO2、Nb2O5、或MgF2。例如,可通過SiO2/TiO2或SiO2/Nb2O5等層疊。為了改善第一絕緣結構60與第一延伸電極71、金屬反射層52之間的附著性,金屬反射層52可藉由包含銀(Ag)以外之金屬,例如鉑(Pt),與第一絕緣結構60之非金屬氧化層相接,例如SiO2,且第一絕緣結構60藉由金屬氧化層與第一延伸電極71相接,例如TiO2或Nb2O5。As shown in Figure 2, the first insulation structure 60 includes a first insulation structure first opening 601 and a first insulation structure second opening 602. The first insulation structure first opening 601 extends through the reflective structure 40 to expose the first semiconductor layer 21 of the first contact first region CT1 and the first contact second region CT1'. The first insulation structure first opening 601 may be disposed on the first recessed region E1 and the second recessed region E2, and the first insulation structure second opening 602 is located above the metal reflective layer 52 of the second contact region CT2. In one embodiment of the invention, to increase the light extraction efficiency of the light-emitting element 1, the first insulation structure 60 includes a first distributed Bragg reflector (DBR) structure, which is formed by alternating stacks of a plurality of non-metallic oxide layers and a plurality of metallic oxide layers. The materials of the non-metallic oxide layers include SiO₂ , SiN, SiOₓNy , and Si₃N₄ . The materials of the metallic oxide layers include TiO₂ , Si₃N₄ , Al₂O₃ , TiN, AlN, ZrO₂ , TiAlN, TiSiN, HfO , TaO₂ , Nb₂O₅ , or MgF₂ . For example, it can be achieved by stacking SiO₂ / TiO₂ or SiO₂ / Nb₂O₅ layers . To improve the adhesion between the first insulating structure 60, the first extended electrode 71, and the metal reflective layer 52, the metal reflective layer 52 can be connected to the non-metallic oxide layer of the first insulating structure 60 by means of a metal other than silver (Ag), such as platinum (Pt), for example, SiO 2 , and the first insulating structure 60 is connected to the first extended electrode 71 by means of a metal oxide layer, such as TiO 2 or Nb 2 O 5 .
於一實施例中,如第1圖所示,第一絕緣結構第二開口602與複數個反射結構開口400錯位設置,亦即第一絕緣結構第二開口602不與複數個反射結構開口400重疊。為了維持複數個反射結構開口400等間距排列的圖案,第一絕緣結構第二開口602包含一不規則的環形,複數個反射結構開口400為環形所包圍,其中第一絕緣結構第二開口602不與複數個反射結構開口400重疊。於另一實施例中,如第10A圖所示,第一絕緣結構第二開口602包含一矩形,複數個反射結構開口400為矩形所包圍,其中第一絕緣結構第二開口602係與複數個反射結構開口400重疊。於另一實施例中,如第10B圖所示,第一絕緣結構第二開口602包含一矩形,複數個反射結構開口400位於矩形以外的區域,其中第一絕緣結構第二開口602不與複數個反射結構開口400重疊。於另一實施例中,第10A圖及第10C圖例示之矩形可以變化為圓形、三角形、或規則或不規則的多邊形。In one embodiment, as shown in Figure 1, the second opening 602 of the first insulating structure is staggered with the plurality of reflective structure openings 400, that is, the second opening 602 of the first insulating structure does not overlap with the plurality of reflective structure openings 400. In order to maintain the pattern of the plurality of reflective structure openings 400 being arranged at equal intervals, the second opening 602 of the first insulating structure includes an irregular ring, and the plurality of reflective structure openings 400 are surrounded by the ring, wherein the second opening 602 of the first insulating structure does not overlap with the plurality of reflective structure openings 400. In another embodiment, as shown in Figure 10A, the second opening 602 of the first insulating structure comprises a rectangle, and a plurality of reflective structural openings 400 are enclosed by the rectangle, wherein the second opening 602 of the first insulating structure overlaps with the plurality of reflective structural openings 400. In another embodiment, as shown in Figure 10B, the second opening 602 of the first insulating structure comprises a rectangle, and a plurality of reflective structural openings 400 are located in the area outside the rectangle, wherein the second opening 602 of the first insulating structure does not overlap with the plurality of reflective structural openings 400. In another embodiment, the rectangle shown in Figures 10A and 10C can be varied into a circle, a triangle, or a regular or irregular polygon.
於一實施例中,如第1圖所示,第一絕緣結構第二開口602包含一網絡開口,具有一封閉曲線外輪廓,複數個反射結構開口400包含一第一部分4001位於封閉曲線外輪廓內以及一第二部分4002位於封閉曲線外輪廓外,其中第一部分4001及第二部分4002以六邊形排列的格子圖案佈置在半導體平台M上。於另一實施例中,如第10C圖所示,第一絕緣結構第二開口602包含一封閉曲線外輪廓,複數個反射結構開口400位於封閉曲線外輪廓外,且以六邊形排列的格子圖案佈置在半導體平台M上。In one embodiment, as shown in Figure 1, the second opening 602 of the first insulation structure includes a mesh opening having a closed curve outer contour. A plurality of reflective structure openings 400 include a first portion 4001 located within the closed curve outer contour and a second portion 4002 located outside the closed curve outer contour, wherein the first portion 4001 and the second portion 4002 are arranged in a hexagonal lattice pattern on the semiconductor platform M. In another embodiment, as shown in Figure 10C, the second opening 602 of the first insulation structure includes a closed curve outer contour, and a plurality of reflective structure openings 400 are located outside the closed curve outer contour and arranged in a hexagonal lattice pattern on the semiconductor platform M.
如第2圖及第4圖所示,第一延伸電極71可以設置在第一絕緣結構60上,並通過第一絕緣結構第一開口601延伸到第一接觸第一區域CT1和第一接觸第二區域CT1’的第一半導體層21上而接觸並電連接到第一半導體層21。在一實施例中,為了改善第一延伸電極71與第一半導體層21之間的接觸電阻特性,可以在第一延伸電極71和第一半導體層21之間設置一導電接觸層(圖未示)。導電接觸層可以包含氧化銦錫 (ITO)、鋅摻雜氧化銦錫(ZITO)、氧化鋅銦(ZIO)、氧化鎵銦(GIO)、氧化鋅錫(ZTO)、氟摻雜氧化錫(FTO)、鋁摻雜氧化鋅(AZO)、鎵摻雜的氧化鋅(GZO)、或氧化鋅鎂(Zn(1-x)MgxO,0≤x ≤1)等導電金屬氧化物。於一實施例中,於第一凹陷區域E1的上表面20b上及/或第二凹陷區域E2的上表面20b’上可設置一金屬接觸層(圖未示),金屬接觸層的上表面的一部分可以為第一接觸第一區域CT1及/或第一接觸第二區域CT1’。As shown in Figures 2 and 4, the first extended electrode 71 can be disposed on the first insulating structure 60 and extend through the first opening 601 of the first insulating structure to contact and electrically connect to the first semiconductor layer 21, which is in contact with the first contact area CT1 and the first contact area CT1'. In one embodiment, in order to improve the contact resistance characteristics between the first extended electrode 71 and the first semiconductor layer 21, a conductive contact layer (not shown) can be disposed between the first extended electrode 71 and the first semiconductor layer 21. The conductive contact layer may contain conductive metal oxides such as indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or zinc magnesium oxide (Zn (1-x) MgxO , 0≤x≤1). In one embodiment, a metal contact layer (not shown) may be provided on the upper surface 20b of the first recessed region E1 and/or the upper surface 20b' of the second recessed region E2. A portion of the upper surface of the metal contact layer may be a first contact with the first region CT1 and/or a first contact with the second region CT1'.
第二延伸電極72可以設置在第一絕緣結構60上,並且通過第一絕緣結構第二開口602延伸到金屬反射層52上而電連接第二半導體層23。The second extended electrode 72 can be disposed on the first insulating structure 60 and extend to the metal reflective layer 52 through the second opening 602 of the first insulating structure and be electrically connected to the second semiconductor layer 23.
於一實施例中,第一延伸電極71和第二延伸電極72可以設置在第一絕緣結構60上,由不同的材料形成,並且彼此間隔開。例如,第一延伸電極71和第二延伸電極72可以由包括以下各項中的至少一項的材料形成:鋁(Al)、金(Au)、鎢(W)、鉑(Pt)、銥(Ir)、銀(Ag)、銅(Cu)、鎳(Ni)、鈦(Ti)、鉻(Cr)和上述材料之合金。In one embodiment, the first extended electrode 71 and the second extended electrode 72 may be disposed on the first insulating structure 60, formed of different materials, and spaced apart from each other. For example, the first extended electrode 71 and the second extended electrode 72 may be formed of a material including at least one of the following: aluminum (Al), gold (Au), tungsten (W), platinum (Pt), iridium (Ir), silver (Ag), copper (Cu), nickel (Ni), titanium (Ti), chromium (Cr), and alloys of the above materials.
第二絕緣結構80包含位於第一延伸電極71上的第二絕緣結構第一開口801和位於第二延伸電極72上的第二絕緣結構第二開口802。第二絕緣結構第一開口801可以暴露第一延伸電極71,第二絕緣結構第二開口802可以暴露第二延伸電極72。The second insulation structure 80 includes a first opening 801 of the second insulation structure located on the first extended electrode 71 and a second opening 802 of the second insulation structure located on the second extended electrode 72. The first opening 801 of the second insulation structure can expose the first extended electrode 71, and the second opening 802 of the second insulation structure can expose the second extended electrode 72.
第一電極墊91可以通過第二絕緣結構第一開口801設置在第一延伸電極71上,第二電極墊92可以通過第二絕緣結構第二開口802設置在第二延伸電極72上。第一焊墊(圖未示)可以設置在第一電極墊91上,第二焊墊(圖未示)可以設置在第二電極墊92上。第一焊墊和第二焊墊可以由導電材料(例如,Sn或AuSn)形成。如第1圖所示,在俯視圖中,第一電極墊91可以與第一邊11相鄰,第二電極墊92可以與第二邊12相鄰。A first electrode pad 91 can be disposed on a first extended electrode 71 through a first opening 801 of a second insulation structure, and a second electrode pad 92 can be disposed on a second extended electrode 72 through a second opening 802 of a second insulation structure. A first solder pad (not shown) can be disposed on the first electrode pad 91, and a second solder pad (not shown) can be disposed on the second electrode pad 92. The first and second solder pads can be formed of a conductive material (e.g., Sn or AuSn). As shown in Figure 1, in a top view, the first electrode pad 91 can be adjacent to the first side 11, and the second electrode pad 92 can be adjacent to the second side 12.
第一電極墊91,及第二電極墊92包含金屬材料,例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)、銀(Ag)等金屬或上述材料之合金。第一電極墊91及第二電極墊92可由單個層或是多個層所組成。例如,第一電極墊91,或第二電極墊92可包括Ti/Au層、Ti/Pt/Au層、Cr/Au層、Cr/Pt/Au層、Ni/Au層、Ni/Pt/Au層、Cr/Al/Cr/Ni/Au層、或Ag/NiTi/TiW/Pt層。第一電極墊91及第二電極墊92可做為外部電源供電至第一半導體層21及第二半導體層23之電流路徑。於一實施例中,第一電極墊91及第二電極墊92各包含一厚度介於0.5微米~5微米之間。The first electrode pad 91 and the second electrode pad 92 comprise metallic materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), silver (Ag), or alloys thereof. The first electrode pad 91 and the second electrode pad 92 may consist of a single layer or multiple layers. For example, the first electrode pad 91 or the second electrode pad 92 may include a Ti/Au layer, a Ti/Pt/Au layer, a Cr/Au layer, a Cr/Pt/Au layer, a Ni/Au layer, a Ni/Pt/Au layer, a Cr/Al/Cr/Ni/Au layer, or an Ag/NiTi/TiW/Pt layer. The first electrode pad 91 and the second electrode pad 92 can serve as current paths for external power supply to the first semiconductor layer 21 and the second semiconductor layer 23. In one embodiment, the first electrode pad 91 and the second electrode pad 92 each include a layer with a thickness between 0.5 micrometers and 5 micrometers.
於一實施例中,絕緣層42、第一絕緣結構60及第二絕緣結構80設置在半導體結構20上,是作為發光元件1的保護膜及防靜電的層間絕緣膜。於一實施例中,作為絕緣膜,絕緣層42、第一絕緣結構60及第二絕緣結構80可以為一單層結構,包含金屬氧化物或金屬氮化物,例如可優選使用選自由矽(Si)、鈦(Ti)、鋯(Zr)、鈮(Nb)、鉭(Ta)、鋁(Al)構成的組中的至少一種氧化物或氮化物。於另一實施例中,絕緣層42、第一絕緣結構60及第二絕緣結構80包含不同折射率的兩種以上之材料交替堆疊以形成一分布式布拉格反射鏡(DBR)結構,選擇性地反射特定波長之光。例如,可通過SiO2、TiO2、Nb2O5或Al2O3等兩種或三種材料絕緣層堆疊形成高反射率的反射結構。例如以SiO2/TiO2或SiO2/Nb2O5等子層堆疊形成分布式布拉格反射鏡(DBR)結構時,分布式布拉格反射鏡結構的每一個子層被設計成活性層22發出的光的波長的四分之一的光學厚度的一或整數倍。分布式布拉格反射鏡(DBR)結構的每一個子層的光學厚度在λ/4的一或整數倍的基礎上可具有±30%的偏差。由於分布式布拉格反射鏡結構的每一個子層的光學厚度改變會影響到反射率,因此基於分布式布拉格反射鏡結構的光學厚度得到的絕緣層42、第一絕緣結構60及第二絕緣結構80中的每一個子層的物理厚度可利用電子束蒸鍍(E-beam evaporation)來形成,以穩定的控制絕緣層42、第一絕緣結構60及第二絕緣結構80中每一個子層的厚度。In one embodiment, the insulating layer 42, the first insulating structure 60, and the second insulating structure 80 are disposed on the semiconductor structure 20, serving as a protective film for the light-emitting element 1 and an interlayer insulating film for preventing static electricity. In one embodiment, as an insulating film, the insulating layer 42, the first insulating structure 60, and the second insulating structure 80 can be a single-layer structure comprising a metal oxide or a metal nitride, for example, preferably using at least one oxide or nitride selected from the group consisting of silicon (Si), titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), and aluminum (Al). In another embodiment, the insulating layer 42, the first insulating structure 60, and the second insulating structure 80 comprise two or more materials with different refractive indices stacked alternately to form a distributed Bragg reflector (DBR) structure that selectively reflects light of specific wavelengths. For example, a highly reflective reflective structure can be formed by stacking two or three insulating layers such as SiO2 , TiO2 , Nb2O5 , or Al2O3 . For example , when a distributed Bragg reflector (DBR ) structure is formed by stacking sublayers such as SiO2 / TiO2 or SiO2 / Nb2O5 , each sublayer of the distributed Bragg reflector structure is designed to be one or an integer multiple of the optical thickness of one-quarter of the wavelength of light emitted by the active layer 22. The optical thickness of each sublayer of the distributed Bragg reflector (DBR) structure can have a deviation of ±30% on a basis of one or an integer multiple of λ/4. Since the change in the optical thickness of each sublayer of the DBR structure affects the reflectivity, the physical thickness of each sublayer in the insulating layer 42, the first insulating structure 60, and the second insulating structure 80, obtained based on the optical thickness of the DBR structure, can be formed using electron beam evaporation to stably control the thickness of each sublayer in the insulating layer 42, the first insulating structure 60, and the second insulating structure 80.
第11圖係本發明一實施例之發光裝置2之示意圖。將前述實施例中的發光元件1以倒裝晶片之形式安裝於封裝基板50之第一墊片501及第二墊片502上。第一墊片501及第二墊片502之間藉由一包含絕緣材料之絕緣部53做電性絕緣。倒裝晶片安裝係將與電極墊形成面相對之成長基板側向上設為主要的光取出面,例如發光元件1之基板10的出光面10t係為發光元件1之主要的光取出面。為了增加發光裝置2之光取出效率,可於發光元件1之周圍設置一反射結構54。Figure 11 is a schematic diagram of a light-emitting device 2 according to an embodiment of the present invention. The light-emitting element 1 of the aforementioned embodiment is mounted as a flip chip on the first pad 501 and the second pad 502 of the packaging substrate 50. The first pad 501 and the second pad 502 are electrically insulated from each other by an insulating portion 53 containing insulating material. In flip chip mounting, the growth substrate facing upwards opposite the electrode pad formation surface is designated as the primary light extraction surface; for example, the light-emitting surface 10t of the substrate 10 of the light-emitting element 1 is the primary light extraction surface of the light-emitting element 1. To increase the light extraction efficiency of the light-emitting device 2, a reflective structure 54 can be provided around the light-emitting element 1.
第12圖係本發明一實施例之發光裝置3之示意圖。發光裝置3為一球泡燈,包括一燈罩612、一反射鏡604、一發光模組600、一燈座611、一散熱片614、一連接部616以及一電連接元件618。發光模組600包含一承載部606,以及複數個發光單元608位於承載部606上,其中複數個發光單元608可為前述實施例中的發光元件1或發光裝置2。Figure 12 is a schematic diagram of a light-emitting device 3 according to an embodiment of the present invention. The light-emitting device 3 is a bulb lamp, including a lampshade 612, a reflector 604, a light-emitting module 600, a lamp holder 611, a heat dissipation fin 614, a connecting part 616, and an electrical connection element 618. The light-emitting module 600 includes a support part 606, and a plurality of light-emitting units 608 are located on the support part 606, wherein the plurality of light-emitting units 608 may be the light-emitting element 1 or the light-emitting device 2 in the aforementioned embodiments.
第13圖係本發明一實施例之背光模組4的示意圖。背光模組4包括第一框架201、液晶顯示面板202、增亮膜310、光學模組430、發光模組組件500、以及第二框架700。發光模組組件500包括複數個前述實施例中的發光元件1或發光裝置2,以側光式(edge type)或直下式(direct type)的出光方式配置於發光模組組件500中。於一實施例中,背光模組4更包括波長轉換結構610,設置於發光模組組件500上。Figure 13 is a schematic diagram of a backlight module 4 according to an embodiment of the present invention. The backlight module 4 includes a first frame 201, a liquid crystal display panel 202, a brightness enhancement film 310, an optical module 430, a light-emitting module assembly 500, and a second frame 700. The light-emitting module assembly 500 includes a plurality of light-emitting elements 1 or light-emitting devices 2 as described in the aforementioned embodiments, arranged in the light-emitting module assembly 500 in an edge-type or direct-type light emission manner. In one embodiment, the backlight module 4 further includes a wavelength conversion structure 610 disposed on the light-emitting module assembly 500.
第14圖係本發明一實施例之顯示器5的示意圖。顯示器5包括LED發光板3000與電流源(未圖示)。支架2000用以支撐LED發光板3000。LED發光板3000包括複數個前述實施例中的發光元件1或發光裝置2中的任一種或背光模組4。於一實施例中,LED發光板3000包括複數個畫素單元。每一畫素單元包括複數個前述實施例中的發光元件1或發光裝置2以分別發出不同顏色,例如,每一畫素單元包括三個分別發出紅光、綠光、藍光的發光元件1或發光裝置2。Figure 14 is a schematic diagram of a display 5 according to an embodiment of the present invention. The display 5 includes an LED light-emitting panel 3000 and a current source (not shown). A bracket 2000 is used to support the LED light-emitting panel 3000. The LED light-emitting panel 3000 includes any one of the light-emitting elements 1 or light-emitting devices 2 in the aforementioned embodiments or a backlight module 4. In one embodiment, the LED light-emitting panel 3000 includes a plurality of pixel units. Each pixel unit includes a plurality of light-emitting elements 1 or light-emitting devices 2 in the aforementioned embodiments to emit different colors. For example, each pixel unit includes three light-emitting elements 1 or light-emitting devices 2 that emit red light, green light, and blue light respectively.
第15圖係本發明一實施例之發光裝置6之示意圖。於一實施例中,發光裝置6為用於汽車的LED燈泡,可以插接固定在汽車大燈總成的後殼上的安裝通孔中。發光裝置6包括用於近光燈發光的第一LED晶片4100或遠光燈發光的第二LED晶片4200 、長柱狀的燈柱4300、驅動電源電路板4400、用於散熱的散熱鰭片(圖未示)、用於散熱的風扇(圖未示)、用於罩護所述風扇的風扇罩(圖未示)、用於與車載電池電連接的電源線(圖未示),設置於電源線末端的插頭(圖未示)。發光裝置6中的第一LED晶片4100或第二LED晶片4200可以包含前述之發光元件1或發光裝置2之任一個或多個。Figure 15 is a schematic diagram of a light-emitting device 6 according to an embodiment of the present invention. In one embodiment, the light-emitting device 6 is an LED bulb for automobiles, which can be inserted and fixed into a mounting through hole on the rear cover of the automobile headlight assembly. The light-emitting device 6 includes a first LED chip 4100 for low beam illumination or a second LED chip 4200 for high beam illumination, a long columnar lamp post 4300, a driver power circuit board 4400, a heat dissipation fin (not shown), a heat dissipation fan (not shown), a fan cover (not shown) for protecting the fan, a power cord (not shown) for electrical connection with the vehicle battery, and a plug (not shown) disposed at the end of the power cord. The first LED chip 4100 or the second LED chip 4200 in the light-emitting device 6 may include one or more of the aforementioned light-emitting element 1 or light-emitting device 2.
第16圖係本發明一實施例之發光裝置7之示意圖。於一實施例中,發光裝置7可以為車用照明燈5000,可以被應用在日行燈、頭燈、尾燈、或方向燈。主照明燈5100在車用照明燈5000中可以是主發光燈,例如,在車用照明燈5000被利用為車前燈的情況下,主照明燈5100可以具有照亮車輛的前方的頭燈的功能。組合照明燈5200可以具有至少兩種功能。例如,在車輛用照明燈被利用為車前燈的情況下,組合照明燈5200可以執行日間行車燈(daytime running light;DRL)及方向指示燈的功能。主照明燈5100或組合照明燈5200可以包含前述之發光元件1或發光裝置2之任一個或多個。Figure 16 is a schematic diagram of a light-emitting device 7 according to an embodiment of the present invention. In one embodiment, the light-emitting device 7 can be an automotive lighting lamp 5000, which can be used as a daytime running light, headlight, taillight, or turn signal. The main lighting lamp 5100 can be the main light in the automotive lighting lamp 5000. For example, when the automotive lighting lamp 5000 is used as a headlight, the main lighting lamp 5100 can have the function of illuminating the front of the vehicle as a headlight. The combination lighting lamp 5200 can have at least two functions. For example, when the automotive lighting lamp is used as a headlight, the combination lighting lamp 5200 can perform the functions of a daytime running light (DRL) and a turn signal. The main lighting 5100 or the combination lighting 5200 may include one or more of the aforementioned light-emitting elements 1 or light-emitting devices 2.
上述一些實施例的部件,以便在本揭露所屬技術領域中具有通常知識者可以更理解本揭露實施例的觀點。在本揭露所屬技術領域中具有通常知識者應該理解,他們能以本揭露實施例為基礎,設計或修改其他製程和結構以達到與在此介紹的實施例相同之目的及/或優勢。在本揭露所屬技術領域中具有通常知識者也應該理解到,此類等效的結構並無悖離本揭露的精神與範圍,且他們能在不違背本揭露之精神和範圍之下,做各式各樣的改變、取代和替換。因此,本揭露之保護範圍當視後附之申請專利範圍所界定者為準。另外,雖然本揭露已以數個較佳實施例揭露如上,然其並非用以限定本揭露。The components of the above embodiments are provided to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purpose and/or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended patent claims. Furthermore, although this disclosure has disclosed several preferred embodiments as described above, it is not intended to limit this disclosure.
整份說明書對特徵、優點或類似語言的引用,並非意味可以利用本揭露實現的所有特徵和優點應該或者可以在本揭露的任何單個實施例中實現。相對地,涉及特徵和優點的語言被理解為其意味著結合實施例描述的特定特徵、優點或特性包括在本揭露的至少一個實施例中。因而,在整份說明書中對特徵和優點以及類似語言的討論可以但不一定代表相同的實施例。References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable using this disclosure should or can be achieved in any single embodiment of this disclosure. Instead, language relating to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, discussions of features and advantages, as well as similar language, throughout this specification may, but do not necessarily, represent the same embodiments.
再者,在一個或多個實施例中,可以任何合適的方式組合本揭露的所描述的特徵、優點和特性。根據本文的描述,相關領域的技術人員將意識到,可在沒有特定實施例的一個或多個特定特徵或優點的情況下實現本揭露。在其他情況下,在某些實施例中可辨識附加的特徵和優點,這些特徵和優點可能不存在於本揭露的所有實施例中。Furthermore, in one or more embodiments, the features, advantages, and characteristics described herein can be combined in any suitable manner. Based on the description herein, those skilled in the art will recognize that this disclosure can be implemented without any particular feature or advantage of a particular embodiment. In other cases, additional features and advantages may be identified in some embodiments that may not be present in all embodiments of this disclosure.
1:發光元件1: Light-emitting element
2:發光裝置2: Light-emitting device
3:發光裝置3: Light-emitting device
4:背光模組4: Backlight Module
5:顯示器5: Display
6:發光裝置6: Light-emitting device
7:發光裝置7: Light-emitting device
10:基板10:Substrate
10s:上表面10s: Top surface
10t:出光面10t: Emitting surface
11:第一邊11: First side
12:第二邊12: Second side
13:第三邊13: Third side
14:第四邊14: Fourth side
20:半導體結構20: Semiconductor Structure
20b:第一凹陷區域E1的上表面20b: Upper surface of the first recessed region E1
20b’:第二凹陷區域E2的上表面20b’: Upper surface of the second recessed region E2
20t:半導體平台M的上表面20t: Upper surface of semiconductor platform M
21:第一半導體層21: First Semiconductor Layer
21t:第一上表面21t: First upper surface
22:活性層22: Active layer
23:第二半導體層23: Second Semiconductor Layer
23H:高阻值區23H: High resistance region
23L:低阻值區23L: Low resistance region
23t:第二上表面23t: Second upper surface
231:第二半導體層凹部231: Second semiconductor layer recess
201:第一框架201: First Framework
202:液晶顯示面板202: LCD display panel
2000:支架2000: Bracket
30:接觸電極30: Contact electrode
30s:上表面30s: Top surface
300:接觸開口300: Contact opening
300b:第三底部300b: Third bottom
300t:第三頂部300t: Third Top
302:接觸凹部302: Contact Recess
303:接觸凸部303: Contact protrusion
301:平面部301: Planar Section
33:電流阻擋部33: Current blocking section
33e:側面33e: Side view
310:增亮膜310: Brightening film
3000:發光板3000: Light-emitting panel
40:反射結構40: Reflective Structure
40s:側壁40s: Sidewall
400:反射結構開口400: Reflective structure opening
4001:第一部分4001: Part One
4002:第二部分4002: Part Two
41:絕緣反射鏡41: Insulating reflector
410:第一反射結構開口410: First reflective structure opening
41t:第一頂部41t: First top
410b:第一底部410b: First bottom
420:第二反射結構開口420: Second reflection structure opening
420t:第二頂部420t: Second Top
420b:第二底部420b: Second bottom
42:絕緣層42: Insulation Layer
42s:絕緣層上表面42s: Insulation layer upper surface
4100:第一LED晶片4100: First LED chip
4200:第二LED晶片4200: Second LED chip
430:光學模組430: Optical Module
4300:長柱狀的燈柱4300: Long, columnar lamppost
4400:驅動電源電路板4400: Driver Power Circuit Board
50:封裝基板50: Packaging substrate
51:連接層51: Connector Layer
52:金屬反射層52: Metal reflective layer
53:絕緣部53: Section on Separation
54:反射結構54: Reflective Structure
500:發光模組組件500: Light-emitting module assembly
501:第一墊片501: First pad
502:第二墊片502: Second pad
5000:車用照明燈5000: Automotive lights
5100:主照明燈5100: Main Lighting
5200:組合照明燈5200: Combination Lighting
60:第一絕緣結構60: First Insulation Structure
600:發光模組600: Light-emitting module
601:第一絕緣結構第一開口601: First opening of the first insulation structure
601s:第一側壁601s: First sidewall
602:第一絕緣結構第二開口602: First insulation structure, second opening
604:反射鏡604: Mirror
606:承載部606: Load-bearing section
608:發光單元608: Light-emitting unit
610:波長轉換結構610: Wavelength conversion structure
611:燈座611: Lamp stand
612:燈罩612: Lampshade
614:散熱片614: Heat dissipation plate
616:連接部616: Connecting part
618:電連接元件618: Electrical connection components
71:第一延伸電極71: First extended electrode
711:第一金屬反射層711: First Metal Reflective Layer
711e:金屬端部711e: Metal end
72:第二延伸電極72: Second extended electrode
700:第二框架700: Second Frame
80:第二絕緣結構80: Second insulation structure
801:第二絕緣結構第一開口801: First opening of the second insulation structure
802:第二絕緣結構第二開口802: Second opening of the second insulation structure
91:第一電極墊91: First electrode pad
92:第二電極墊92: Second electrode pad
B1:第一邊界B1: First Boundary
B2:第二邊界B2: Second Boundary
CT1:第一接觸第一區域CT1: First contact, first area
CT1’:第一接觸第二區域CT1’: First contact with the second area
CT2:第二接觸區域CT2: Second contact area
D1:第一最短距離D1: First shortest distance
D2:第二最短距離D2: Second shortest distance
E1:第一凹陷區域E1: First Depression Region
E2:第二凹陷區域E2: Second Depression Region
e1:第一側邊e1: First side
e2:第二側邊e2: Second side
e3:第三側邊e3: Third side
e3’:第三側面e3’: Third side
H:階差H: grade difference
h:階差h: grade difference
M:半導體平台M: Semiconductor Platform
Smax:最小距離Smax: Minimum distance
S1:第一斜面S1: First inclined plane
S2:第二斜面S2: Second inclined plane
T:厚度T: Thickness
W:最小寬度W: Minimum Width
W1:第一開口寬度W1: First opening width
W2:第二開口寬度W2: Second opening width
W3:第三開口寬度W3: Third opening width
W4:第四寬度W4: Fourth width
以下將配合所附圖式詳述本揭露實施例。應注意的是,各種特徵部件並未按照比例繪製且僅用以說明例示。事實上,元件的尺寸可能經放大或縮小,以清楚地表現出本揭露實施例的技術特徵。The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the various feature components are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the components may be enlarged or reduced to clearly show the technical features of the embodiments of this disclosure.
第1圖係本發明一實施例所揭示之一發光元件1的俯視圖。Figure 1 is a top view of one of the light-emitting elements 1 disclosed in an embodiment of the present invention.
第2圖係沿著第1圖之切線L-L’的剖面圖。Figure 2 is a cross-sectional view along the tangent line L-L’ of Figure 1.
第3圖係第1圖用虛線表示之區域A的部分放大圖。Figure 3 is a magnified view of area A, which is represented by the dashed line in Figure 1.
第4圖係本發明一實施例所揭示之沿著第3圖之切線X-X’的剖面圖。Figure 4 is a cross-sectional view along the tangent X-X’ of Figure 3, as shown in an embodiment of the present invention.
第5A圖~第5D圖係本發明一實施例所揭示之製造發光元件1之反射結構開口的方法的剖視圖。Figures 5A to 5D are cross-sectional views of a method for manufacturing a reflective structure opening of a light-emitting element 1 as disclosed in an embodiment of the present invention.
第6圖係本發明一實施例所揭示之反射結構開口的剖面圖。Figure 6 is a cross-sectional view of the opening of the reflective structure disclosed in an embodiment of the present invention.
第7圖係本發明一實施例所揭示之反射結構開口的剖面圖。Figure 7 is a cross-sectional view of the opening of the reflective structure disclosed in an embodiment of the present invention.
第8圖係本發明一實施例所揭示之反射結構開口的剖面圖。Figure 8 is a cross-sectional view of the reflective structure opening disclosed in an embodiment of the present invention.
第9圖係本發明一實施例所揭示之反射結構開口的剖面圖。Figure 9 is a cross-sectional view of the opening of the reflective structure disclosed in an embodiment of the present invention.
第10A圖~第10C圖係本發明一實施例所揭示之發光元件1的部分俯視圖。Figures 10A to 10C are partial top views of the light-emitting element 1 disclosed in an embodiment of the present invention.
第11圖係為依本發明一實施例之發光裝置2之示意圖。Figure 11 is a schematic diagram of a light-emitting device 2 according to an embodiment of the present invention.
第12圖係為依本發明一實施例之發光裝置3之示意圖。Figure 12 is a schematic diagram of a light-emitting device 3 according to an embodiment of the present invention.
第13圖係為依本發明一實施例之背光模組4之示意圖。Figure 13 is a schematic diagram of a backlight module 4 according to an embodiment of the present invention.
第14圖係為依本發明一實施例之顯示器5之示意圖。Figure 14 is a schematic diagram of a display 5 according to an embodiment of the present invention.
第15圖係為依本發明一實施例之發光裝置6之示意圖。Figure 15 is a schematic diagram of a light-emitting device 6 according to an embodiment of the present invention.
第16圖係為依本發明一實施例之發光裝置7之示意圖。Figure 16 is a schematic diagram of a light-emitting device 7 according to an embodiment of the present invention.
無without
1:發光元件 1: Light-emitting element
10:基板 10:Substrate
10s:上表面 10s: Top surface
10t:出光面 10t: Polished surface
11:第一邊 11: First side
12:第二邊 12: Second side
20:半導體結構 20: Semiconductor Structure
20b:第一凹陷區域E1的上表面 20b: Upper surface of the first recessed region E1
20t:半導體平台M的上表面 20t: Upper surface of semiconductor platform M
21:第一半導體層 21: First Semiconductor Layer
21t:第一上表面 21t: First upper surface
22:活性層 22: Active layer
23:第二半導體層 23: Second Semiconductor Layer
23t:第二上表面 23t: Second upper surface
30:接觸電極 30: Contacting the electrode
40:反射結構 40: Reflective Structure
400:反射結構開口 400: Reflective structure opening
41:絕緣反射鏡 41: Insulating reflector
42:絕緣層 42: Insulation Layer
51:連接層 51: Connector Layer
52:金屬反射層 52: Metal Reflective Layer
60:第一絕緣結構 60: First Insulation Structure
601:第一絕緣結構第一開口 601: First opening of the first insulation structure
602:第一絕緣結構第二開口 602: First insulation structure, second opening
71:第一延伸電極 71: First Extended Electrode
72:第二延伸電極 72: Second Extended Electrode
80:第二絕緣結構 80: Second Insulation Structure
801:第二絕緣結構第一開口 801: First opening of the second insulation structure
802:第二絕緣結構第二開口 802: Second opening in the second insulation structure
91:第一電極墊 91: First electrode pad
92:第二電極墊 92: Second electrode pad
B1:第一邊界 B1: First Boundary
CT1:第一接觸第一區域 CT1: First Contact, First Area
CT2:第二接觸區域 CT2: Second Contact Area
E1:第一凹陷區域 E1: First depression region
M:半導體平台 M: Semiconductor Platform
S1:第一斜面 S1: First inclined plane
S2:第二斜面 S2: Second inclined plane
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW112122981A TWI911541B (en) | 2023-06-19 | Light-emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW112122981A TWI911541B (en) | 2023-06-19 | Light-emitting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW202501851A TW202501851A (en) | 2025-01-01 |
| TWI911541B true TWI911541B (en) | 2026-01-11 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230165040A1 (en) | 2021-11-19 | 2023-05-25 | Samsung Display Co., Ltd. | Display apparatus |
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230165040A1 (en) | 2021-11-19 | 2023-05-25 | Samsung Display Co., Ltd. | Display apparatus |
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