CN1110065C - Method for automatically aligning grid cap to grid foot of T-shaped grid of smeicondctor device - Google Patents
Method for automatically aligning grid cap to grid foot of T-shaped grid of smeicondctor device Download PDFInfo
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- CN1110065C CN1110065C CN00105221A CN00105221A CN1110065C CN 1110065 C CN1110065 C CN 1110065C CN 00105221 A CN00105221 A CN 00105221A CN 00105221 A CN00105221 A CN 00105221A CN 1110065 C CN1110065 C CN 1110065C
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- photoresist
- grid
- window
- upper strata
- silicon nitride
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 72
- 238000005260 corrosion Methods 0.000 claims abstract description 16
- 230000007797 corrosion Effects 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 238000012545 processing Methods 0.000 claims abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 43
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 34
- 239000011248 coating agent Substances 0.000 claims description 26
- 238000000576 coating method Methods 0.000 claims description 26
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- 239000003292 glue Substances 0.000 claims description 12
- 238000003384 imaging method Methods 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 8
- 238000005036 potential barrier Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 12
- 230000002146 bilateral effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 10
- 239000010410 layer Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 241000216843 Ursus arctos horribilis Species 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000010923 batch production Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000001015 X-ray lithography Methods 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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Abstract
The present invention discloses a method for processing a T-shaped grid for automatically aligning a grid cap to a grid foot of a semiconductor device. In the method, general technical equipment is adopted, a bilayer photoresist is adopted, and the medium with a rapid corrosion speed rate is removed after reaction ions are etched by utilizing the characteristic of the large difference of the corrosion speed rates between two media. A grid window is composed of the medium with a low corrosion speed rate and the photoresist. The grid window is photoetched for one time without alignment. The bilateral symmetry T-shaped grid with a grid cap automatically aligning to a grid foot is obtained after the grid window is peeled, and the shortest grid length can be 0.1 mu m. The T-shaped grid has the advantages of reducing plate-making precision, difficulty in photoetching and processing cost. The present invention is particularly suitable for researching and developing a large wafer semiconductor device which is above 2 inches and can be popularized for application.
Description
Technical field
The present invention relates to a kind of T shape grid making method of semiconductor device, be specially adapted to the self aligned T shape grate processing technology technology of GaAs (GaAs) semiconductor device and monolithic integrated circuit grid cover thereof and grid foot.
Background technology
In GaAs semiconductor device and monolithic integrated circuit thereof, need to improve the performance of device and circuit with T shape grid, be a critical process.Drop into a large amount of manpower and financial resources from the eighties abroad, be engaged in the equipment and the technology research of microfabrication, develop multiple process technology, as: electron beam lithography, projection lithography, the X-ray lithography method is assembled electron beam and is not had mask method etc.Wherein use to such an extent that be the electron beam direct photoetching process the most widely.It utilizes two-layer above photoresist, and twice contraposition photoetching obtains T shape window on glue, through evaporated metal, obtain T shape grid after peeling off.It can produce the following T shape grid of 0.1 μ m.But the equipment complexity, costliness, processing time consuming, cost height.
A kind of semi-conductive T shape grid making method is disclosed in China Patent No. 96104462.4, " the T shape grid making method of semiconductor device ", the grid cover of semiconductor device and grid are to adopt secondary mask alignment to form enough, owing to adopt the common process device fabrication, the alignment difficulty is bigger, thereby the batch process of maturity and applying is restricted.
Summary of the invention
Order of the present invention have be to avoid the weak point in the above-mentioned background technology and provide a kind of need not expensive electron beam exposure apparatus, employing common process equipment photolithographic fabrication semiconductor device grid cover and the self aligned T shape grid making method of grid foot, and this method also to have grid metallization thickness thicker, little and the easy operation of technology difficulty, the rate of finished products height, processing cost is low, the thickness of grid is easy to characteristics such as control, can make the T shape grid of 0.1 μ m especially.
The object of the present invention is achieved like this, and the manufacturing procedure of processing that it comprises has:
Deposit one deck silicon nitride 2 films are coated with one deck upper strata photoresist 3 on silicon nitride 2 films on GaAs 1 substrate, are coated with one deck lower floor photoresist 4 on the upper strata photoresist 3;
Be placed on lower floor's photoresist 4 with a mask, the contraposition exposure imaging, exposure imaging goes out approximate rectangular photoresist window on lower floor's photoresist 4;
Large area exposure develops, be positioned on the upper strata photoresist 3 window on lower floor's photoresist 4 under locate exposure imaging and go out the big photoresist window of approximate rectangular size than the window on the lower floor photoresist 4, expose the silicon nitride 2 of glue window bottom;
Deposit one layer dielectric 5 in lower floor's photoresist 4 upper and lower layer photoetching glue 4 windows and upper strata photoresist 3 windows, deielectric-coating 5 deposition thicknesses are 0.1 μ m to 1.0 μ m; Deielectric-coating 5 and silicon nitride 2 on the silicon nitride 2 of bottom in deielectric-coating 5 on the reactive ion etching lower floor photoresist 4 and upper strata photoresist 3, lower floor's photoresist 4 windows obtain the narrow window that size has been dwindled on silicon nitride 2 films of window bottom and deielectric-coating 5; Get rid of all deielectric-coating 5 with the hydrofluoric acid corrosive liquid, stay silicon nitride 2 films; The corrosion rate difference of silicon nitride 2 and deielectric-coating 5 is big, and corrosion is than being 1: 20;
After GaAs 1 corrosion grooving, vertical evaporation barrier metal film 6 on 1 of GaAs, peel off the potential barrier metal film 6 on upper strata photoresist 3 on the GaAs 1, lower floor's photoresist 4 and upper strata photoresist 3, the lower floor's photoresist 4, obtain the self aligned T shape grid of grid cover and grid foot.
The present invention also comprises following manufacturing procedure of processing:
Deposit one layer thickness is silicon nitride 2 films of 500 to 4000 on GaAs of the present invention (GaAs) 1 substrate, and the thickness of coating layer photoetching glue 3, lower floor's photoresist 4 on silicon nitride 2 films is respectively 3000 to 15000 .
The temperature that hydrofluoric acid of the present invention is removed deielectric-coating 5 employings is 20 ℃ to 80 ℃.
The present invention compares background technology following advantage:
(1) the electron beam lithography machine of the present invention's costliness of no use, but, adopt the filled media film with common process equipment, technologies such as reactive ion etching are made the long controllable T shape grid of grid, greatly reduce processing cost.
(2) the present invention adopts silicon nitride (Si
3N
4) 2 and deielectric-coating 5 two-layered mediums, utilize the big characteristic of two media corrosion rate difference (corrosion was than about 1: 20), after the reactive ion etching, remove the fast medium of corrosion rate, constitute the grid window, peel off grid cover of back acquisition and the autoregistration of grid foot, symmetrical T shape grid by glue and ground floor medium, do not need the contraposition alignment, greatly reduce the photoetching difficulty, make the rate of finished products height, processing cost is low.
(3) the grid metal thickness of the T shape grid potential barrier metal film 6 of manufacturing of the present invention is thicker, helps the raising of device performance.
(4) the T shape grid of manufacturing of the present invention are located in silicon nitride (Si
3N
4) on 2 media,, can not lodge satisfactory mechanical property though the grid metal thickness is thicker yet.
(5) the present invention can use thicker mask, obtains very thin grizzly bar, greatly reduces plate-making precision and photoetching difficulty, the little and easy operation of technology difficulty, and the utmost point has popularizing value.
(6) the present invention can be used for the batch process of big circular slice semiconductor device more than 2 inches, the production efficiency height.
Description of drawings
Fig. 1 is deposit silicon nitride (Si of the present invention
3N
4) 2 and be coated with the process structure schematic diagram of twice upper strata photoresist 3, lower floor's photoresist 4.
Fig. 2 is the process structure schematic diagram after resist exposure of the present invention develops.
Fig. 3 is the process structure schematic diagram behind the deposition dielectric film 5 of the present invention.
Fig. 4 is the process structure schematic diagram after the reactive ion etching of the present invention.
Fig. 5 is the process structure schematic diagram after the present invention removes deielectric-coating 5.
Fig. 6 is evaporated metal of the present invention, peel off the structural representation of back T shape grid.
Embodiment
Referring to figs. 1 through Fig. 6, the present invention takes following procedure of processing:
(1) utilizes PECVD type deposit stove general on market deposit one deck silicon nitride (Si on GaAs (GaAs) 1 substrate
3N
4) 2 films, film thickness is 400 to 4000 , the Si of embodiment deposit
3N
4Film thickness is 2500 , adopts conventional method to handle the front of GaAs slice, thin piece then, at first at Si
3N
4Be coated with one deck upper strata photoresist 3 on the film, thickness is 3000 to 15000 , and embodiment upper strata photoresist 3 adopts the commercially available stratotype photoresist of going up, and the thickness of gluing is 1 micron (1 μ m).Be coated with one deck lower floor photoresist 4 then on photoresist 3, thickness is 3000 to 15000 , and embodiment photoresist 4 adopts commercially available stratotype photoresist down, and the thickness of gluing is 6000 , and with drying by the fire before the commercially available general baking oven, pre-bake temperature is 100 ℃, and the time is 15 minutes.(2) be placed on lower floor's photoresist 4 with a mask, the contraposition exposure imaging, exposure imaging goes out approximate rectangular photoresist window on lower floor's photoresist 4.Embodiment adopts the wide mask of 1 μ m, after the contraposition on the rotine exposure machine 10 seconds of exposure, be placed on again in Tetramethylammonium hydroxide equals 1: 3 than water the developer solution and developed 1 minute, on lower floor's photoresist 4, obtain approximate 1 a μ m photoresist window.
Large area exposure develops, and exposure imaging goes out the approximate rectangular photoresist window bigger than lower floor photoresist 4 sizes on the upper strata photoresist 3, exposes the silicon nitride (Si of glue window bottom
3N
4) 2.Embodiment with common floodlight to upper strata photoresist 3 large area exposures 5 minutes, be placed on again in Tetramethylammonium hydroxide equals 1: 3 than water the developer solution and developed 1 minute, at last with drying by the fire behind a conventional oven, back baking temperature is 100 ℃, time is to carry out post bake in 15 minutes, on upper strata photoresist 3, obtain a photoresist window bigger slightly, expose the silicon nitride (Si of glue window bottom simultaneously than lower floor photoresist 4 sizes
3N
4) 2.
(3) utilizing PECVD type deposit stove general on the market deposit one layer dielectric 5, deielectric-coating deposition thickness in lower floor's photoresist 4, lower floor's photoresist 4 windows and upper strata photoresist 3 windows again is 0.1 μ m to 1.0 μ m, and embodiment deielectric-coating 5 grows Si0
2Film, deposit dielectric thickness are 5000 .
(4) adopt bottom silicon nitride (Si in deielectric-coating 5 on the commercially available general reactive ion etching machine reactive ion etching lower floor photoresist 4 and upper strata photoresist 3, lower floor's photoresist 4 windows
3N
4) deielectric-coating 5 and silicon nitride 2 on 2, the silicon nitride (Si in the window bottom
3N
4) obtain the narrow window that size has been dwindled on 2 films and the deielectric-coating 5.
(5) get rid of all deielectric-coating 5 with the hydrofluoric acid corrosive liquid, stay silicon nitride 2 films, obtain the window that upper and lower layer photoetching glue 3,4 and silicon nitride 2 films are formed.The temperature that hydrofluoric acid is removed deielectric-coating 5 employings is 20 ℃ to 80 ℃.It is 40 ℃ hydrofluoric acid that embodiment adopts temperature, and etching time 1 minute is removed all deielectric-coating 5.Embodiment adopts silicon nitride 2 and deielectric-coating 5 two-layered mediums, utilize the big characteristic of this two media corrosion rate difference (corrosion than be 1: 20), after reactive ion etching, behind the fast deielectric-coating 5 of removal corrosion rate, constitute the grid window by upper and lower layer photoetching glue 3,4 and silicon nitride 2
(6) to GaAs 1 corrosion grooving, use commercially available electron beam evaporation platform to go up vertical evaporation barrier metal film 6 then 1 of GaAs (GaAs), peel off the potential barrier metal film 6 on the upper and lower layer photoetching glue 3,4 and upper and lower layer photoetching glue 3,4 on the GaAs 1, stay the potential barrier metal film 6 in the window, obtain the autoregistration of grid cover and grid foot, symmetrical T shape grid.Potential barrier metal film 6 is made of titanium (Ti), platinum (Pt), gold (Au) three-layer metal,
The thickness titanium (Ti) of embodiment potential barrier metal film 6 is 1000 , and platinum (Pt) is 2000 , and gold (Au) is 7000 .Therefore the grid metal thickness of T shape grid potential barrier metal film 6 is thicker, helps improving device performance, and T shape grid are located on silicon nitride 2 media, though the grid metal thickness is thicker, also can not lodge, and good mechanical properties is arranged.The present invention can use thicker mask, obtains very thin grizzly bar, reduces plate-making precision and photoetching difficulty greatly, is convenient to produce in batches, is applicable to the development and the production of big circular slice semiconductor device more than 2 inches, enhances productivity.
Claims (3)
1. the self aligned T shape grid making method of semiconductor device grid cover and grid foot is characterized in that the procedure of processing that it comprises has:
Deposit one deck silicon nitride (2) film on GaAs (1) substrate is coated with one deck lower floor photoresist (3) on silicon nitride (2) film, is coated with one deck upper strata photoresist (4) on lower floor's photoresist (3);
Be placed on the upper strata photoresist (4) with a mask, contraposition exposure imaging, upper strata photoresist (4) are gone up exposure imaging and are gone out approximate rectangular photoresist window;
Large area exposure develops, be positioned on lower floor's photoresist (3) window on the upper strata photoresist (4) under locate exposure imaging and go out the approximate rectangular big photoresist window of the size than the window on the upper strata photoresist (4), expose the silicon nitride (2) of glue window bottom;
Go up at upper strata photoresist (4), deposit one layer dielectric (5) in upper strata photoresist (4) window and lower floor's photoresist (3) window, deielectric-coating (5) deposition thickness is 0.1 μ m to 1.0 μ m;
Bottom silicon nitride (2) is gone up deielectric-coating (5) and silicon nitride (2) in deielectric-coating (5) on the reactive ion etching upper strata photoresist (4) and upper strata photoresist (4), lower floor's photoresist (3) window, obtains the narrow window that size has been dwindled on silicon nitride (2) film bottom window and the deielectric-coating (5);
Get rid of all deielectric-coating (5) with the hydrofluoric acid corrosive liquid, stay silicon nitride (2) film; The corrosion rate difference of silicon nitride (2) and deielectric-coating (5) is big, and corrosion is than being 1: 20;
After GaAs (1) corrosion grooving, vertical evaporation barrier metal film (6) on GaAs (1) sheet, peel off the potential barrier metal film (6) on the last upper strata photoresist (4) of GaAs (1), lower floor's photoresist (3) and upper strata photoresist (4), the lower floor's photoresist (3), obtain the self aligned T shape grid of grid cover and grid foot.
2. semiconductor device grid cover according to claim 1 and the self aligned T shape grid making method of grid foot, it is characterized in that deposit one layer thickness is silicon nitride (2) film of 500 to 4000 on GaAs (1) substrate, the thickness that is coated with lower floor's photoresist (3), upper strata photoresist (4) on silicon nitride (2) film is respectively 3000 to 15000 .
3. semiconductor device grid cover according to claim 1 and 2 and the self aligned T shape grid making method of grid foot is characterized in that it is 20 ℃ to 80 ℃ that hydrofluoric acid is removed the temperature of deielectric-coating (5) employing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN00105221A CN1110065C (en) | 2000-04-05 | 2000-04-05 | Method for automatically aligning grid cap to grid foot of T-shaped grid of smeicondctor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN00105221A CN1110065C (en) | 2000-04-05 | 2000-04-05 | Method for automatically aligning grid cap to grid foot of T-shaped grid of smeicondctor device |
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| Publication Number | Publication Date |
|---|---|
| CN1273434A CN1273434A (en) | 2000-11-15 |
| CN1110065C true CN1110065C (en) | 2003-05-28 |
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|---|---|---|---|
| CN00105221A Expired - Fee Related CN1110065C (en) | 2000-04-05 | 2000-04-05 | Method for automatically aligning grid cap to grid foot of T-shaped grid of smeicondctor device |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7413942B2 (en) * | 2004-01-29 | 2008-08-19 | Rohm And Haas Electronic Materials Llc | T-gate formation |
| KR100647459B1 (en) * | 2005-11-29 | 2006-11-23 | 한국전자통신연구원 | Method for manufacturing tee or gamma gate electrode |
| CN101251713B (en) * | 2008-04-07 | 2010-11-10 | 中国电子科技集团公司第十三研究所 | Method for deep-UV lithography making T type gate |
| US7943465B2 (en) * | 2009-01-26 | 2011-05-17 | Semiconductor Components Industries, Llc | Method for manufacturing a semiconductor component |
| CN102110738B (en) * | 2009-12-25 | 2013-04-24 | 华东光电集成器件研究所 | Method for manufacturing double-sided phase-sensitive detector (PSD) device |
| JP5979495B2 (en) * | 2013-03-19 | 2016-08-24 | Ｓｈマテリアル株式会社 | Manufacturing method of semiconductor device mounting substrate |
| CN105789037B (en) * | 2016-03-18 | 2021-03-02 | 中国电子科技集团公司第五十五研究所 | Preparation method of small-size gate of microwave millimeter wave chip |
| CN107393959A (en) * | 2017-07-07 | 2017-11-24 | 西安电子科技大学 | GaN hyperfrequencies device and preparation method based on sag |
| CN112645276B (en) * | 2020-03-06 | 2024-02-09 | 腾讯科技（深圳）有限公司 | Indium column and preparation method thereof |
| CN112614777A (en) * | 2020-12-18 | 2021-04-06 | 江苏能华微电子科技发展有限公司 | Self-alignment method and device for T-shaped gate metal lower gate channel opening |
| CN112713084A (en) * | 2020-12-29 | 2021-04-27 | 中国科学院微电子研究所 | Method for manufacturing semiconductor structure |
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|---|---|---|---|---|
| US4599790A (en) * | 1985-01-30 | 1986-07-15 | Texas Instruments Incorporated | Process for forming a T-shaped gate structure |
| EP0650185A1 (en) * | 1993-10-18 | 1995-04-26 | France Telecom | Method of manufacturing self-aligned conducting contacts for electronic components |
| CN1112288A (en) * | 1995-02-21 | 1995-11-22 | 中国科学院微电子中心 | Method for manufacturing T-shaped gate on semiconductor surface |
| CN1164760A (en) * | 1996-05-03 | 1997-11-12 | 电子工业部第十三研究所 | T shape grid making method for semiconductor device |
| US5688704A (en) * | 1995-11-30 | 1997-11-18 | Lucent Technologies Inc. | Integrated circuit fabrication |
-
2000
- 2000-04-05 CN CN00105221A patent/CN1110065C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4599790A (en) * | 1985-01-30 | 1986-07-15 | Texas Instruments Incorporated | Process for forming a T-shaped gate structure |
| EP0650185A1 (en) * | 1993-10-18 | 1995-04-26 | France Telecom | Method of manufacturing self-aligned conducting contacts for electronic components |
| CN1112288A (en) * | 1995-02-21 | 1995-11-22 | 中国科学院微电子中心 | Method for manufacturing T-shaped gate on semiconductor surface |
| US5688704A (en) * | 1995-11-30 | 1997-11-18 | Lucent Technologies Inc. | Integrated circuit fabrication |
| CN1164760A (en) * | 1996-05-03 | 1997-11-12 | 电子工业部第十三研究所 | T shape grid making method for semiconductor device |
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