CN1194415C - Back gate MOS transistor and its manufacturing method and static random access memory - Google Patents

Abstract

The present invention provides a self aligned back-gate MOS transistor structure which comprises a gate electrode, a sidewall dielectric layer, a gate dielectric layer, a source-drain region composed of a source-drain heavily doped region and a source-drain lightly doped region, and a channel region, wherein the source-drain region and the channel region are doped to mutually and self align with the gate electrode; the lightly doped region which is self aligned with the gate electrode is formed between the source-drain heavily doped region and the channel region, and is symmetrical; the source-drain region is thick, and the channel region is thin. In a making method of the present invention, after a back-gate electrode and a back-gate dielectric layer are formed, a thick Si film is deposited; then, ion implantation doping without a mask with lower energy is done; the surface of the present invention is smoothed by chemico-mechanical polishing. A self aligned structure of the self aligned back-gate MOS transistor structure of the present invention enables the dispersion of device properties to be minimized; the thick source-drain region and the corresponding lightly doped zone cause a parasitic resistor and off-state current to reduce; the thin channel region can provide large on-state current and improve short-channel effect. A back-gate MOS transistor of the present invention can be used as a p MOS loading pipe in a static random access memory (SRAM).

Description

Back of the body grid MOS transistor and preparation method thereof and static random access memory

Technical field:

The invention belongs to semiconductor integrated circuit manufacturing technology field, relate in particular to back of the body grid mos transistor structure and preparation method thereof and application.

Background technology:

The main flow cellular construction of static random access memory (SRAM) comprises 6 MOS transistor.Its formation can be the whole CMOS planar structure, also can be the laminated type three-dimensional structure.In three-dimensional structure, be positioned on the driving tube as 2 pMOS transistors of load pipe.Like this, the cellar area of D S RAM is little, integration density is high.Yet after the CMOS technology enters sub-micro, the bad stability of D S RAM.Its main cause is that 2 pMOS load pipes are to be made by non-aligned back of the body grid technique technology.As shown in Figure 1, in routine back of the body grid MOS transistor, therefore gate electrode can't be that mask carries out autoregistration ion implantation doping to source-drain area with it in the bottom.It is to be realized by an additional mask that the injection of source-drain area is mixed.Unavoidably there is alignment error between this mask layer and the back-gate electrode.Because it is discrete that the randomness of this error causes device property to take place.After the characteristic size of device narrowed down to deep-submicron, the discreteness of device property enlarged markedly, and caused the obvious variation of SRAM performance.

Summary of the invention:

The purpose of this invention is to provide a kind of self aligned back of the body grid mos transistor structure.

Another object of the present invention provides a kind of integrated circuit manufacture method that can realize autoregistration back of the body grid mos transistor structure.

Another purpose of the present invention provides the application of described autoregistration back of the body grid mos transistor structure in static random access memory.

Technical scheme of the present invention is as follows:

Back of the body grid MOS transistor comprises the source region that gate electrode, side wall medium layer, gate dielectric layer, source heavily doped region and source light doping section constitute, and leaks heavily doped region and leaks the drain region that light doping section constitutes, channel region.Described source or drain region and channel region mix and the mutual autoregistration of described gate electrode; Exist between the heavily doped region in described source or drain region and the channel region and described self-aligned with grid electrode and the symmetrical source or the light doping section in drain region; Thick and the channel region in described source or drain region is thin.

The manufacture method of back of the body grid MOS transistor may further comprise the steps:

1. adopting conventional cmos technology to make the bottom device on silicon substrate forms until back-gate electrode;

2.LPCVD deposit one silicon dioxide layer also carries out anisotropy and returns formation at quarter side wall, then thermal oxide growth back of the body gate dielectric layer;

3. deposit one amorphous silicon membrane and this is carried out crystallization treatment again, this amorphous silicon membrane should be thick in as far as possible to guarantee that the source-drain area that will form has acceptable low dead resistance, must guarantee also that simultaneously the channel region thickness that forms after the chemico-mechanical polishing in following the 5th step meets design requirement; Then this film is not had masked ion and inject doping, this ion implantation energy should be low as far as possible, has enough light doping sections to constitute channel region to guarantee the bottom that is doped film;

As another technical scheme that can select, the crystallization treatment again in this step is carried out after also can be moved to the following the 5th chemico-mechanical polishing that goes on foot.

4. deposit one silicon nitride stops layer certainly, and by photoetching and etching elevated regions is appeared;

5. do chemico-mechanical polishing to be carried out on the surface with silicon nitride, above back of the body gate dielectric layer, stay a thin silicon fiml after the flattening surface, constitute the channel region of device from stopping layer, and the constant formation source-drain area of the silicon film thickness at its two ends;

6. fall silicon nitride with hot phosphoric acid corrosion, photoetching and etching are formed with the source region then;

7. enter conventional later process, deposit passivation layer, opening contact hole and metallization can make described back of the body grid MOS transistor.

Above-mentioned manufacture method, amorphous silicon film thickness 〉=1500 of step (3) institute deposit.

The injection energy that no masked ion is injected in the above-mentioned manufacture method, step (3) is 20～35Kev.

Above-mentioned manufacture method, the silicon nitride thickness of step (4) institute deposit is 100～300 .

A kind of static random access memory (SRAM), its cellular construction is made of 6 MOS transistor, wherein 2 is the pMOS transistor, 4 is the nMOS transistor, described 2 pMOS transistors are the load pipe, 2 is the driving tube of described 2 load pipes in described 4 nMOS transistors, and other 2 nMOS transistors are respectively the read/write control valve, and described 2 pMOS load pipes adopt back of the body grid MOS transistor of the present invention.

Above-mentioned static random access memory, described 2 pMOS load pipes lay respectively on separately the nMOS driving tube, and share same gate electrode with its nMOS driving tube.Like this, need 2 polysilicon film deposits at described memory fabrication process China National Instruments Import ﹠ Export Corporation.Fig. 3 is that driving tube and load pipe mutual alignment concern schematic diagram among the described SRAM.

Manufacture method of the present invention, at back-gate electrode and the back of the body after gate dielectric layer forms, the Si film that deposit one is thicker; Then this there is not the more low-energy ion implantation doping of mask; Then carry out flattening surface with chemico-mechanical polishing (CMP).Made like this back of the body grid MOS transistor is structure as shown in Figure 2.Wherein, 0 is the bottom device area, and 1 is gate electrode, and 2 is side wall medium layer, and 3 is gate dielectric layer, and heavily doped region is leaked in 4 and 5 sources that are respectively, and 4 ' and 5 ' is source leakage light doping section (LDD), and 6 is channel region.Above-mentioned thicker Si film, more low-energy ion inject and chemico-mechanical polishing (CMP) has caused this back of the body grid mos transistor structure to have following feature jointly: the mutual autoregistration of mixing of (1) source-drain area and channel region, (2) source is leaked between heavily doped region and the channel region and is had self aligned and symmetrical light doping section, and (3) source-drain area is thick and channel region thin.So in theory a kind of structure is a desirable back of the body grid mos transistor structure.At first, self-alignment structure makes the discrete of device property minimize.Secondly thick source and drain regions and corresponding light doping section cause dead resistance and off-state current to reduce.The thin channel district can provide big conducting electric current and improve short-channel effect in addition.

Description of drawings:

Fig. 1 is conventional back of the body grid mos transistor structure schematic diagram.

Fig. 2 is autoregistration back of the body grid mos transistor structure schematic diagram of the present invention.

Fig. 3 is that driving tube and load pipe mutual alignment concern schematic diagram among the SRAM of the present invention.

Fig. 4 is autoregistration back of the body grid MOS transistor preparation method's of the present invention main procedure of processing schematic diagram.

Among the figure,

0-removes the blanket of gate electrode outer bottom layer device

1-gate electrode (heavily doped polysilicon)

2-side wall (silicon dioxide)

3-gate dielectric layer (silicon dioxide)

4-source region heavy doping part

4 '-source region light dope part

5-drain region heavy doping part

5 '-drain region light dope part

The 6-channel region

The light doping section of 6 '-thick silicon fiml, the predecessor of channel region

The part of the heavily doped region of the thick silicon fiml of 10-

11-CMP is from stopping layer (silicon nitride)

The 20-monocrystalline substrate

23-driving tube gate dielectric layer (silicon dioxide)

24-driving tube source region (heavy doping of N type)

25-driving tube drain region (heavy doping of N type)

26-driving tube channel region (P type light dope)

Embodiment:

Embodiment 1: back of the body grid MOS transistor and preparation method thereof

As shown in Figure 2, be the structure of back of the body grid MOS transistor of the present invention.

The processing step of the manufacturing technology of the structure of back of the body grid MOS transistor shown in Figure 2 following (referring to Fig. 4):

1. shown in Fig. 4 (a), at first on monocrystalline substrate, make bottom device (0) with the conventional cmos technology.Polygate electrodes (1) while is as the gate electrode of upper strata back-gated transistor.

2. shown in Fig. 4 (b), with LPCVD deposit one silicon dioxide layer and carry out anisotropy and return and form side wall (2) quarter (etch-back).This Hui Kexu finished before silicon dioxide on the gate electrode is carved fully.Residual part is removed by wet etching (rare HF).Can guarantee that like this surface gate electrode is not carved and damaged by mistake.Then thermal oxide growth is carried on the back gate dielectric layer (3).

3. shown in Fig. 4 (c),, after laser or other crystallization technique processing again (annotate: crystallization also can carried out behind the CMP in the 5th step again), do not have mask and mix than the low energy ion injection with the amorphous silicon layer of LPCVD deposit one thicker (thickness 〉=1500 ).Injectant is BF ₂, dosage is 1～2E15cm ^-2, energy is 20～35Kev.The formation that silicon fiml that this is thicker and lower ion implantation energy have caused autoregistration to be mixed jointly.Its principle is: this than the low energy ion injection condition under because silicon fiml is thicker, although its nearly surface portion be heavy doping (P+), its bottom is gently or utmost point light dope (P-).Like this, the near surperficial heavy doping part (10) of the silicon fiml of gate electrode top projection can equivalence be the mask of bottom light dope part (6 ').And this bottom light dope part (6 ') heavily doped region (10) at an upper portion thereof removes the channel region that will become device afterwards.Because the geometry of the protruding silicon fiml in back-gate electrode top is followed this back-gate electrode, therefore nature autoregistration mutual with it.And always greater than back of the body gate length, therefore go back nature forms self aligned light doping section (4 ' and 5 ') in side wall (2) both sides to the length on protruding silicon fiml surface.

4. shown in Fig. 4 (d), deposit one 100～300 silicon nitride films (11) and photoetching and etching are exposed the silicon fiml part of projection.

5. shown in Fig. 4 (e), do chemico-mechanical polishing (CMP) to be carried out on the surface from stopping layer with silicon nitride.Above gate oxide, stay a thin silicon fiml after the flattening surface, constitute the channel region (6) of device, and the constant formation of the silicon film thickness at its two ends source (4+4 ') leak (5+5 ') district.(4) and (5) be respectively the heavy doping part of source-drain area, and (4 ') and (5 ') be light dope part (LDD).

6. fall silicon nitride with hot phosphoric acid corrosion.Photoetching and etching are formed with the source region then.So far, formed device architecture has following feature: the mutual autoregistration of mixing of (1) source-drain area and channel region, (2) source are leaked between heavily doped region and the channel region and are had self aligned and symmetrical light doping section, and (3) source-drain area is thick and channel region thin.

7. enter conventional later process, such as deposit passivation layer, opening contact hole and metallization etc.

Embodiment 2: static random access memory (SRAM)

Static random access memory (SRAM), its cellular construction is made of 6 MOS transistor, and wherein 2 is the pMOS transistor, and 4 is the nMOS transistor.Described 2 pMOS transistors are the load pipe, and 2 is the driving tube of described 2 load pipes in described 4 nMOS transistors, and other 2 nMOS transistors are respectively the read/write control valve.Described 2 pMOS load pipes adopt the back of the body grid MOS transistor among the embodiment 1, and lay respectively on separately the nMOS driving tube, and described pMOS load Guan Yuqi nMOS driving tube is shared same gate electrode.Like this, in described memory fabrication process, only need 2 polysilicon film deposits.Fig. 3 is that driving tube and load pipe mutual alignment concern schematic diagram among the described SRAM.

Claims (7)

1. Back gate MOS transistor, including gate electrode, side wall dielectric layer, gate dielectric layer, source region composed of heavily doped source region and lightly doped source region, drain composed of heavily doped drain region and lightly doped drain region region, channel region, characterized in that the doping of the source or drain region and the channel region is self-aligned with the gate electrode; there is a gap between the heavily doped region of the source or drain region and the channel region A lightly doped region of a source or drain region self-aligned with the gate electrode and symmetrical; the source or drain region is thick and the channel region is thin. 2. The manufacture method of back gate MOS transistor, comprises the following steps: (1) The underlying device is made on the silicon substrate by conventional CMOS technology until the back gate electrode is formed; (2) LPCVD deposits a silicon dioxide layer and performs anisotropic etching back to form sidewalls, and then thermally oxidizes and grows a back gate dielectric layer; (3) Deposit an amorphous silicon film and carry out recrystallization treatment, the thickness of this amorphous silicon film is sufficient to ensure that the source and drain regions to be formed have acceptable low parasitic resistance, and it must also be guaranteed in the following (5) ) The thickness of the channel region formed after the chemical mechanical polishing in the first step meets the design requirements; then the film is doped with maskless ion implantation, and the ion implantation energy should be as low as possible to ensure that the bottom of the doped film has enough A lightly doped region to form a channel region; (4) Deposit a silicon nitride self-stop layer, and expose the raised area by photolithography and etching; (5) Using silicon nitride as the self-stop layer, the surface is chemically mechanically polished. After the surface is planarized, a thin silicon film is left above the back gate dielectric layer to form the channel region of the device, and the silicon at both ends The film thickness remains unchanged to form the source and drain regions; (6) Etch silicon nitride with hot phosphoric acid, and then photolithography and etching form an active region; (7) Entering into the conventional subsequent process, depositing a passivation layer, opening a contact hole and metallizing, the back gate MOS transistor can be manufactured. 3. The manufacturing method according to claim 2, characterized in that the thickness of the amorphous silicon film deposited in step (3) is greater than or equal to 1500 Å. 4. The manufacturing method according to claim 2, characterized in that the maskless ion implantation in step (3) has an implantation energy of 20-35Kev. 5. The manufacturing method according to claim 2, characterized in that the thickness of the silicon nitride deposited in step (4) is 100-300 Å. 6. A kind of static random access memory (SRAM), its cell structure is made of 6 MOS transistors, wherein 2 are pMOS transistors, 4 are nMOS transistors, described 2 pMOS transistors are load tubes, and described 4 nMOS transistors Two of them are the driving tubes of the two load tubes, and the other two nMOS transistors are respectively read/write control tubes. It is characterized in that the two pMOS load tubes are all back-gate MOS transistors, and the structure includes a gate electrode , a sidewall dielectric layer, a gate dielectric layer, a source region composed of a heavily doped source region and a lightly doped source region, a drain region composed of a heavily doped drain region and a lightly doped drain region, and a channel region, the source or The doping of the drain region and the channel region is self-aligned with the gate electrode; between the heavily doped region of the source or drain region and the channel region there is a source or source that is self-aligned and symmetrical with the gate electrode The lightly doped region of the drain region; the source or drain region is thick and the channel region is thin. 7. The SRAM according to claim 6, wherein the two pMOS load transistors are respectively located above their respective nMOS drive transistors, and share the same gate electrode with the nMOS drive transistors.

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