CN1215564C

CN1215564C - A kind of semiconductor flash memory and its preparation method

Info

Publication number: CN1215564C
Application number: CN03137019.5A
Authority: CN
Inventors: 张盛东; 陈文新; 黄如; 刘晓彦; 张兴; 韩汝琦; 王阳元
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2003-05-29
Filing date: 2003-05-29
Publication date: 2005-08-17
Anticipated expiration: 2023-05-29
Also published as: CN1455457A

Abstract

The invention provides a semiconductor flash memory structure, which is a MOS transistor, the channel region of which is a silicon wall perpendicular to the silicon substrate; The dielectric layer, the control gate; the control gate and the floating gate distributed on the left and right sides of the channel region are self-aligned with each other. In the preparation method of the flash memory of the present invention, the vertical silicon wall as the channel region is formed by photolithography and etching the silicon film on the SOI silicon wafer; the floating gate electrodes on both sides of the silicon wall are formed by depositing The polysilicon film is formed by anisotropic etching, and its formation does not require any photolithography steps; the length of the control gate and the floating gate is determined by the same photolithography mask, so a mutual self-aligned structure is naturally formed. Compared with the conventional structure, the gate length of the memory structure of the present invention can be further significantly reduced under the same conditions, and the memory has stronger shrinkability and better storage performance.

Description

A kind of semiconductor flash memory and preparation method thereof

Technical field:

The present invention is semiconductor integrated circuit structure and manufacture technology field, is specifically related to semiconductor quickflashing (FLASH) memory construction and preparation method thereof.

Background technology:

The semiconductor flash memory is a kind of erasable memory of writing that emerges in recent years.Its conventional structure is by shown in Figure 1.This structure of all things considered is a MOS transistor.Wherein, 1 is silicon substrate; 2 and 5 are respectively transistorized source/drain region; 8 is transistorized channel region; 6 and 3 are respectively tunneling medium layer and block media layer; 4 and 7 are respectively control gate and floating boom.The high speed of semiconductor integrated circuit and high-density development direction require the gate electrode length of MOS transistor constantly to reduce.For the short-channel effect that suppresses to cause therefrom, transistorized gate medium also must corresponding attenuate.But in flash memory, when tunneling medium layer 6 is thinned to 80 dusts when following, the direct Tunneling electric current that floating boom 7 and raceway groove are 8 will significantly increase, and make the information (electric charge) that writes on the floating boom 7 reliably not preserve.Therefore, in flash memory, gate length reduce to be subjected to very big restriction, correspondingly the raising of the speed of memory and density also has been subjected to serious restriction.

Summary of the invention:

The purpose of this invention is to provide a kind of new semiconductor flash memory structure, make gate length under equal conditions can further significantly reduce, thereby provide memory with higher speed and density.

Another object of the present invention provides the preparation method of above-mentioned flash memory.

Technical scheme of the present invention is as follows:

A kind of semiconductor flash memory, it is a MOS transistor, comprise silicon substrate and on insulating medium layer, channel region, source/drain region, tunneling medium layer, block media layer, control gate and floating boom, described channel region and source/drain region are a silicon wall perpendicular to described silicon substrate on the described insulating medium layer, and the described channel region left and right sides all is arranged in order tunneling medium layer, floating boom, block media layer, control gate.The control gate that is distributed in the described channel region left and right sides is separated from each other, autoregistration mutually; The floating boom that is distributed in the described channel region left and right sides is separated from each other, autoregistration mutually.

Because control grid electrode does not have head portion, be two mutual independent parts about control gate is separated into, therefore take different voltage bias respectively by control gate, can on the floating boom of corresponding two separation, write different information, thereby realize the storage of 2 bit data these two separation.

The preparation method of described semiconductor flash memory may further comprise the steps successively:

1. parent material is the SOI wafer, and it is made of silicon substrate, insulating medium layer and monocrystalline silicon membrane;

2. monocrystalline silicon membrane is carried out the channel region of photoetching and etching formation vertical silicon screen formation; Follow the thermal oxide growth tunneling medium layer;

3. deposit one in-situ doped polysilicon layer also returns quarter with anisotropic etching equipment to this polysilicon layer, forms the polysilicon side wall that is separated from each other, i.e. floating gate electrode in silicon wall both sides;

4. thermal oxide growth silicon dioxide forms the block media layer once more, then the in-situ doped polysilicon layer of deposit one and this polysilicon layer carried out photoetching and etching forms control grid electrode again;

5. after control grid electrode forms, and then etch away the gate electrode zone silicon dioxide and the polysilicon that is used for forming floating gate electrode that are used for forming the block media layer in addition;

6. make masking layer with control grid electrode, the silicon wall beyond the gate electrode zone is carried out ion implantation doping with formation source/drain region;

7. the silicon nitride layer that equates with silicon wall height of deposit one thickness, and this silicon nitride layer carried out photoetching and etching are covered in device area with removal silicon nitride part;

8. stop layer with this silicon nitride as oneself,, fall silicon nitride from stopping layer with hot phosphoric acid corrosion then, realize the separation of control gate in both sides with the head portion of chemico-mechanical polishing removal control gate polysilicon;

9. adopt the conventional cmos postchannel process, finish, can make described quickflashing semiconductor memory such as deposit passivation layer, opening contact hole and metallization etc.

Through the obtained quickflashing semiconductor memory of above method, can realize the storage of 2 bit data.

Flash memory of the present invention structurally has following distinguishing feature: (1) channel region is a vertical silicon screen; (2) control gate and floating boom are double-gate structure; (3) control gate, block media layer, floating boom, tunneling medium layer and channel region are vertical arrangement; (4) control gate and floating boom are positioned at the channel region left and right sides and autoregistration mutually.Memory construction proposed by the invention is compared with conventional structure, and gate length under equal conditions can further significantly reduce, and memory has stronger dwindled ability, better memory property.Its principle is: channel region is a vertical silicon screen, and its both sides all are subjected to grid-control system; The silicon wall can be made into ultra-thin body simultaneously.And double grid control and ultra-thin body raceway groove can farthest suppress short-channel effect.

The preparation method of flash memory of the present invention and existing CMOS technology are compatible fully.As the vertical silicon screen of channel region is by the silicon fiml on the soi wafer being carried out photoetching and etching forms; The floating gate electrode of silicon wall both sides is to carry out anisotropic etching by the polysilicon film to deposit to form, and it forms does not need any lithography step; The length of control gate and floating boom is by being determined with a photo etched mask, so form mutual self-alignment structure naturally.

Description of drawings:

Fig. 1 is conventional FLASH memory construction schematic diagram.

Fig. 2 is a FLASH memory construction schematic diagram of the present invention, (a) is stereogram, (b) is the A-A ' profile among the figure (a).

Fig. 3 is 2 bit data FLASH memory construction schematic diagrames of the present invention.

Fig. 4 is the key step schematic diagram of FLASH memory process manufacture method of the present invention.

Among the figure:

1-substrate (monocrystalline silicon piece)

2-source region (heavily doped silicon)

3-grid resistance retaining dielectric layer (silicon dioxide)

4,4 '-control grid electrode (heavily doped polysilicon)

5-drain region (heavily doped silicon)

6-grid tunneling medium layer (silicon dioxide)

7,7 '-floating gate electrode (heavily doped polysilicon)

8-channel region (be the plane monocrystalline silicon layer in Fig. 1, be vertical monocrystalline silicon wall among other figure)

8 '-monocrystalline silicon membrane

9-insulating medium layer (silicon dioxide)

10-CMP stops layer (silicon nitride)

Embodiment:

Embodiment 1: the semiconductor flash memory

As shown in Figure 2, be the schematic diagram of flash memory structure.Wherein (a) is stereogram, (b) is corresponding A-A profile.This semiconductor flash memory is a MOS transistor, comprises silicon substrate, source/drain region, channel region, tunneling medium layer, block media layer, control gate and floating boom, and insulating medium layer 9 is arranged on the silicon substrate 1; Channel region 8 is a silicon wall perpendicular to silicon substrate 1 on the insulating medium layer 9; Channel region 8 left and right sides are vertically arranged tunneling medium layer 6, floating boom 7, block media layer 3, control gate 4 successively; Be distributed in control gate 4, the floating boom 7 mutual autoregistrations of channel region 8 left and right sides.

Fig. 3 is 2 bit data flash memory structure schematic diagrames.With the main distinction of structure shown in Figure 2 be that control grid electrode does not have head portion, two mutual independent parts 4 and 4 ' about promptly control gate is separated into.Like this, take different voltage bias respectively with 4 ', can write different information on 7 ', thereby realize the storage of 2 bit data at corresponding floating boom 7 by control gate 4 to these two separation.

Embodiment 2: the preparation method of flash memory

The concrete process implementation method of flash memory structure shown in Figure 2 is as follows, and Fig. 4 shows its key step.

1. parent material is the SOI wafer, and it is made of silicon substrate 1, insulating medium layer 9 and monocrystalline silicon membrane 8 ', shown in Fig. 4 (a);

2. monocrystalline silicon membrane 8 ' is carried out photoetching and etching formation channel region 8 (vertical silicon screen); Follow thermal oxide growth tunneling medium layer 3 (silica), shown in Fig. 4 (b);

3. deposit one in-situ doped (in-situ doped) polysilicon layer also returns this polysilicon layer with anisotropic etching equipment and forms floating gate electrode 7 quarter (etch-back), shown in Fig. 4 (c);

4. thermal oxide growth silicon dioxide forms block media layer 3 once more, and then in-situ doped (in-situ doped) polysilicon layer of deposit one and this polysilicon layer carried out photoetching and etching forms control grid electrode 4 again is shown in Fig. 4 (d);

5. after control grid electrode 4 forms, and then etch away the gate electrode zone silicon dioxide and the polysilicon that is used for forming floating gate electrode 7 that are used for forming block media layer 3 in addition;

6. make masking layer with control grid electrode 4, the silicon wall beyond the gate electrode zone is carried out ion implantation doping to form 2/ drain region 5, source region, shown in Fig. 2 (a).

So far, preceding working procedure finishes, and later process is identical with conventional cmos technology, such as deposit passivation layer, opening contact hole and metallization etc.

After above-mentioned 6 steps, also need increase following 2 steps, can form 2 bit data memory constructions shown in Figure 3:

1. the silicon nitride layer 10 that highly equates of deposit one thickness and silicon wall 8, and this silicon nitride layer is carried out photoetching and etching be covered in the silicon nitride part of device area with removal, shown in Fig. 4 (e);

2. stop layer with this silicon nitride as oneself, remove the head portion of control gate polysilicon with chemico-mechanical polishing (CMP).So just, formed as shown in Figure 3 about two control gates disconnected from each other 4 and 4 '.Fall silicon nitride from stopping layer with hot phosphoric acid corrosion then, enter later process.

Claims

1. semiconductor flash memory, it is a MOS transistor, comprise silicon substrate and on insulating medium layer, channel region, source/drain region, tunneling medium layer, block media layer, control gate and floating boom, described channel region and source/drain region are a silicon wall perpendicular to described silicon substrate on the described insulating medium layer, the described channel region left and right sides all is arranged in order tunneling medium layer, floating boom, block media layer, control gate, it is characterized in that: the control gate that is distributed in the described channel region left and right sides is separated from each other, autoregistration mutually; The floating boom that is distributed in the described channel region left and right sides is separated from each other, autoregistration mutually.

2. the preparation method of the described semiconductor flash memory of claim 1 may further comprise the steps successively:

(1) parent material is the SOI wafer, and it is made of silicon substrate, insulating medium layer and monocrystalline silicon membrane;

(2) monocrystalline silicon membrane is carried out photoetching and etching and form the channel region that vertical silicon screen constitutes; Follow the thermal oxide growth tunneling medium layer;

(3) deposit one in-situ doped polysilicon layer also returns quarter with anisotropic etching equipment to this polysilicon layer, and forming the polysilicon side wall that is separated from each other in silicon wall both sides is floating gate electrode;

(4) thermal oxide growth silicon dioxide forms the block media layer once more, then the in-situ doped polysilicon layer of deposit one and this polysilicon layer carried out photoetching and etching forms control grid electrode again;

(5) after control grid electrode forms, and then etch away the gate electrode zone silicon dioxide and the polysilicon that is used for forming floating gate electrode that are used for forming the block media layer in addition;

(6) make masking layer with control grid electrode, the silicon wall beyond the gate electrode zone is carried out ion implantation doping with formation source/drain region;

(7) silicon nitride layer that equates with silicon wall height of deposit one thickness, and this silicon nitride layer carried out photoetching and etching are covered in device area with removal silicon nitride part;

(8) stop layer with this silicon nitride as oneself,, fall silicon nitride from stopping layer with hot phosphoric acid corrosion then, realize the separation of control gate in both sides with the head portion of chemico-mechanical polishing removal control gate polysilicon;

(9) adopt the conventional cmos postchannel process, finish deposit passivation layer, opening contact hole and metallization, can make described quickflashing semiconductor memory.