CN119249986B

CN119249986B - Verification method and device of voltage configuration algorithm and electronic equipment

Info

Publication number: CN119249986B
Application number: CN202411773643.XA
Authority: CN
Inventors: 生蕾
Original assignee: Dingdao Zhixin Shanghai Semiconductor Co ltd
Current assignee: Dingdao Zhixin Shanghai Semiconductor Co ltd
Priority date: 2024-12-04
Filing date: 2024-12-04
Publication date: 2025-04-22
Anticipated expiration: 2044-12-04
Also published as: CN119249986A

Abstract

The application discloses a verification method, a device and electronic equipment of a voltage configuration algorithm, wherein the method comprises the steps of obtaining a plurality of reference voltages of the voltage configuration algorithm deployed by memory particles, determining target voltages from the plurality of reference voltages, adjusting signal values corresponding to partial time periods in a first signal according to the target voltages and the plurality of reference voltages to obtain a second signal, obtaining standard voltages determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal, and obtaining verification results according to the standard voltages and the target voltages, wherein the verification results represent whether the voltage configuration algorithm is accurate or not.

Description

Verification method and device of voltage configuration algorithm and electronic equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for verifying a voltage configuration algorithm, and an electronic device.

Background

Currently, a voltage configuration algorithm may select a suitable standard voltage, which may be denoted by VREF (Voltage reference), for the memory particles among a plurality of candidate voltages. The memory granule may use standard voltages for conversion between analog and digital signals.

However, in the simulation environment, the eye width of the signals fed back by the simulation model of the memory particles cannot be changed by different reference voltages, so that the eye width cannot be obtained by the voltage configuration algorithm in the simulation environment, the standard voltage cannot be selected, and the accuracy of the voltage configuration algorithm cannot be verified.

Therefore, it is only dependent on the memory particle chip itself to verify whether the voltage configuration algorithm is accurate.

Disclosure of Invention

In view of the above, the application provides a verification method and device for a voltage configuration algorithm and an electronic device, as follows:

a method of verifying a voltage configuration algorithm, comprising:

obtaining a plurality of reference voltages of a voltage configuration algorithm deployed by memory particles;

determining a target voltage from the plurality of reference voltages;

according to the target voltage and the plurality of reference voltages, adjusting signal values corresponding to partial time periods in the first signal to obtain a second signal;

Obtaining a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal;

and obtaining a verification result according to the standard voltage and the target voltage, wherein the verification result represents whether the voltage configuration algorithm is accurate or not.

In the above method, preferably, adjusting a signal value corresponding to a partial period in the first signal according to the target voltage and the plurality of reference voltages to obtain the second signal includes:

Obtaining a voltage difference between each of the reference voltages and the target voltage;

and adjusting a signal value corresponding to a part of time periods in the first signal according to the voltage difference value to obtain a second signal.

In the above method, preferably, adjusting a signal value corresponding to a partial period in the first signal according to the voltage difference value includes:

processing an absolute value corresponding to the voltage difference value by using a sampling coefficient corresponding to the memory particle to obtain a first period;

And adjusting a signal value corresponding to the first time period in the first signal to be a preset target value so as to obtain a second signal.

Obtaining a third signal according to the voltage difference;

and performing bit-wise AND on the third signal and the first signal to obtain a second signal.

In the above method, preferably, a signal value corresponding to the second period in the third signal is a preset target value;

wherein the second period is obtained by:

And processing the absolute value corresponding to the voltage difference value by using the sampling coefficient corresponding to the memory particle to obtain a second period.

In the above method, preferably, obtaining a verification result according to the standard voltage and the target voltage includes:

comparing the standard voltage with the target voltage;

if the standard voltage is consistent with the target voltage, obtaining an accurate verification result representing the voltage configuration algorithm;

and if the standard voltage is inconsistent with the target voltage, obtaining a verification result representing inaccuracy of the voltage configuration algorithm.

In the above method, preferably, the voltage configuration algorithm obtains an eye width parameter corresponding to each reference voltage according to the second signal corresponding to each reference voltage, and determines the standard voltage from the plurality of reference voltages according to the eye width parameter;

The eye width parameter corresponding to the standard voltage is the largest among the eye width parameters corresponding to all the reference voltages.

The method, preferably, obtains a plurality of reference voltages of the voltage configuration algorithm, including:

And reading voltage configuration parameters corresponding to the voltage configuration algorithm at each rising edge of the clock signal in a back gate mode, wherein the voltage configuration parameters comprise reference voltages corresponding to the rising edges.

A verification apparatus for a voltage configuration algorithm, comprising:

a reference obtaining unit, configured to obtain a plurality of reference voltages of a voltage configuration algorithm deployed by the memory granule;

A target determination unit configured to determine a target voltage from among the plurality of reference voltages;

The signal obtaining unit is used for adjusting signal values corresponding to partial time periods in the first signal according to the target voltage and the plurality of reference voltages so as to obtain a second signal;

A signal processing unit for obtaining a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal;

And the algorithm verification unit is used for obtaining a verification result according to the standard voltage and the target voltage, and the verification result represents whether the voltage configuration algorithm is accurate or not.

An electronic device, comprising:

A memory for storing a computer program and data resulting from the execution of the computer program;

A processor for executing the computer program to implement:

determining a target voltage from the plurality of reference voltages;

A computer readable storage medium having stored thereon a computer program/instruction which when executed by a processor implements the steps of the verification method of the voltage configuration algorithm described above.

A computer program product comprising computer programs/instructions which when executed by a processor implement the steps of the verification method of the voltage configuration algorithm described above.

According to the technical scheme, in the verification method, the verification device and the electronic equipment of the voltage configuration algorithm, after the multiple reference voltages of the voltage configuration algorithm deployed by the memory particles are obtained, the signals provided for the voltage configuration algorithm can be adjusted according to the target voltage selected from the reference voltages and each other reference voltage, so that the signals used by the voltage configuration algorithm can be actively changed, the voltage configuration algorithm can select the standard voltage from the reference voltages according to the different signals, and further, the verification result representing whether the voltage configuration algorithm is accurate or not can be obtained according to the standard voltage and the target voltage.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flowchart of a verification method of a voltage configuration algorithm according to an embodiment of the present application;

FIG. 2 is a diagram illustrating an example of determining a standard voltage using a voltage configuration algorithm by generating a second signal in accordance with an embodiment of the present application;

FIG. 3 is a diagram showing another example of determining a standard voltage using a voltage configuration algorithm by generating a second signal according to an embodiment of the present application;

FIG. 4 is a diagram of another example of determining a standard voltage using a voltage configuration algorithm by generating a second signal in accordance with an embodiment of the present application;

Fig. 5 is a schematic structural diagram of a verification device for a voltage configuration algorithm according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

FIG. 7 is a flow chart of the verification of the voltage configuration algorithm in the context of the present application applicable to LPDDR 5;

fig. 8 is an exemplary diagram of adjusting signal eye width in a scene suitable for LPDDR5 according to the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Referring to fig. 1, a flowchart of an implementation of a verification method of a voltage configuration algorithm according to an embodiment of the present application may be applicable to an electronic device, such as a computer or a server, capable of being connected to a simulation model corresponding to a memory granule and performing Data processing, where the memory granule may be a memory granule of low-power memory power LPDDR5 (Low Power Double Data Rate), and has a voltage configuration algorithm CBT tracking (command Bus training), and the voltage configuration algorithm may be applicable to selection of various VREF, such as VREF of command Bus CA (Command Address), i.e., CA VREF, and VREF of Data Bus DQ (Data Bus), i.e., DQ VREF. The technical scheme in the embodiment is mainly used for improving the accuracy and the reliability of verifying the voltage configuration algorithm under the condition of not depending on the memory particles.

Specifically, the method in this embodiment may include the following steps:

step 101, obtaining a plurality of reference voltages of a voltage configuration algorithm deployed by memory particles.

In this embodiment, the voltage configuration parameters corresponding to the voltage configuration algorithm may be read by a back-gate manner, such as backdoor, at each rising edge of the clock signal, where the voltage configuration parameters include the reference voltages corresponding to the rising edges. The reference voltage in the voltage configuration parameters is used by the voltage configuration algorithm to determine the standard voltage for CA or the standard voltage for DQ. For example, the voltage configuration algorithm may configure a plurality of reference voltages from which an appropriate reference voltage is selected as the standard voltage by the voltage configuration algorithm.

Step 102, determining a target voltage from a plurality of reference voltages.

The target voltage may be a voltage randomly selected from a plurality of reference voltages, or the target voltage may be an intermediate value selected from the plurality of reference voltages. The target voltage may be represented by GV or golden VREF, which is collectively referred to as golden Voltage reference.

Step 103, adjusting signal values corresponding to partial time periods in the first signal according to the target voltage and the plurality of reference voltages to obtain a second signal.

The first signal refers to a CA signal or DQ signal input to the memory granule.

It should be noted that, in this embodiment, for each reference voltage, according to the reference voltage and the target voltage, the signal value corresponding to the partial period in the first signal may be adjusted, so as to achieve the purpose of changing the signal eye width of the first signal multiple times, and further obtain multiple corresponding second signals. The resulting second signals correspond to each of the reference voltages different from the target voltage, respectively.

For example, as shown in fig. 2, the voltage configuration algorithm may configure n reference voltages, V1 to Vn, from which one is selected as a target voltage, such as V3 is selected as GV in this embodiment, and then, for each of the reference voltages V1 to Vn, signal values of partial periods in the first signal are respectively adjusted, so that the signal eye widths of the obtained different second signals are different based on the different reference voltages, and thus, the eye widths of the analog signals are changed by the plurality of second signals.

Step 104, obtaining standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal.

In this embodiment, the second signal may be captured by a simulation model corresponding to the memory particle, and the standard voltage may be determined from the plurality of reference voltages by using a voltage configuration algorithm according to the second signal.

Specifically, in step 104, the second signal may be transmitted to a simulation model corresponding to the memory particle, where the simulation model is configured to capture the second signal and determine, by using a voltage configuration algorithm, a standard voltage from a plurality of reference voltages according to the second signal.

In one implementation, the simulation model may obtain, by a voltage configuration algorithm, an eye width parameter corresponding to each reference voltage according to a second signal corresponding to each reference voltage, and determine a standard voltage from the plurality of reference voltages according to the eye width parameter. For example, taking fig. 2 as an example, in the present embodiment, one is selected as the target voltage, for example, V3 is selected as GV, and then a plurality of second signals are obtained for each of the reference voltages V1 to Vn, respectively, which are adjusted based on different reference voltages, and thus, the signal eye widths of the second signals are different, and thus, the second signals are sequentially transmitted to the simulation model, whereby the change in the eye width of the signal is simulated to the simulation model. Based on the above, the simulation model performs eye width detection on the sequentially captured second signals, and further obtains an eye width parameter (signal eye width) of each second signal, that is, an eye width parameter corresponding to each reference voltage, so that the voltage configuration algorithm can select a standard voltage from the reference voltages according to the magnitude of the signal eye width of the eye width parameter, where the standard voltage may be V3 in the reference voltages or other voltages in the reference voltages.

The eye width parameter corresponding to the standard voltage is the largest among the eye width parameters of the second signals corresponding to all the reference voltages.

Specifically, after capturing the second signal, the simulation model provides the second signal to a voltage configuration algorithm, the voltage configuration algorithm identifies an eye width parameter corresponding to the second signal, namely an eye width parameter corresponding to a reference voltage corresponding to the second signal, specifically, a signal eye width of the second signal, so that the simulation model captures one second signal each time, the voltage configuration algorithm performs one-time eye width identification, the eye width parameter corresponding to the second signal can be obtained, and based on the eye width parameter identified by the voltage configuration algorithm according to each second signal, a standard voltage is determined from a plurality of reference voltages.

In one implementation, the voltage configuration algorithm may determine, from among a plurality of reference voltages, a reference voltage corresponding to a second signal having a maximum signal eye width as the standard voltage.

For example, as shown in fig. 2, the voltage configuration algorithm in the simulation model selects the reference voltage, such as V2 or V3, with the maximum eye width of the corresponding signal from V1 to Vn as the standard voltage.

And 105, obtaining a verification result according to the standard voltage and the target voltage, wherein the verification result represents whether the voltage configuration algorithm is accurate.

In one implementation manner, in this embodiment, the standard voltage and the target voltage may be compared, and then a verification result may be obtained according to the obtained comparison result.

Specifically, if the standard voltage is consistent with the target voltage, the voltage configuration algorithm can accurately identify the signal eye width and select the standard voltage according to the signal eye width, then an accurate verification result of the characteristic voltage configuration algorithm can be obtained, and if the standard voltage is inconsistent with the target voltage, the voltage configuration algorithm can not accurately identify the signal eye width or can not accurately select the standard voltage according to the signal eye width, then an inaccurate verification result of the characteristic voltage configuration algorithm can be obtained.

For example, in this embodiment, the signal value of the CA signal part period provided to the simulation model is changed by the voltage difference between the reference voltage and the target voltage, so as to change the signal eye width of the CA signal, so that the eye width change process of the CA signal can be simulated, and whether the voltage configuration algorithm CBT tracking can accurately determine the correct standard voltage is determined based on whether the standard voltage determined by the voltage configuration algorithm CBT tracking is consistent with the target voltage, thereby realizing verification of the voltage configuration algorithm CBT tracking, and the verification process does not depend on the memory particle of LPDDR 5. For example, taking the example shown in fig. 2, if the voltage configuration algorithm determines that V3 is the standard voltage, it is consistent with GV, and then it can be determined that the voltage configuration algorithm can accurately determine the correct standard voltage, and if the voltage configuration algorithm determines that V2 is the standard voltage, it is inconsistent with GV, and then it can be determined that the voltage configuration algorithm cannot accurately determine the correct standard voltage.

According to the technical scheme, in the verification method of the voltage configuration algorithm provided by the embodiment of the application, after the multiple reference voltages of the voltage configuration algorithm deployed by the memory particles are obtained, the signals provided for the voltage configuration algorithm can be adjusted according to the target voltage selected from the reference voltages and each other reference voltage, so that the signals used by the voltage configuration algorithm can be actively changed, the voltage configuration algorithm can select the standard voltage from the reference voltages according to the different signals, and further, the verification result representing whether the voltage configuration algorithm is accurate or not can be obtained according to the standard voltage and the target voltage.

In one implementation manner, when adjusting the signal value corresponding to the partial period in the first signal according to the target voltage and the multiple reference voltages in step 103, the following manner may be implemented:

First, a voltage difference between each reference voltage and the target voltage is obtained, and then, according to the voltage difference, a signal value corresponding to a part of time periods in the first signal is adjusted to obtain a second signal.

Wherein the period of time for which the signal value is adjusted in the first signal may be determined based on the voltage difference.

Specifically, in this embodiment, a sampling coefficient corresponding to a memory particle may be used to process an absolute value corresponding to a voltage difference value to obtain a first period, where the sampling coefficient may be an empirical value, but the sampling coefficient may be determined based on a frequency point of the memory particle and a sampling mechanism, and the sampling coefficient may enable the memory particle to sample a signal, and then, according to the first period, a signal value corresponding to the first period in the first signal is adjusted to a preset target value to obtain a second signal.

The preset target value may be represented by X, and the specific value may be set according to the service requirement. The first period of time, which indicates a period of time in which the eye width needs to be adjusted to be narrowed in the first signal, may be denoted by T1, and in this embodiment, the sampling coefficient may be multiplied by an absolute value corresponding to the voltage difference to obtain the first period of time T1. Based on this, the signal value of the first period is adjusted to the target value in the present embodiment to obtain the second signal.

It can be seen that in this embodiment, the signal value processing may be directly performed on the first signal based on the reference voltage and the target voltage, so as to obtain the second signal with the changed eye width.

For example, as shown in fig. 3, in this embodiment, V1 and V3 may be subjected to difference, in which the signal value of the period T1 in the CA signal is adjusted to X according to the voltage difference, so as to obtain a second signal different from the eye width of the CA signal, V2 and V3 are subjected to difference, in which the signal value of the period T1 in the CA signal is adjusted to X according to the voltage difference, so as to obtain a second signal different from the eye width of the second signal corresponding to CA signal and V1, V3 and V3 are subjected to difference, in which the signal value of the period T1 in the CA signal is adjusted to X according to the voltage difference (0), so as to obtain a second signal different from the eye width of the second signal corresponding to each of the CA signal and V1 and V2 (in other embodiments, the same reference voltage as GV is not adjusted), and V4 and V3 are subjected to difference, so as to obtain a signal value of the period T1 in the CA signal, and V3 are subjected to difference, so as to obtain a signal of the eye width of the second signal corresponding to the CA signal, and V1 and V3 are subjected to difference, so as to obtain a signal of the eye width of the second signal different from the second signal corresponding to the eye width of the second signal. Based on this, after these second signals are transmitted to the simulation model of the memory particle in this way, the simulation model can capture the second signals with varying eye widths, and then select the standard voltage from the reference voltages V1 to Vn according to the eye width parameters of these second signals through the voltage configuration algorithm, compare it with the target voltage, if the standard voltage is consistent with the GV, for example, V3, it can be determined that the voltage configuration algorithm can accurately select the correct standard voltage, and if the standard voltage is inconsistent with the GV, it can be determined that the voltage configuration algorithm cannot accurately select the correct standard voltage.

In another implementation manner, when the signal value corresponding to the partial period in the first signal may be adjusted according to the target voltage and the multiple reference voltages in step 103, the following manner may be implemented:

Firstly, obtaining a voltage difference value between each reference voltage and a target voltage, then, obtaining a third signal according to the voltage difference value, wherein a signal value in the third signal is related to the voltage difference value, and finally, performing bit-wise AND on the third signal and the first signal to obtain a second signal.

For example, in this embodiment, a set of CA signals may be generated as a third signal based on the voltage difference, which may be referred to as lpddr5_if.ca_valid signal, the signal values in the lpddr5_if.ca_valid signal are determined based on the determination, and then the lpddr5_if.ca_valid signal and the first signal are bitwise and to obtain a second signal that can be provided to the simulation model.

Specifically, in this embodiment, the absolute value corresponding to the voltage difference may be processed by using the sampling coefficient corresponding to the memory grain, so as to obtain the second period, so that the signal value of the second period in the third signal generated according to the second period is a specific value, that is, a preset target value. Therefore, in this embodiment, the third signal is bit-wise and the first signal to obtain the second signal.

It should be noted that, the signal value corresponding to the second period in the third signal is a preset target value, the preset target value may be denoted by X, and a specific numerical value may be set according to the service requirement. The period of time in which the eye width in the third signal is narrowed is represented by a period T2, in this embodiment, the sampling coefficient may be multiplied by an absolute value corresponding to the voltage difference to obtain a second period T2, based on which, in this embodiment, a corresponding third signal is generated, and then bit-wise summed with the first signal to obtain a second signal.

It can be seen that, in this embodiment, the third signal may be generated based on the reference voltage and the target voltage, and then the third signal and the first signal are bit-wise and, so as to obtain the second signal with the changed eye width.

For example, as shown in fig. 4, in this embodiment, V1 and V3 may be subjected to difference, a third signal with a signal value X in the period of T2 is generated according to a voltage difference, the third signal and the CA signal are subjected to bit-wise and thus obtain a second signal with a different eye width with respect to the CA signal, V2 and V3 are subjected to difference, a third signal with a signal value X in the period of T2 is generated according to a voltage difference, the third signal and the CA signal are subjected to bit-wise and thus obtain a second signal with a different eye width with respect to the second signal corresponding to the CA signal and V1, V3 and V3 are subjected to difference, a third signal with a signal value X in the period of T2 is generated according to a voltage difference (0), the third signal with a signal value X in the period of T2 is subjected to bit-wise and thus obtain a second signal with respect to the CA signal and a second signal with a different eye width with respect to the second signal corresponding to the CA signal in the period of V1 and V2 (in other embodiments, the CA signal is not adjusted with respect to the same reference voltage value of GV), and V4 and V3 is subjected to voltage difference, and thus obtain a signal with a value X in the period of V2 and thus different eye width with respect to the second signal with a value X in the period of V2. Based on this, after these second signals are transmitted to the simulation model of the memory particle in this way, the simulation model can capture the second signals with varying eye widths, and then select the standard voltage from the reference voltages V1 to Vn according to the eye width parameters of these second signals through the voltage configuration algorithm, compare it with the target voltage, if the standard voltage is consistent with the GV, for example, V3, it can be determined that the voltage configuration algorithm can accurately select the correct standard voltage, and if the standard voltage is inconsistent with the GV, it can be determined that the voltage configuration algorithm cannot accurately select the correct standard voltage.

Referring to fig. 5, a schematic structural diagram of a verification device for a voltage configuration algorithm according to an embodiment of the present application may be deployed in an electronic device, such as a computer or a server, capable of being connected to a simulation model corresponding to a memory granule, where the memory granule may be an LPDDR5 memory granule, and has a voltage configuration algorithm CBT tracking. The technical scheme in the embodiment is mainly used for improving the reliability of verifying the voltage configuration algorithm.

Specifically, the apparatus in this embodiment may include the following units:

a reference obtaining unit 501, configured to obtain a plurality of reference voltages of a voltage configuration algorithm in which the memory particles are deployed;

a target determining unit 502 for determining a target voltage from the plurality of reference voltages;

a signal obtaining unit 503, configured to adjust a signal value corresponding to a partial period in the first signal according to the target voltage and the plurality of reference voltages, so as to obtain a second signal;

a signal transmission unit 504, configured to obtain a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal;

and the algorithm verification unit 505 is configured to obtain a verification result according to the standard voltage and the target voltage, where the verification result characterizes whether the voltage configuration algorithm is accurate.

According to the technical scheme, in the verification device of the voltage configuration algorithm provided by the embodiment of the application, after the multiple reference voltages of the voltage configuration algorithm deployed by the memory particles are obtained, the signals provided for the voltage configuration algorithm can be adjusted according to the target voltage selected from the reference voltages and each other reference voltage, so that the signals used by the voltage configuration algorithm can be actively changed, the voltage configuration algorithm can select the standard voltage from the reference voltages according to the different signals, and further, the verification result representing whether the voltage configuration algorithm is accurate or not can be obtained according to the standard voltage and the target voltage.

In one implementation, the signal obtaining unit 503 is specifically configured to obtain a voltage difference between each of the reference voltages and the target voltage, and adjust a signal value corresponding to a part of the time periods in the first signal according to the voltage difference, so as to obtain the second signal. For example, the absolute value corresponding to the voltage difference is processed by using the sampling coefficient corresponding to the memory particle to obtain a first period, and the signal value corresponding to the first period in the first signal is adjusted to a preset target value to obtain a second signal.

In one implementation, the signal obtaining unit 503 is specifically configured to obtain a voltage difference between each of the reference voltages and the target voltage, obtain a third signal according to the voltage difference, and perform bitwise and on the third signal and the first signal to obtain a second signal.

The signal obtaining unit 503 obtains the second period by processing the absolute value corresponding to the voltage difference value by using the sampling coefficient corresponding to the memory particle, so as to obtain the second period.

In one implementation, the algorithm verification unit 505 is specifically configured to compare the standard voltage with the target voltage, obtain an accurate verification result representing the voltage configuration algorithm if the standard voltage is consistent with the target voltage, and obtain an inaccurate verification result representing the voltage configuration algorithm if the standard voltage is inconsistent with the target voltage.

In one implementation manner, the voltage configuration algorithm obtains an eye width parameter corresponding to each reference voltage according to the second signal corresponding to each reference voltage, and determines the standard voltage from the plurality of reference voltages according to the eye width parameter, wherein the eye width parameter corresponding to the standard voltage is the largest among the eye width parameters corresponding to all the reference voltages.

In one implementation, the reference obtaining unit 501 is specifically configured to read, by a back-gate manner, a voltage configuration parameter corresponding to the voltage configuration algorithm at each rising edge of the clock signal, where the voltage configuration parameter includes a reference voltage corresponding to the rising edge.

It should be noted that, the specific implementation of each unit in this embodiment may refer to the corresponding content in the foregoing, which is not described in detail herein.

Referring to fig. 6, a schematic structural diagram of an electronic device according to an embodiment of the present application may include the following structures:

a memory 601 for storing a computer program and data resulting from the operation of said computer program;

a processor 602 for executing the computer program to implement:

determining a target voltage from the plurality of reference voltages;

According to the technical scheme, in the electronic device provided by the embodiment of the application, after the multiple reference voltages of the voltage configuration algorithm deployed by the memory particles are obtained, the signals provided for the voltage configuration algorithm can be adjusted according to the target voltage selected from the reference voltages and each other reference voltage, so that the signals used by the voltage configuration algorithm can be actively changed, the voltage configuration algorithm can select the standard voltage from the reference voltages according to the different signals, and further, the verification result representing whether the voltage configuration algorithm is accurate or not can be obtained according to the standard voltage and the target voltage.

Taking the scenario that the voltage configuration algorithm CBT tracking used by the LPDDR5 memory granule is verified as an example, the following illustrates the technical scheme of the present application:

First, CBT tracking of LPDDR5 contains CA VREF TRAINING, which aims to find the most appropriate VREF (CA). The CA VREF TRAINING algorithm written by the developer will try out a different VREF configuration, the reference voltage in the foregoing, to find an optimal VREF (CA) configuration to maximize the eye width of the CA signal. However, in a simulation environment, configuring VREF (CA) to different values does not actually affect the eye width of the CA signal. How to simulate the eye width change of the VREF (CA) according to the configuration value of the CA through a simulation environment without depending on the memory particles, and further, the correctness of the tracking algorithm is difficult to verify.

Aiming at the problems, the application provides the following technical scheme:

in the simulation environment, the CA signal of a part of time period is assigned as X according to the VREF value configured in CA VREF TRAINING, and the CA eye width change process is simulated, so that the correctness of CA VREF TRAINING is verified.

The following key points of the technical scheme of the application are as follows:

1. in the simulation environment, a set of CA signals, such as lpddr5_if.ca_valid, is added. The signal and the CA signal output by the LPDDR5 PHY are bit-wise and the second signal is obtained, and finally the second signal is sent to the LPDDR5 particle (simulation model).

2. The golden VREF value, i.e. the target voltage in the foregoing, is specified in the simulation environment, and is the VREF value that should be selected after CA VREF TRAINING algorithm is executed, i.e. the VREF value corresponding to the maximum CA eye width, and is assumed to be 8' b01010001.

3. After entering CA VREF TRAINING, the voltage configuration parameters of VREF, i.e., MR (Memory Register) register configuration, are read on each rising edge of the clock signal dficlk. Taking VREF for CA as an example, OP [6:0] of MR12 can be read by means of backdoor.

4. The currently configured VREF value (i.e., the reference voltage in the foregoing) is compared with the golden VREF value and multiplied by a sampling factor (assuming the value is step), and specifically, as in equation (1), the eye width to be adjusted is determined (that is, the value obtained by multiplying the sampling factor determines the change in eye width), and the lpddr5_if.ca_valid signal value of this part of the period is assigned as X, which simulates the process of changing the eye width of the CA signal.

t=|VREF-VREF_golden|×step (1)

Where vref_golden is the golden VREF value, VREF is the currently configured VREF value (i.e., the reference voltage in the foregoing), and t is the eye width that needs to be adjusted, i.e., the first period or the second period in the foregoing.

5. The LPDDR5 granule (simulation model) feeds back its received CA value to CA VREF TRAINING via pins, and the algorithm will look for which VREF value corresponds to the maximum CA eye width.

6. After the algorithm is run, the VREF result obtained by algorithm tracking is read and compared with the golden VREF value, and if the VREF result is equal to the golden VREF value, the algorithm is correct.

As shown in fig. 7, a flowchart of the algorithm verification method according to the present application is shown, and the flowchart is specifically as follows:

Step 701, designating a golden VREF value;

Step 702, entering CA VREF TRAINING of CBT training, and providing corresponding signals for CA VREF TRAINING through step 703 and step 704 so as to train CA VREF TRAINING a CA VREF result value along with the start of training of CA VREF TRAINING;

Step 703, reading the MR configuration of VREF at each dfi clk rising edge, judging whether the MR configuration is equal to the golden VREF value, if not, executing step 704, and if so, providing the CA signal to CA VREF TRAINING, executing step 705;

step 704, setting the time period of narrowing the eye width as |VREF-VREF_golden|×step, obtaining a second signal based on the set time period, providing the second signal to CA VREF TRAINING, and executing step 705;

Step 705, determining CA VREF TRAINING if the algorithm is finished, i.e. the reference voltages in the MR configuration of VREF are all read and accordingly provide a corresponding second signal to CA VREF TRAINING (i.e. used to change the signal eye width provided to CA VREF TRAINING), if not, performing step 703, if so, performing step 706;

Step 706, comparing VREF result values trained by CA VREF TRAINING algorithm (namely VREF result values determined according to all signal eye widths) with golden VREF values, if the VREF result values are the same, executing step 707, and if the VREF result values are not the same, executing step 708;

Step 707, obtaining a result of the algorithm verification passing (i.e. the algorithm is accurate);

Step 708, obtaining a result that the algorithm is not validated (i.e., the algorithm is inaccurate).

Wherein, as shown in fig. 8, in step 704, after the reference voltage is read according to the rising edge of the clock signal CK, the signal value of the period t for which the eye width in the CA signal is narrowed (i.e., |vref_vref_golden|×step) is set to X according to the voltage difference from the golden VREF, thereby obtaining the second signal ca_valid, thereby changing the signal eye width.

In summary, after the technical scheme of the application is adopted, the method has the following advantages:

first, the defects in the algorithm can be discovered in advance without waiting for the chip to return and then verify CA VREF TRAINING the algorithm.

Secondly, the simulation environment is an ideal environment and is not influenced by the outside, so that the CA eye widths corresponding to different VREF values can be certainly and accurately changed according to the setting, and the influence of different VREF configuration values on the CA eye widths can be reflected.

In addition, the configuration of the signal eye width is convenient in the simulation environment, and the method for changing the signal eye width corresponding to each gear is flexible.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of verifying a voltage configuration algorithm, comprising:

obtaining a plurality of reference voltages of a voltage configuration algorithm deployed in the memory grain;

determining a target voltage from the plurality of reference voltages;

According to the voltage difference, adjusting a signal value corresponding to a part of time period in the first signal to obtain second signals, wherein the signal eye width of each second signal is different from that of the first signal, and the signal eye width of each second signal is different;

obtaining a verification result according to the standard voltage and the target voltage, wherein the verification result represents whether the voltage configuration algorithm is accurate or not;

The voltage configuration algorithm obtains an eye width parameter corresponding to each reference voltage according to the second signal corresponding to each reference voltage, and determines the standard voltage from the plurality of reference voltages according to the eye width parameter;

and the eye width parameter corresponding to the standard voltage is the largest among the eye width parameters corresponding to all the reference voltages.

2. The method of claim 1, adjusting a signal value corresponding to a partial period in the first signal according to the voltage difference, comprising:

3. The method of claim 1, according to the voltage difference, adjusting a signal value corresponding to a partial period in the first signal to obtain a second signal, including:

Obtaining a third signal according to the voltage difference;

4. A method according to claim 3, wherein the signal value corresponding to the second period in the third signal is a preset target value;

wherein the second period is obtained by:

5. The method according to claim 1 or2, obtaining a verification result from the standard voltage and the target voltage, comprising:

comparing the standard voltage with the target voltage;

6. The method of claim 1 or 2, obtaining a plurality of reference voltages for a voltage configuration algorithm deployed in a memory granule, comprising:

and reading voltage configuration parameters corresponding to a voltage configuration algorithm deployed by the memory particles at each rising edge of the clock signal in a back gate mode, wherein the voltage configuration parameters comprise reference voltages corresponding to the rising edges.

7. A verification apparatus for a voltage configuration algorithm, comprising:

A reference obtaining unit for obtaining a plurality of reference voltages of a voltage configuration algorithm deployed in the memory grain;

The signal acquisition unit is used for acquiring a voltage difference value between each reference voltage and the target voltage, and adjusting a signal value corresponding to a part of time period in a first signal according to the voltage difference value to acquire a second signal, wherein the signal eye width of the second signal is different from that of the first signal, and the signal eye width of each second signal is different;

The algorithm verification unit is used for obtaining a verification result according to the standard voltage and the target voltage, and the verification result represents whether the voltage configuration algorithm is accurate or not;

8. An electronic device, comprising:

A processor for executing the computer program to implement:

determining a target voltage from the plurality of reference voltages;