CN114662427B

CN114662427B - Debugging method and device for logic system design

Info

Publication number: CN114662427B
Application number: CN202210220089.7A
Authority: CN
Inventors: 黄世杰
Original assignee: Xinhuazhang Technology Co ltd
Current assignee: Xinhuazhang Technology Co ltd
Priority date: 2022-03-08
Filing date: 2022-03-08
Publication date: 2023-07-18
Anticipated expiration: 2042-03-08
Also published as: CN114662427A

Abstract

The disclosure provides a debugging method and equipment for logic system design. The method comprises the following steps: reading a first log file, the first log file being obtained by simulating the logic system design in a first configuration, the first log file comprising first simulation information for a plurality of first simulation events, each first simulation event comprising at least one of a timing of the first simulation event, a plurality of signals in the first simulation event, or a value of the plurality of signals at the timing; extracting first simulation information of the plurality of first simulation events; and generating first waveform diagrams of target signals in the plurality of signals according to the first simulation information respectively, wherein the first log file is in a text format.

Description

Debugging method and device for logic system design

Technical Field

The disclosure relates to the technical field of chip design, and in particular relates to a debugging method and equipment for logic system design.

Background

In the design of logic systems, testing and verification of the logic system design is required. When a user verifies a logical system design, the user always needs to simulate the logical system design by using a simulation tool. The simulation tool validates the logic system design using a test platform (testbench). Thus, the logic system design under test in the simulation tool may also be referred to as a design under test (Design Under Test, DUT for short).

In general, a test platform may apply stimulus to a DUT according to a predetermined test case, read corresponding test results from the DUT, and generate a log (log) file. The user can judge whether the verification of the logic system design is successful or not according to the information of the log file.

Manual review of log files is very time consuming.

Disclosure of Invention

In view of this, the present disclosure proposes a method, apparatus and storage medium for debugging a logic system design.

In a first aspect of the present disclosure, a method for debugging a logic system design is provided, including: reading a first log file, the first log file being obtained by simulating the logic system design in a first configuration, the first log file comprising first simulation information for a plurality of first simulation events, each first simulation event comprising at least one of a timing of the first simulation event, a plurality of signals in the first simulation event, or a value of the plurality of signals at the timing; extracting first simulation information of the plurality of first simulation events; and generating first waveform diagrams of target signals in the plurality of signals according to the first simulation information respectively, wherein the first log file is in a text format.

In a second aspect of the present disclosure, there is provided a debugging device of a logic system design, including: a memory storing a computer program; and a processor configured to execute the computer program to implement the method as described in the first aspect.

In a third aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing a set of instructions of an electronic device for causing the electronic device to perform the method of the first aspect.

According to the debugging method and the debugging equipment for the logic system design, the log file is converted from the text format to the waveform diagram, and the waveform diagram is utilized to conduct machine learning, so that errors or abnormal points are preliminarily determined, and the burden of manually consulting the log file is reduced. As the processing of graphics by machine learning has become mature, the existing machine learning algorithm can be fully utilized by converting the log file in text format into waveform diagrams, and the advantage of machine learning in graphics processing can be exerted. Meanwhile, since recording and reading the waveform file in the simulation process is a very time-consuming operation, generating the waveform map from the log file may eliminate the need for additionally loading the waveform file, and errors or outliers may be quickly determined compared to recording and reading the waveform file.

On the other hand, in the test environment, not all signals can acquire the waveform diagram by loading waveforms, but the simulation results of all signals can be printed into the log file. Based on the method provided by the disclosure, the waveform diagram of the signal which cannot acquire the waveform diagram by loading the waveform can be generated.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure or the prior art, the following description will briefly introduce the drawings required for the embodiments or the prior art descriptions, and it is obvious that the drawings in the following description are merely the disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 shows a schematic structural diagram of an exemplary apparatus provided according to an embodiment of the present disclosure.

FIG. 2 illustrates a schematic diagram of an exemplary simulation tool and debug tool in accordance with an embodiment of the present disclosure.

Fig. 3A shows a partial schematic view of a first log file according to an embodiment of the present disclosure.

Fig. 3B illustrates a schematic diagram of a waveform diagram corresponding to a target signal in a first log file according to an embodiment of the present disclosure.

Fig. 4A shows a schematic diagram of training of a machine learning model according to an embodiment of the present disclosure.

FIG. 4B illustrates a schematic diagram of simulation results predicted using a machine learning model, according to an embodiment of the present disclosure.

Fig. 4C shows a schematic diagram of clustering multiple waveform diagrams according to an embodiment of the disclosure.

Fig. 5A shows a flowchart of an exemplary debugging method according to an embodiment of the present disclosure.

Fig. 5B shows a flowchart of yet another exemplary debugging method in accordance with an embodiment of the present disclosure.

Detailed Description

For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.

It is to be noted that unless otherwise defined, technical or scientific terms used in the present disclosure should be taken in a general sense as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Logic system designs (e.g., integrated circuit chip designs) require multiple verifications before being finalized for production. Verification of the logic system design may be accomplished through the use of one or more field programmable gate arrays (Field Programmable Gate Array, FPGAs) to simulate (emulate) the logic system design. The logical design system running the simulation on the FPGA may obtain log files for the user to view the simulation results.

In the process of executing the simulation, an error or an abnormality inevitably occurs, and at this time, a user is required to find an error or an abnormal point from the log file obtained by the simulation, and then the error or the abnormal point corresponds to the error in the design of the logic system. As described above, the task of finding an outlier from a log file is often performed manually by a user, which is time-consuming and laborious.

On the other hand, in the test environment, not all signals can acquire the waveform diagram by loading waveforms, but the simulation results of all signals can be printed into the log file. The debugging method of the logic system design can generate the waveform diagram of the signal which cannot acquire the waveform diagram in a waveform loading mode.

In view of the above, the disclosure provides a method and apparatus for debugging a logic system design.

Fig. 1 shows a schematic structural diagram of an exemplary device 100 according to an embodiment of the present disclosure.

The device 100 may be, for example, a host computer. The device 100 may include: processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110. Wherein the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 may be communicatively coupled to each other within the device 100 via a bus 110.

The processor 102 may be a central processing unit (Central Processing Unit, CPU), an image processor, a neural network processor, a microcontroller, a programmable logic device, a digital signal processor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the techniques described in this disclosure. In some embodiments, processor 102 may also include multiple processors integrated as a single logical component. As shown in fig. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, log files, etc.). For example, as shown in fig. 1, the stored data may include program instructions (e.g., program instructions for implementing the techniques of the present disclosure) as well as log files (e.g., memory 104 may store log files in a text format resulting from the simulation). The processor 102 may also access stored program instructions and log files and execute the program instructions to operate on the log files. The memory 104 may include a non-transitory computer readable storage medium, such as a volatile storage device or a non-volatile storage device. In some embodiments, memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSD), flash memory, memory sticks, and the like.

The network interface 106 may be configured to enable the apparatus 100 to communicate with one or more other external devices via a network. The network may be any wired or wireless network capable of transmitting and/or receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the foregoing. It will be appreciated that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, receivers, modems, routers, gateways, adapters, cellular network chips, etc.

Peripheral interface 108 may be configured to connect apparatus 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, various types of sensors, and output devices such as displays, speakers, vibrators, indicator lights, and the like.

Bus 110 may be configured to transfer information between the various components of device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), and may be, for example, an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), etc.

In some embodiments, device 100 may include, in addition to processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110 shown in fig. 1 and described above, one or more other components necessary to achieve proper operation and/or to achieve the solutions of embodiments of the present disclosure. In some embodiments, the device 100 may not include one or more of the components shown in fig. 1.

It should be noted that, although the above-described architecture of the apparatus 100 only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in the implementation, the architecture of the apparatus 100 may also include other components necessary to achieve normal operation. Moreover, those skilled in the art will appreciate that the constituent architecture of the apparatus 100 may include only the components necessary to implement the embodiments of the present disclosure, and not all the components shown in the drawings.

FIG. 2 shows a schematic diagram of an exemplary simulation tool 202 and debug tool 200 in accordance with an embodiment of the present disclosure. The emulation tool 202 and the debug tool 200 may be computer programs running on the device 100.

In the field of chip design, a design may be simulated, typically with simulation tools. The simulation tool may be, for example, a GalaxSim simulation tool available from Kagaku Co., ltd. The exemplary simulation tool 202 illustrated in FIG. 2 may include a compiler 120 and a simulator 220. Compiler 120 may compile logical system design 210 into object code 204, and simulator 220 may simulate based on object code 204 and output simulation results 206. For example, the simulation tool 202 may output the simulation results 206 (e.g., log files resulting from the simulation) onto an output device (e.g., displayed on a display) via the peripheral interface 108 of fig. 1.

Debug tool 200 may also read simulation results 206. For example, debug tool 200 may read simulation results 206 stored in log files for debugging. Debug tool 200 may also read a description of logic system design 210 (typically SystemVerilog and Verilog code) and display (e.g., via the output device of fig. 1) to the user. Debug tool 200 may also generate various graphical interfaces to facilitate the user's debugging efforts. The user may issue a debug command 208 to the debug tool 200 (e.g., running the validation system 210 to a certain time), which the debug tool 200 then applies to the simulation tool 202 to execute accordingly.

It is understood that in addition to interfacing with a software emulation tool (e.g., galaxsim), debug tool 200 may also interface with a hardware emulation tool (emulgator) for debugging.

Fig. 3A shows a partial schematic diagram of a first log file 300 according to an embodiment of the present disclosure. It will be appreciated that for a clearer illustration, the first log file 300 shown in FIG. 3A includes only a portion of simulation information.

In some embodiments, a user may perform simulation operations on a logical system design in a first configuration using simulation tool 202. Simulation of the logic system design may be performed under different configurations. The configuration (e.g., first configuration) in the present disclosure may include environmental parameters, a description of a logical system design, or configuration and parameters of a simulation tool, etc. After the simulation is completed, the simulation tool 202 may output the first log file 300 as the simulation result 206. The first log file 300 may be stored in a text format in the memory 104 of the device 100 for reading and further processing by the debug tool 200.

As shown in fig. 3A, the first log file 300 may include first simulation information (e.g., simulation information 301) of a plurality of first simulation events (e.g., simulation events 310 and 320). The first simulation information may include a timing of the first simulation event (e.g., "begin_time" in the simulation event 310), a plurality of signals in the first simulation event (e.g., signal "a" and signal "b" in the simulation event 310), or values of the plurality of signals at respective timings (e.g., "value" in the simulation event 310), and the like.

Accordingly, the debugging tool 200 may extract the above simulation information of the plurality of simulation events from the read first log file 300.

In some embodiments, multiple signals are included in the simulation event 310, one of which a user may select as a target signal (e.g., signal "a").

Fig. 3B shows a schematic diagram of a waveform diagram 302 corresponding to the target signal "a" in the first log file 300 according to an embodiment of the present disclosure.

In some embodiments, the debug tool 200 may read simulation information related to the target signal "a" in the plurality of simulation events (e.g., "begin_time", "value" of the target signal in each simulation event) from the first log file 300 and draw a waveform graph according to the simulation information. For example, the debug tool 200 may have the timing "begin_time" as the horizontal axis and the Value "of the target signal" a "at the corresponding timing as the vertical axis, thereby generating the waveform diagram. The horizontal axis of the waveform chart represents time, and the vertical axis represents a numerical value. The waveform diagram corresponds to a simulation result of the target signal "a" in the first log file 300 running in time series.

In some embodiments, the debug tool 200 may generate the waveform map directly from the first log file 300. In some embodiments, debug tool 200 may store emulation information related to target signal "a" as waveform data as a waveform file in a particular waveform data format. When it is desired to generate a waveform diagram, debug tool 200 may read the waveform file and generate the waveform diagram from the waveform data in the waveform file.

Thus, the debug tool 200 can generate a waveform diagram of the target signal "a" in the first configuration from the first log file 300.

It is understood that the debug tool 200 may also generate a plurality of waveforms for other signals in the first configuration from the first log file 300.

In some embodiments, the user may also perform simulation operations on the logic system design in the second configuration using the simulation tool 202. After the simulation is complete, the simulation tool 202 may output the second log file as the simulation result 206. Wherein the simulation event of the second log file includes the same target signal "a" as in the first log file 300. The debug tool 200 may read the second log file, extract emulation information (e.g., "begin_time", "value" of the target signal "a" in each emulation event) related to the target signal "a" from the plurality of emulation events, and draw a second waveform diagram according to the emulation information.

It is understood that the above described debugging tool 200 reads the first log file and the second log file to generate the waveform diagram is merely an example. Debug tool 200 may also read log files in other configurations to generate a plurality of waveform diagrams corresponding to a plurality of signals in the log file.

Fig. 4A illustrates a schematic diagram of training 400 of a machine learning model according to an embodiment of the present disclosure.

As described above, debug tool 200 may generate a plurality of waveform maps corresponding to a plurality of signals in the log file. In some embodiments, a user may generate a plurality of waveform diagrams for a plurality of signals based on historical debug data and log files. Still further, debug tool 200 may determine simulation results (e.g., simulation success or simulation failure) for each simulation event from historical debug data and use the simulation results and corresponding waveform patterns for training of the machine learning model.

In some embodiments, debug tool 200 may employ the methods described above to generate a waveform of a target signal (e.g., signal "a") (e.g., waveform 302 generated in fig. 3B and further generated waveforms 408, 410, etc.), and receive simulation results (e.g., simulation results 402, 404, 406, etc.) corresponding to the waveform from, for example, a user. Simulation results may include simulation success or simulation failure. In some embodiments, training is performed using simulation results of simulation success and corresponding waveform diagrams.

In some embodiments, debug tool 200 may train a machine learning model based on the generated waveforms and simulation results corresponding to those waveforms, resulting in machine learning model 422 corresponding to the target signal (e.g., signal "a"). In some embodiments, machine learning model 422 may be a common feature of extracting waveform graphs for which simulation results are successful. If the new waveform diagram features accord with the common features in the first machine learning model, determining that the simulation result is successful; if the new waveform diagram features do not conform to the common features in the first machine learning model, determining that the simulation result is failure.

It will be appreciated that the waveform diagrams 302, 408, and 410 of the target signals and the simulation results 402, 404, and 406 corresponding to the waveform diagrams shown in the embodiments are merely examples. In actual implementation, the debug tool 200 may also generate a number of waveform patterns and receive simulation results corresponding to the waveform patterns for training a machine learning model corresponding to the target signal.

It will be appreciated that the commissioning tool 200 may also train a machine learning model corresponding to other target signals.

Fig. 4B shows a schematic diagram of simulation results using machine learning model prediction 410, according to an embodiment of the present disclosure.

In some embodiments, a user may perform simulation operations on a logical system design with the simulation tool 202 in a different configuration than during the training phase of the machine learning model. After the simulation is complete, the simulation tool 202 may output a log file of the simulation. Wherein the simulation event of the log file includes the same target signal "a" as in the log file 300. Debug tool 200 may read the log file and generate waveform graph 412.

In some embodiments, debug tool 200 processes waveform 412 using trained machine learning model 422 corresponding to target signal "a" to obtain predicted simulation results 408. In some embodiments, simulation results 408 may indicate that waveform 412 has a failure event. Machine learning model 422 may determine that a "graphic error" exists for a segment or a graphic in waveform map 412 and further locate the timing of the graphic error. In this way, the user can find a failure event from among the plurality of simulation events in the log file according to the given timing.

It will be appreciated that debug tool 200 may also process the waveform patterns of other target signals using a plurality of machine learning models corresponding to the other target signals after training to determine whether a failure event exists.

As described above, the debug tool 200 may find a waveform map in which a failure event may exist using a machine learning model corresponding to the target signal. In general, simulation of a single logic system design may produce multiple waveform patterns with failure events. Using a machine learning model, debug tool 200 may identify a very large number of failure events. And some of these failure events may be caused by the same error source (e.g., design error). Although the machine learning model trained in embodiments of the present disclosure cannot accurately determine what error sources are in particular, failure events caused by the same error source may exhibit some of the same features on the waveform map. It is difficult for a human to find these same features by observing multiple oscillograms, however these same features can be obtained via machine learning processing of the oscillograms, thereby clustering multiple oscillograms with the same features, i.e. clustering failure events caused by the same error source. In this way, the efficiency with which a user (e.g., a verification engineer) performs debugging can be improved.

Fig. 4C shows a schematic diagram of clustering 420 a plurality of waveform diagrams according to an embodiment of the disclosure. Debug tool 200 may extract the graphical features of the plurality of oscillograms for clustering 420. In some embodiments, the graphical features of the waveform map may be generated in a stage of prediction 410. In some embodiments, the graphical features of the waveform map may be generated by debug tool 200 otherwise from the waveform map.

The extracted graphic features may be one or more. The plurality of graphical features may form a feature vector for subsequent processing.

The debug tool 200 may cluster 420 the plurality of oscillograms according to the graphical features. Clustering 420 may employ a combination of one or more of the following methods: k-means, mean shift clustering, density-based clustering methods, and the like. It will be appreciated that the above clustering method is merely exemplary, and those skilled in the art may select an appropriate clustering method according to actual needs without being limited to the above example.

As shown in fig. 4C, the plurality of waveforms may be clustered into at least one group (e.g., group 1, group 2, group 3, and group 4, the waveforms within the group being represented by small dots).

Thus, the embodiment of the disclosure reduces the burden of manually consulting the log file by converting the log file from a text format to a waveform diagram and performing machine learning by using the waveform diagram, thereby preliminarily determining errors or abnormal points. Meanwhile, generating the waveform diagram from the log file may eliminate the need for additional loading of the waveform file, and thus an error or outlier may be quickly determined compared to recording and reading the waveform file. Still further, some of these errors or outliers may be caused by the same error source and may exhibit some of the same characteristics on the waveform map. These same features may be obtained via a machine learning process of waveform graphs, thereby clustering multiple waveform graphs having the same features, i.e., failure events caused by the same error source. In this way, the efficiency of user commissioning can be improved.

FIG. 5A illustrates a flow chart of a method 500 of debugging a logic system design in accordance with an embodiment of the present disclosure. Method 500 may be performed by, for example, device 100 of fig. 1, and more particularly, by debug tool 200 running on device 100. The method 500 may include the following steps.

In step S501, the debug tool 200 may read a first log file (e.g. the first log file 300 shown in fig. 3A). The first log file may be obtained by simulating a logic system design (e.g., logic system design 210 in FIG. 2) in a first configuration. As described above, the configuration (e.g., the first configuration) in the present disclosure may include environmental parameters, a description of a logical system design, or configuration and parameters of a simulation tool, etc. The first log file includes first simulation information (e.g., simulation information 301 in FIG. 3A) of a plurality of first simulation events (e.g., simulation events 310 and 320 in FIG. 3A). Each first simulation event may include at least one of a timing of the first simulation event (e.g., "begin_time" in simulation event 310 in fig. 3A), a plurality of signals in the first simulation event (e.g., signal "a" and signal "b" in simulation event 310 in fig. 3A), or a Value of the plurality of signals at the respective timing (e.g., "Value" in simulation event 310 in fig. 3A). The debug tool 200 may instruct the simulation tool 202 to simulate the design and obtain simulation results (e.g., the first log file 300, etc.).

Wherein the first log file is stored in a memory (e.g., memory 104 in fig. 1) in a text format.

In step S502, the debug tool 200 may extract the first simulation information from the read first log file. The first simulation information may include, for example, corresponding values of the target signal at a plurality of timings.

In step S503, the debug tool 200 may generate a waveform diagram (e.g. waveform diagram 302 of fig. 3B) of a target signal (e.g. signal "a" in fig. 3A) of the plurality of signals, respectively, according to the first simulation information (e.g. simulation information 301).

In some embodiments, debug tool 200 may generate a waveform graph (e.g., waveform graph 302 shown in FIG. 3B) with a time sequence (e.g., "begin_time" in emulation event 310 in FIG. 3A) as the horizontal axis and a Value of the corresponding time sequence (e.g., "Value" in emulation event 310 in FIG. 3A) as the vertical axis. In some embodiments, the waveform map may be stored in the form of waveform data.

In some embodiments, the waveform map may be stored in a waveform database.

In step S504, debug tool 200 may read a second log file obtained by emulating the logical system design in a second configuration. It will be appreciated that the second configuration is different from the first configuration. A second waveform map of the target signal may be generated based on the second log file. The debug tool 200 performs steps S502 to S503 for the second log file to generate a second waveform diagram (for example, waveform diagram 408 in fig. 4A) of the target signal "a".

In step S505, the debug tool 200 may receive a first simulation result in a first configuration (e.g. simulation result 402 in fig. 4A) and a second simulation result in a second configuration (e.g. simulation result 404 in fig. 4A). Wherein the first and second waveforms (e.g., waveforms 302, 408 in fig. 4A) correspond to the first and second simulation results (e.g., simulation results 402, 404 in fig. 4A), respectively. Simulation results may include simulation success or simulation failure. It is understood that debug tool 200 may generate more waveform diagrams and receive simulation results corresponding to those waveform diagrams.

In step S506, the debug tool 200 may train a first machine learning model (e.g. learning model 422 of fig. 4A) corresponding to the target signal based at least on the first and second waveform diagrams (e.g. waveform diagrams 302, 408 of fig. 4A) and the first and second simulation results (e.g. simulation results 402, 404 of fig. 4A). The first machine learning model may be used to predict simulation results corresponding to one waveform map of the target signal.

In some embodiments, the first machine learning model may be trained based on a plurality of waveform diagrams for which simulation results are successful. It is understood that for different signals, debug tool 200 may generate a plurality of machine learning models corresponding to the plurality of signals, respectively. How to predict simulation results using the first machine learning model will be further described below.

Fig. 5B illustrates a flowchart of a further exemplary debug method 510, according to an embodiment of the present disclosure. Method 510 may be performed by device 100 of fig. 1, for example, and more specifically, by debug tool 200 running on device 100. It is to be appreciated that method 510 may be performed as a stand-alone method or as part of method 500. The method 510 may include the following steps.

In step S511, the debug tool 200 may read the third log file. The third log file is obtained by simulating a logic system design in a third configuration. In some embodiments, the third configuration is different from the first and second configurations. A third waveform map of the target signal (e.g., signal "a") may be generated based on the third log file. The debug tool 200 may perform steps S502 through S503 in the method 500 for the third log file, generating a third waveform diagram (e.g. waveform diagram 412 in fig. 4B) of the target signal "a".

In step S512, the debug tool 200 may determine a third simulation result (e.g. simulation result 408 in fig. 4B) in a third configuration based on the third waveform diagram (e.g. waveform diagram 412 in fig. 4B) using the first machine learning model (e.g. machine learning model 422 in fig. 4A). In some embodiments, simulation results 408 may indicate that waveform 412 has a failure event.

In step S513, in response to determining that the third simulation result (e.g., simulation result 408 in fig. 4B) is a failure, debug tool 200 may determine a third failure event among the plurality of third simulation events.

In some embodiments, methods 500 and 510 may be performed multiple times such that debug tool 200 may generate multiple waveforms for multiple signals based on the third log file, process the multiple waveforms using multiple machine learning models, and determine multiple target waveforms in the multiple waveforms for which a failure event is present.

In some embodiments, debug tool 200 may also cluster multiple target waveforms to cluster the multiple target waveforms into at least one group, each of the at least one group indicating one error source that caused the failure event.

Further, some of the failure events described above may be caused by the same error source (e.g., design error). Although the machine learning model trained in embodiments of the present disclosure cannot accurately determine what error sources are in particular, failure events caused by the same error source may exhibit some of the same features on the waveform map. The debug tool 200 may cluster a plurality of target waveforms to cluster the plurality of target waveforms into at least one group, each of the at least one group corresponding to one error source that caused the failure event. In some embodiments, clustering may employ a combination of one or more of, for example, K-means, mean shift clustering, density-based clustering methods, and the like.

The disclosure also provides a debugging device for the logic system design. The device may be the device 100 shown in fig. 1. Debug tool 200 may be configured to execute a computer program stored in memory 104 to implement a debugging method of a logic system design consistent with the present disclosure, such as one of the exemplary methods described above (e.g. method 500 shown in fig. 5A or method 510 shown in fig. 5B). And will not be described in detail herein.

The present disclosure also provides a non-transitory computer readable storage medium. The non-transitory computer readable storage medium stores a computer program. When executed by the debug tool 200, the computer program causes the debug tool to implement a debug method of a logic system design consistent with the present disclosure, such as one of the exemplary methods described above (e.g. method 500 shown in fig. 5A or method 510 shown in fig. 5B). And will not be described in detail herein.

The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.

The foregoing has described certain embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the disclosure, including the claims, is limited to these examples; the technical features of the above embodiments or in different embodiments may also be combined under the idea of the present disclosure, the steps may be implemented in any order, and there are many other variations of the different aspects of the present disclosure as described above, which are not provided in details for the sake of brevity.

Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the present disclosure. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the present disclosure, and this also takes into account the fact that specifics with respect to the implementation of such block diagram devices are highly dependent upon the platform on which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

The present disclosure is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalents, improvements and the like that may be made within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. A method of debugging a logic system design, comprising:

reading a first log file, the first log file being obtained by simulating the logic system design in a first configuration, the first log file comprising first simulation information for a plurality of first simulation events, the first simulation information for each of the first simulation events comprising at least one of a timing of the first simulation event, a plurality of signals in the first simulation event, or a value of the plurality of signals at the timing;

extracting first simulation information of the plurality of first simulation events; and

and respectively generating first waveform diagrams of target signals in the plurality of signals according to the first simulation information, wherein the first log file is in a text format.

2. The debugging method of claim 1, further comprising:

reading a second log file, wherein the second log file is obtained by simulating the logic system design under a second configuration;

generating a second waveform map of the target signal based on the second log file;

receiving a first simulation result under the first configuration and a second simulation result under the second configuration;

a first machine learning model corresponding to the target signal is trained based at least on the first and second waveform diagrams and the first and second simulation results.

3. The debugging method of claim 2, further comprising:

reading a third log file, wherein the third log file is obtained by simulating the logic system design under a third configuration;

generating a third waveform diagram of the target signal based on the third log file;

a third simulation result in the third configuration is determined based on the third waveform diagram using the first machine learning model.

4. The debugging method of claim 3, wherein the third log file comprises a plurality of third simulation events, the debugging method further comprising:

in response to determining that the third simulation result is a failure, a third failure event is determined among the plurality of third simulation events.

5. The debugging method of claim 4, further comprising:

generating a plurality of machine learning models corresponding to the plurality of signals;

generating a plurality of waveform diagrams of the plurality of signals based on the third log file;

processing the plurality of waveform maps using the plurality of machine learning models; and

a plurality of target waveform patterns in which a failure event exists is determined among the plurality of waveform patterns.

6. The debugging method of claim 5, further comprising:

the plurality of target waveforms is clustered to cluster the target waveforms into at least one group, each of the at least one group corresponding to one error source that caused the failure event.

7. The debugging method of claim 1, wherein the timing of the first simulation event comprises a start time of the target signal.

8. A debugging apparatus of a logic system design, comprising:

a memory storing a computer program; and

a processor configured to execute the computer program to implement the method of any one of claims 1 to 7.

9. A non-transitory computer readable storage medium storing a set of instructions for an electronic device for causing the electronic device to perform the method of any one of claims 1-7.