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CN119201838B - A method for managing out-of-order reception of RapidIO Message transactions based on FPGA - Google Patents

A method for managing out-of-order reception of RapidIO Message transactions based on FPGA Download PDF

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CN119201838B
CN119201838B CN202411702503.3A CN202411702503A CN119201838B CN 119201838 B CN119201838 B CN 119201838B CN 202411702503 A CN202411702503 A CN 202411702503A CN 119201838 B CN119201838 B CN 119201838B
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data
rapidio
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sram
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CN119201838A (en
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叶明�
曹兴
万波
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Chengdu Xuanjili Communication Technology Co ltd
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

本发明公开了一种基于FPGA的RapidIO Message事务的乱序接收管理方法，涉及通信技术领域，用于改善源节点间的竞争导致数据堵塞问题，包括接收RapidIO事务包传入RapidIO驱动模块，在RapidIO驱动模块中，对RapidIO接口进行跨时钟域处理使得不同时钟域中的数据传输趋于同步，跨时钟域处理后对Message事务包进行缓存，对Message事务包进行协议解析，获取Message事务包解析后的分帧数据，输出解析后的Message分帧数据，对Message分帧数据进行缓存后对SRAM缓存通道进行仲裁，获取匹配的SRAM缓存通道，将Message分帧数据写入对应通道，将SRAM缓存地址与Message分帧的分片偏移进行映射处理，将分帧数据写入SRAM模块的对应空间，从而完成Message分帧的自动排序，降低各源节点间竞争导致的Message事务包重传乱序引发的通信故障问题。

The invention discloses a disordered receiving management method of RapidIO Message transactions based on FPGA, relates to the technical field of communication, and is used to improve the problem of data congestion caused by competition between source nodes. The method comprises the following steps: receiving a RapidIO transaction packet and transmitting it into a RapidIO driver module; in the RapidIO driver module, performing cross-clock domain processing on a RapidIO interface so that data transmission in different clock domains tends to be synchronized; caching the Message transaction packet after the cross-clock domain processing; performing protocol parsing on the Message transaction packet, obtaining framed data after the parsing of the Message transaction packet; outputting the parsed Message framed data; arbitrating an SRAM cache channel after caching the Message framed data, obtaining a matching SRAM cache channel, writing the Message framed data into a corresponding channel, mapping an SRAM cache address with a fragment offset of the Message frame, and writing the framed data into a corresponding space of the SRAM module, thereby completing automatic sorting of the Message frame and reducing the communication failure problem caused by disordered retransmission of the Message transaction packet caused by competition between source nodes.

Description

Disorder receiving management method of rapidIO Message transaction based on FPGA
Technical Field
The invention relates to the technical field of communication, in particular to an out-of-order receiving management method of rapidIO Message transactions based on an FPGA.
Background
Along with the high-speed development of information technology, the embedded high-speed interconnection technology based on rapidIO has been widely applied to various fields such as radar, communication, remote sensing and the like. As an open interconnection technical standard, rapidIO supports NWR, NREAD, SWR, doorBell, message and other transaction applications.
In Message transaction application, the length of a single Message supported by RapidIO is 4096 bytes, and a maximum of 16 packets can be divided into 16 packets for carrying out sliced data transmission, each packet is 256 bytes at maximum, and each packet is distinguished by the number of slices and a slice offset field. The RapidIO protocol allows individual tiles of a Message transaction to be sent or received out of order. In a large RapidIO switching system, when Message transactions are sent to a single node at high speed through multiple nodes, competition can occur among source nodes, data blocking can occur to nodes which do not acquire transmission rights, the probability of unordered transmission is increased, a destination node can receive unordered Message transaction packets, and communication faults can be caused if ordering cannot be performed.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks of the prior art, an embodiment of the present invention provides an out-of-order receiving management method for RapidIO Message transactions based on FPGA, which solves the problems set forth in the above-mentioned background art by performing simultaneous receiving and ordering on Message data of a plurality of different source nodes.
In order to achieve the above purpose, the present invention provides the following technical solutions:
An out-of-order receiving management method of rapidIO Message transactions based on FPGA comprises the following steps:
step S1, receiving a rapidIO transaction packet and entering a rapidIO driving module, performing cross-clock processing on a rapidIO interface and caching a Message transaction packet;
Step S2, carrying out protocol analysis on the Message transaction package, processing the analyzed Message transaction data to obtain Message framing data, triggering a Message response request, and carrying out package output according to the Message response request;
step S3, arbitrating the SRAM buffer channel, and writing Message framing data into the corresponding channel;
Step S4, mapping the SRAM buffer address and the fragment offset of the Message framing one by one, and writing framing data into a corresponding space of the SRAM module to complete automatic sequencing of the Message framing;
the SRAM cache is a high-performance memory for temporarily storing data, the rapidIO is a high-performance serial communication protocol for embedded systems and high-performance computing environments, message transactions are Message transactions, and the IP interface is an interface for data communication between equipment and a network and is used for information interaction operation.
In a preferred embodiment, the method for out-of-order receiving and managing the RapidIO Message transaction based on the FPGA mainly comprises three modules, namely a RapidIO IP interface module, a RapidIO driving module and a multichannel sequencing module.
The rapidIO IP interface module is used for completing bottom layer sending and receiving of the rapidIO transaction packet;
The rapidIO driving module is used for completing protocol analysis of the rapidIO transaction packet and giving a response to a request packet requiring the response;
The multi-channel ordering module is used for completing the ordering and combining of Message transaction data from different source nodes and outputting complete Message frame data after the ordering and combining is completed.
In a preferred implementation manner, the rapidIO driving module comprises three modules, namely an AXI FIFO buffer module, a Message request transaction analysis module and a Message response transaction group package module;
the rapidIO driving module analyzes the protocol of the received Message transaction and gives a Message request transaction response;
the AXI FIFO buffer module is used for cross-clock domain processing of the RapidIO interface and buffering the Message transaction packet;
The Message request transaction analysis module is used for carrying out protocol analysis on the Message request transaction and outputting Message framing parameters;
The Message response transaction grouping module is used for responding to the Message request transaction and performing grouping and sending according to a Message response frame format.
In a preferred embodiment, in step S1, the AXI FIFO buffer module performs the clock domain crossing processing on the RapidIO interface as follows:
Identifying clock domains, namely acquiring data and frequency of each clock domain, and determining data and interfaces transmitted across the clock domains;
The clock domain crossing is realized by using an AXI FIFO with asynchronous and independent clocks, the data and clock interfaces between different clock domains are butted, and simultaneously, the data is captured by using a double-edge trigger at a receiving end, so that the occurrence rate of time sequence problems of data sampling is reduced;
Determining the head and effective load of data package, and controlling the data sending and receiving process by existing state machine;
data synchronization, namely using a synchronizer to ensure that received data can be stabilized in a new clock domain;
And data caching, namely caching the data packet in the new clock domain.
In a preferred embodiment, in step S2, the Message request transaction parsing module performs protocol parsing on the Message transaction packet and processes the parsed Message transaction data as follows:
Obtaining a rapidIO transaction packet, namely reading an original rapidIO transaction packet through a Serial RapidIO Gen IP interface;
Analyzing the payload, namely extracting payload data according to the header information;
checking the tail information to ensure that the rapidIO transaction packet is free from errors in the transmission process;
Frame processing, namely processing the parsed Message transaction data to obtain frame parameters, wherein the frame processing comprises the following steps of:
msg_id, msg_len, msg_seg, msg_data, msg_data_val, msg_data_last, which are Message source ID, message fragment number, message fragment offset, message data valid, and Message data end flag, respectively.
In a preferred embodiment, in step S2, each framing parameter corresponds to framing data in the Message transaction packet, and after framing, the Message response request is triggered;
After receiving the Message response request, the Message response transaction group packet module generates a corresponding Message response transaction packet and sends the Message response transaction packet to the AXI FIFO buffer module, and the AXI FIFO buffer module caches and processes the Message response transaction packet across clock domains and outputs the Message response transaction packet to the Serial RapidIO Gen IP interface for sending.
In a preferred embodiment, in step S3, the multi-channel sorting module includes a FIFO buffer module, a channel arbitration module, an SRAM buffer control module, an SRAM buffer module, and a Message output control module;
The FIFO buffer module is used for buffering the Message frames;
The channel arbitration module is used for arbitrating the SRAM buffer channel, inputting the Message framing data into the corresponding SRAM buffer channel for arbitration, and the arbitration steps are as follows:
after receiving new Message framing data, polling occupy _st register of SRAM buffer module, if there is msg_id and occupy _id of Message framing in occupied SRAM buffer module, writing the Message framing data into corresponding SRAM buffer channel, otherwise applying for new SRAM buffer channel, assigning msg_id of Message framing to occupy _id of SRAM, and writing Message framing data into new buffer channel.
In a preferred embodiment, in step S4, the SRAM buffer control module is configured to write Message frame data of the same Message source ID to a corresponding address of the SRAM module, and allocate a plurality of parameters for state management of the SRAM module, including:
occupy _id, ocupy_st, msg_rlen, msg_rdata, msg_rcnt, which are SRAM_taken ID, SRAM_taken state, message full frame actual length, message full frame data, message full frame fragment count, respectively;
occupy _id is used for inquiring whether Message framing data from the same source node is written into a corresponding channel;
occupy _st is used to query the current occupancy state of the SRAM, marking the idle state as occupy _st [1:0] =2' b00;
The occupancy state is marked occupy _st [1:0] =2' b01;
marking the packet completion status as occupy _st [1:0] =2' b10;
the Message output state is marked occupy _st [1:0] =2' b11;
msg_rcnt is used for counting the complete frame fragments of the Message, and the count value of msg_rcnt is increased by 1 every time one frame of the Message fragments is written.
In a preferred embodiment, in step S4, when the Message frame storage is completed, the msg_rcnt value for the Message frame statistics count is increased by 1, and when it is detected that the Message frame statistics count msg_rcnt is equal to the number of fragments of the Message frames msg_len, the SRAM occupied state is set to occupy _st [1:0] =2 'b10, the Message complete frame output is waited, the Message complete frame after the completion of the output is completed, the frame statistics count msg_rcnt is cleared, and the SRAM occupied state is set to occupy _st [1:0] =2' b00;
If the SRAM buffer channel occupied in the preset specified time is not completely ordered into packets, when a timeout interrupt is generated, the Message framing statistics count msg_rcnt is cleared, and the SRAM occupied state is occupy _st [1:0] =2' b00.
The invention discloses a method for managing out-of-order receiving of rapidIO Message transactions based on FPGA, which has the technical effects and advantages that:
According to the method, the device and the system, the rapidIO transaction packet is received and transmitted into the rapidIO driving module, in the rapidIO driving module, the rapidIO interface is subjected to cross-clock domain processing to enable data transmission in different clock domains to be synchronous, after the cross-clock domain processing, the Message transaction packet is buffered, the Message transaction packet is subjected to protocol analysis, frame data after the Message transaction packet analysis are obtained, the analyzed Message frame data are output, the Message frame data are buffered, then an SRAM buffer channel is arbitrated, the matched SRAM buffer channel is obtained, the Message frame data are written into the corresponding channel, the mapping processing is carried out on the SRAM buffer address and the fragment offset of the Message frame, and the frame data are written into the corresponding space of the SRAM module, so that the automatic sequencing of the Message frame is completed, and the problem of communication faults caused by Message transaction packet retransmission disorder caused by competition among source nodes is reduced.
Drawings
FIG. 1 is a schematic diagram of an out-of-order receiving management method for a rapidIO Message transaction based on an FPGA of the present invention,
FIG. 2 is a functional block diagram of FPGA logic of a method for out-of-order receive management of Rapid IO Message transactions based on an FPGA of the present invention,
FIG. 3 is a diagram of a RapidIO driving module of the method for out-of-order receiving and managing RapidIO Message transactions based on an FPGA of the present invention,
FIG. 4 is a multi-channel ordering module diagram of an out-of-order receiving management method of RapidIO Message transactions based on FPGA of the present invention,
FIG. 5 is a flow chart of a channel arbitration of an out-of-order receiving management method of RapidIO Message transactions based on FPGA of the present invention,
FIG. 6 is a schematic diagram of SRAM slicing ordering of a method for managing out-of-order receipt of RapidIO Message transactions based on an FPGA of the present invention,
Fig. 7 is a flowchart of an SRAM fragment packet of the method for managing out-of-order reception of RapidIO Message transactions based on an FPGA of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
According to the method, the device and the system, the rapidIO transaction packet is received and transmitted into the rapidIO driving module, in the rapidIO driving module, the rapidIO interface is subjected to cross-clock domain processing to enable data transmission in different clock domains to be synchronous, after the cross-clock domain processing, the Message transaction packet is buffered, the Message transaction packet is subjected to protocol analysis, frame data after the Message transaction packet analysis are obtained, the analyzed Message frame data are output, the Message frame data are buffered, then an SRAM buffer channel is arbitrated, the matched SRAM buffer channel is obtained, the Message frame data are written into the corresponding channel, the mapping processing is carried out on the SRAM buffer address and the fragment offset of the Message frame, and the frame data are written into the corresponding space of the SRAM module, so that the automatic sequencing of the Message frame is completed, and the problem of communication faults caused by Message transaction packet retransmission disorder caused by competition among source nodes is reduced.
An embodiment, as shown in fig. 1, of an out-of-order receiving management method for RapidIO Message transactions based on FPGA, includes the following steps:
step S1, receiving a rapidIO transaction packet and entering a rapidIO driving module, performing cross-clock processing on a rapidIO interface and caching a Message transaction packet;
Step S2, carrying out protocol analysis on the Message transaction package, processing the analyzed Message transaction data to obtain Message framing data, triggering a Message response request, and carrying out package output according to the Message response request;
step S3, arbitrating the SRAM buffer channel, and writing Message framing data into the corresponding channel;
And S4, mapping the SRAM buffer address and the fragment offset of the Message framing one by one, and writing framing data into a corresponding space of the SRAM module to complete automatic sequencing of the Message framing.
The specific implementation is as follows:
The method for out-of-order receiving and managing the rapidIO Message transaction based on the FPGA mainly comprises three modules, namely a rapidIO IP interface module, a rapidIO driving module and a multichannel sequencing module, as shown in figure 2.
The rapidIO IP interface module is mainly used for completing bottom layer sending and receiving of rapidIO transaction packets;
The rapidIO driving module is used for completing protocol analysis of the rapidIO transaction packet and giving a response to a request packet requiring the response;
The multi-channel ordering module is used for completing the ordering and combining of Message transaction data from different source nodes and outputting complete Message frame data after the ordering and combining is completed.
It should be noted that, the FPGA is an integrated circuit, a user may configure the FPGA after manufacturing to implement a highly flexible digital circuit design, rapidIO is a high-performance serial communication protocol used in an embedded system and a high-performance computing environment, a Message transaction is a Message transaction, and the IP interface is an interface for performing data communication between a device and a network, and is used for information interaction operation.
In step S1, interaction of the RapidIO transaction packet is achieved by calling Serial RapidIO Gen IP inside the FPGA when the RapidIO transaction packet is received, that is, the RapidIO transaction packet or the outgoing processed data file is received.
The RapidIO driving module mainly comprises three modules, namely an AXI FIFO buffer module, a Message request transaction analysis module and a Message response transaction group package module, as shown in fig. 3, and the RapidIO driving module performs protocol analysis on received Message transactions and gives Message request transaction responses.
The AXI FIFO buffer module is used for performing cross-clock domain processing of the Rapid IO interface, buffering Message transaction packets, the Message request transaction analysis module is used for performing protocol analysis on the Message request transactions and outputting Message framing parameters, and the Message response transaction grouping module is used for responding to the Message request transactions and performing grouping and sending according to a Message response frame format.
The specific steps of the AXI FIFO buffer module for carrying out cross-clock domain processing on the RapidIO interface are as follows:
Identifying clock domains, namely acquiring data and frequency of each clock domain, and determining data and interfaces which need to be transmitted across the clock domains, namely a Message transaction packet and Serial RapidIO Gen IP interfaces in the example;
The clock domain crossing is realized by using an AXI FIFO with asynchronous and independent clocks, the data and clock interfaces between different clock domains are butted, and simultaneously, the data is captured by using a double-edge trigger at a receiving end, so that the occurrence rate of time sequence problems of data sampling is reduced;
Determining the head and effective load of data package, and controlling the data sending and receiving process by existing state machine;
data synchronization, namely using a synchronizer to ensure that received data can be stabilized in a new clock domain;
And data caching, namely caching the data packet in the new clock domain.
It should be noted that, in the digital circuit design, the clock domains refer to circuit parts driven by specific clock signals, and circuits of each clock domain synchronously work in the same clock period, but different clock domains may operate under different clock frequencies and phases, so that data are inconsistent or lost, and thus, the clock domains need to be processed, and synchronizers used in data synchronization are not unique, for example, a dual-D trigger synchronizer is used for data synchronization.
In step S2, after the AXI FIFO buffer module performs the cross-clock domain processing on the RapidIO interface, the Message request transaction analysis module performs protocol analysis on the Message transaction packet and performs the specific steps of processing the analyzed Message transaction data as follows:
Obtaining a rapidIO transaction packet, namely reading the original rapidIO transaction packet through Serial RapidIO Gen IP;
extracting header information, namely analyzing the header of the transaction packet, extracting key fields, judging the type of the transaction packet, and knowing the length of a payload after determining the type of the transaction packet as a Message transaction packet;
analyzing the effective load, namely extracting effective load data according to the head information;
checking the tail information to ensure that the rapidIO transaction packet is free from errors in the transmission process;
frame processing, namely processing the parsed Message transaction to obtain frame parameters, wherein the frame parameters comprise:
msg_id, msg_len, msg_seg, msg_data, msg_data_val, msg_data_last, which are Message source ID, message fragment number, message fragment offset, message data valid, and Message data end flag, respectively;
And triggering a Message response request after framing processing is carried out on the framing data corresponding to each framing parameter in the Message transaction packet.
After receiving the Message response request, the Message response transaction group packet module generates a corresponding Message response transaction packet and sends the Message response transaction packet to the AXI FIFO buffer module, and the AXI FIFO buffer module caches and processes the Message response transaction packet across clock domains and outputs the Message response transaction packet to the Serial RapidIO Gen IP interface for sending.
It should be noted that Serial RapidIO Gen IP is a preset IP interface in this example, which is used to interact with RapidIO transaction packets, and the parsing algorithm and the checking algorithm are not unique, for example, the parsing algorithm may use recursive downward parsing, and the checking algorithm may use cyclic redundancy checking and so on.
In step S3, the multi-channel ordering module includes a FIFO buffer module, a channel arbitration module, an SRAM buffer control module, an SRAM buffer module, and a Message output control module, as shown in fig. 4, the multi-channel ordering module performs ordering combination on Message transaction data of different source nodes, that is, the Message frame data output by the RapidIO driving module is ordered according to frame parameters, and then integrated and outputs complete Message frame data.
The FIFO buffer module is used for buffering the Message frames;
The channel arbitration module is used for arbitrating the SRAM buffer channel, inputting the Message framing data into the corresponding SRAM buffer channel for arbitration, the flow relation is shown in figure 5, and the arbitration steps are as follows:
after receiving new Message framing data, polling occupy _st register of SRAM buffer module, if there is msg_id and occupy _id of Message framing in occupied SRAM buffer module, writing the Message framing data into corresponding SRAM buffer channel, otherwise applying for new SRAM buffer channel, assigning msg_id of Message framing to occupy _id of SRAM, and writing Message framing data into new buffer channel.
The SRAM cache control module is configured to write Message frame data of the same Message source ID to a corresponding address of the SRAM module, and allocate a plurality of parameters for state management of the SRAM module, as shown in fig. 6, including:
occupy _id, ocupy_st, msg_rlen, msg_rdata, msg_rcnt, which are SRAM busy ID, SRAM busy state, message full frame actual length, message full frame data, and Message full frame fragment count, respectively.
Occupy _id is used for inquiring whether Message framing data from the same source node is written into a corresponding channel;
occupy _st is used to query the current occupancy state of the SRAM, mark the idle state as occupy _st [1:0] =2 'b00, mark the occupancy state as occupy _st [1:0] =2' b01, mark the packet completion state as occupy _st [1:0] =2 'b10, mark the Message output state as occupy _st [1:0] =2' b11;
msg_rcnt is used for counting the complete frame fragments of the Message, and the count value of msg_rcnt is increased by 1 every time one frame of the Message fragments is written.
The channel arbitration module arbitrates the SRAM buffer channels, ensures that Message frame data from the same source ID is written into the same SRAM buffer channel, reduces resource competition conflict, reasonably avoids competition and conflict of shared resources when a plurality of Message transactions access the SRAM buffer at the same time, uses msg_rcnt to count Message complete frame fragments to determine the occupation condition of the Message transactions, can improve concurrency performance, lays an auxiliary foundation for subsequent high-priority transaction processing, sets fragment offset, can divide data into a plurality of fragments for transmission when the data to be transmitted exceeds the capacity of a single Message transaction, and utilizes the fragment offset to mark the relative position of each fragment in the whole data so as to carry out fragment transmission, thereby improving the data transmission inclusion.
It should be noted that, the SRAM buffer is a high-performance memory for temporarily storing data, accelerating access and processing of data, in fig. 6, two variables of sram_addr [11:8] and sram_addr [7:0] represent address buses of the SRAM, 11:8 represents high-order 4-bit addresses, 7:0 represents low-order 8-bit addresses, together form a complete address of the SRAM, the sram_ wdata variable represents written SRAM data, the sram_ wen variable represents write enable signals of the SRAM for controlling write operations of the SRAM, and the sram_rdata variable represents data read from the SRAM.
In step S4, the corresponding mapping is performed on the SRAM buffer address and the fragment offset of the Message frame, the frame data is written into the corresponding space of the SRAM module to complete the automatic sequencing of the Message frame, as shown in fig. 7, the SRAM buffer module is used for buffering the Message complete frame, and as the single Message length supported by RapidIO is 4096 bytes, the maximum size of each packet is 256 bytes, a 4096 buffer space is opened for the SRAM buffer, the address addressing range sram_ waddr [11:0]:0x 000-0 xfff, the high 4-bit address sram_ waddr [11:8] of the SRAM buffer and the fragment offset msg_seg [3:0] of the frame are mapped one by one, i.e. the SRAM buffer is divided into 16 buffer spaces with 256 bytes. In the Message framing storage process, the framing data is written into the corresponding space of the SRAM module through the fragment offset, so that the automatic sequencing function of Message framing is completed;
when the Message frame count msg_rcnt is equal to the number of fragments of the Message frame msg_len, the SRAM occupied state is set to occupy _st [1:0] =2 'b10, namely the SRAM occupied state is set to a packet completion state, the output of the Message complete frame is waited, the Message complete frame after the completion is output, the frame count msg_rcnt is cleared, the SRAM occupied state is set to occupy _st [1:0] =2' b00, namely the SRAM occupied state is set to an idle state.
If the SRAM buffer channel occupied in the preset specified time is not completely ordered into packets, when a timeout interrupt is generated, the Message framing statistics count msg_rcnt is cleared, and the SRAM occupied state is occupy _st [1:0] =2' b00.
The Message output control module is configured to perform complete Message frame output after the SRAM module completes the packet grouping, and display and output Message data in the SRAM module when the SRAM is detected to be in a packet grouping completion state by polling the SRAM state occupy _st of each channel, where the display and output Message complete frame includes:
Msg_rid, msg_rlen, msg_rdata, msg_rdv, msg_rsof, msg_ reof, which are Message reception source ID, message reception length, message reception data valid, message reception data start flag, and Message reception data end flag, respectively.
It should be noted that, when the data is divided into multiple slices for transmission, the slice offset is the starting position or the relative position of different slices in the whole data stream, which is used to identify the position field of a specific slice in the whole data block, and the slice offset is used to correctly recombine the data into the original data by using the position of the slice in the whole data stream, so as to reduce the communication failure problem caused by Message transaction packet retransmission disorder due to competition between source nodes in the large RapidIO switching system through the RapidIO driving module and the multichannel sequencing module, and expand the subsequent application scene analysis of the RapidIO bus in the embedded system.
The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product.
Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and application constraints imposed on the technology. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Finally, the foregoing description of the preferred embodiment of the invention is provided for the purpose of illustration only, and is not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Claims (6)

1.一种基于FPGA的RapidIO Message事务的乱序接收管理方法，其特征在于，包括以下步骤，1. A method for managing out-of-order reception of RapidIO Message transactions based on FPGA, comprising the following steps: 步骤S1：接收RapidIO事务包并进入RapidIO驱动模块，对RapidIO接口进行跨时钟处理并对Message事务包进行缓存;Step S1: Receive the RapidIO transaction packet and enter the RapidIO driver module, perform cross-clock processing on the RapidIO interface and cache the Message transaction packet; 步骤S2：对Message事务包进行协议解析，将解析后的Message事务数据进行分帧处理获取Message分帧数据并触发Message响应请求，按照Message响应请求进行组包输出；Step S2: Perform protocol parsing on the message transaction packet, perform frame processing on the parsed message transaction data to obtain message frame data and trigger a message response request, and perform packet output according to the message response request; 步骤S3：对SRAM缓存通道进行仲裁，将Message分帧数据写入对应通道；Step S3: arbitrate the SRAM cache channel and write the message frame data into the corresponding channel; 步骤S4：将SRAM缓存地址与Message分帧的分片偏移进行一一映射，将分帧数据写入SRAM模块的对应空间，完成Message分帧的自动排序；Step S4: Map the SRAM cache address to the fragment offset of the message frame one by one, write the frame data into the corresponding space of the SRAM module, and complete the automatic sorting of the message frame; SRAM缓存是一种高性能的存储器，用于临时存储数据；RapidIO是一种高性能的串行通信协议，用于嵌入式系统和高性能计算环境，Message事务即消息事务，IP接口是指设备与网络之间进行数据通信的接口，用于信息交互操作；SRAM cache is a high-performance memory used to temporarily store data; RapidIO is a high-performance serial communication protocol used in embedded systems and high-performance computing environments; Message transactions are message transactions; IP interface refers to the interface for data communication between devices and networks, used for information interaction operations; 在基于FPGA的RapidIO Message事务的乱序接收管理方法中包括三个模块，分别为RapidIO IP接口模块、RapidIO驱动模块以及多通道排序模块；The out-of-order receiving management method of RapidIO Message transactions based on FPGA includes three modules, namely RapidIO IP interface module, RapidIO driver module and multi-channel sorting module; RapidIO IP接口模块用于完成RapidIO事务包的底层发送与接收；The RapidIO IP interface module is used to complete the underlying sending and receiving of RapidIO transaction packets; RapidIO驱动模块用于完成RapidIO事务包的协议解析，针对要求响应的请求包给予响应；The RapidIO driver module is used to complete the protocol parsing of the RapidIO transaction packet and respond to the request packet that requires a response; 多通道排序模块用于完成来自于不同源节点的Message事务数据进行排序组合，并在排序组合完成后输出完整的Message帧数据；The multi-channel sorting module is used to sort and combine the message transaction data from different source nodes, and output the complete message frame data after the sorting and combination is completed; 在步骤S3中，多通道排序模块包括FIFO缓存模块、通道仲裁模块、SRAM缓存控制模块、SRAM缓存模块以及Message输出控制模块；In step S3, the multi-channel sorting module includes a FIFO buffer module, a channel arbitration module, an SRAM buffer control module, an SRAM buffer module and a Message output control module; FIFO缓存模块用于对Message分帧进行缓存；The FIFO buffer module is used to buffer message frames; 通道仲裁模块用于对SRAM缓存通道进行仲裁，将Message分帧数据录入对应SRAM缓存通道进行仲裁，仲裁步骤如下：The channel arbitration module is used to arbitrate the SRAM cache channel and enter the message frame data into the corresponding SRAM cache channel for arbitration. The arbitration steps are as follows: 当接收到新的Message分帧数据后，轮询SRAM缓存模块的occupy_st寄存器，若在已占用的SRAM、缓存模块中存在Message分帧的msg_id和occupy_id相等，则将Message分帧数据写入对应SRAM缓存通道；否则申请新的SRAM缓存通道，并将Message分帧的msg_id赋值给SRAM的occupy_id，同时将Message分帧数据写入新的缓存通道；When new message frame data is received, the occupy_st register of the SRAM cache module is polled. If the msg_id and occupy_id of the message frame in the occupied SRAM and cache module are equal, the message frame data is written into the corresponding SRAM cache channel; otherwise, a new SRAM cache channel is applied, and the msg_id of the message frame is assigned to the occupy_id of the SRAM, and the message frame data is written into the new cache channel; 在步骤S4中，SRAM缓存控制模块用于将相同Message源ID的message分帧数据写入SRAM模块的对应地址上，并分配多个参数用于SRAM模块的状态管理，包括：In step S4, the SRAM cache control module is used to write the message frame data of the same Message source ID to the corresponding address of the SRAM module, and allocate multiple parameters for the state management of the SRAM module, including: occupy_id、occupy_st、msg_rlen、msg_rdata、msg_rcnt，其分别为SRAM占用ID、SRAM占用状态、Message完整帧实际长度、Message完整帧数据以及Message完整帧分片计数；occupy_id, occupy_st, msg_rlen, msg_rdata, msg_rcnt, which are SRAM occupation ID, SRAM occupation status, Message complete frame actual length, Message complete frame data and Message complete frame fragment count respectively; occupy_id用于查询来自同一源节点的Message分帧数据是否写入对应通道；occupy_id is used to query whether the message frame data from the same source node is written into the corresponding channel; occupy_st用于查询SRAM的当前占用状态，将空闲状态标记为occupy_st[1：0]=2’b00；occupy_st is used to query the current occupied state of SRAM and mark the idle state as occupied_st[1:0]=2’b00; 将占用状态标记为occupy_st[1:0]=2’b01；Mark the occupied state as occupied_st[1:0]=2’b01; 将组包完成状态标记为occupy_st[1:0]=2’b10；Mark the packet completion status as occupy_st[1:0]=2’b10; 将Message输出状态标记为occupy_st[1:0]=2’b11；Mark the Message output status as occupied_st[1:0]=2’b11; msg_rcnt工作时，对Message完整帧分片进行计数，每写完一帧Message分帧，msg_rcnt的计数值加1。When msg_rcnt is working, it counts the complete message frame fragments. Every time a message frame is written, the count value of msg_rcnt is increased by 1. 2.根据权利要求1所述的一种基于FPGA的RapidIO Message事务的乱序接收管理方法，其特征在于：2. The method for managing out-of-order reception of RapidIO Message transactions based on FPGA according to claim 1, characterized in that: RapidIO驱动模块中包含三个模块：AXI FIFO缓存模块、Message请求事务解析模块以及Message响应事务组包模块；The RapidIO driver module contains three modules: AXI FIFO buffer module, Message request transaction parsing module and Message response transaction packaging module; RapidIO驱动模块通过对接收到的Message事务进行协议解析并给予Message请求事务响应；The RapidIO driver module performs protocol analysis on the received Message transaction and responds to the Message request transaction. AXI FIFO缓存模块用于RapidIO接口的跨时钟域处理，同时对Message事务包进行缓存；The AXI FIFO buffer module is used for cross-clock domain processing of the RapidIO interface and for caching Message transaction packets. Message请求事务解析模块用于对Message请求事务进行协议解析，并输出Message分帧参数；The message request transaction parsing module is used to perform protocol parsing on the message request transaction and output message framing parameters; Message响应事务组包模块用于对Message请求事务进行响应，按照Message响应帧格式进行组包发送。The message response transaction package module is used to respond to the message request transaction and package and send it according to the message response frame format. 3.根据权利要求2所述的一种基于FPGA的RapidIO Message事务的乱序接收管理方法，其特征在于：3. The method for managing out-of-order reception of RapidIO Message transactions based on FPGA according to claim 2, characterized in that: 在步骤S1中，AXI FIFO缓存模块对RapidIO接口进行跨时钟域处理具体步骤如下：In step S1, the AXI FIFO buffer module performs cross-clock domain processing on the RapidIO interface. The specific steps are as follows: 识别时钟域：获取每个时钟域的源、频率和相位，确定跨时钟域传输的数据以及接口；Identify clock domains: obtain the source, frequency, and phase of each clock domain, and determine the data and interfaces transmitted across clock domains; 跨时钟域：使用AXI FIFO缓冲区来缓冲数据，在接收端使用双边沿触发器捕获数据，降低数据采样的时序问题出现率；Cross-clock domain: Use AXI FIFO buffer to buffer data, and use double-edge triggers to capture data at the receiving end to reduce the occurrence of timing problems in data sampling; 设计数据传输协议：确定数据包的头部、有效荷载，通过已有的状态机控制数据的发送和接收过程；Design data transmission protocol: determine the header and payload of the data packet, and control the data sending and receiving process through the existing state machine; 数据同步：使用同步器确保接收到的数据能够在新的时钟域中稳定；Data synchronization: Use synchronizers to ensure that received data is stable in the new clock domain; 数据缓存：对新的时钟域内的数据包进行缓存。Data caching: Caches data packets in the new clock domain. 4.根据权利要求2所述的一种基于FPGA的RapidIO Message事务的乱序接收管理方法，其特征在于：4. The method for managing out-of-order reception of RapidIO Message transactions based on FPGA according to claim 2, characterized in that: 在步骤S2中，Message请求事务解析模块对Message事务包进行协议解析并对解析后的Message事务数据进行分帧处理具体步骤如下：In step S2, the message request transaction parsing module performs protocol parsing on the message transaction packet and performs framing processing on the parsed message transaction data. The specific steps are as follows: 获取RapidIO事务包：通过Serial RapidIO Gen2 IP接口读取原始的RapidIO事务包；Get RapidIO transaction packets: read the original RapidIO transaction packets through the Serial RapidIO Gen2 IP interface; 提取头部信息；解析有效载荷：根据头部消息，提取有效载荷数据；Extract header information; parse payload: extract payload data based on header information; 校验处理：对尾部信息进行校检，确保RapidIO事务包在传输过程中未出错；Verification processing: Check the tail information to ensure that there are no errors in the RapidIO transaction packet during transmission; 分帧处理：将Message事务包进行分帧获取分帧参数，包括：Framing: Framing the message transaction package to obtain framing parameters, including: msg_id、msg_len、msg_seg、msg_data、msg_data_val、msg_data_last，其分别为Message源ID、Message分片数量、Message分片偏移、Message数据、Message数据有效以及Message数据结束标志。msg_id, msg_len, msg_seg, msg_data, msg_data_val, and msg_data_last are respectively the Message source ID, the number of Message fragments, the Message fragment offset, the Message data, the Message data validity, and the Message data end flag. 5.根据权利要求4所述的一种基于FPGA的RapidIO Message事务的乱序接收管理方法，其特征在于：5. The method for managing out-of-order reception of RapidIO Message transactions based on FPGA according to claim 4, characterized in that: 在步骤S2中，每个分帧参数对应Message事务包中的分帧数据，在进行分帧处理后触发Message响应请求；In step S2, each framing parameter corresponds to the framing data in the Message transaction packet, and triggers a Message response request after framing processing; Message响应事务组包模块将分帧处理后的Message请求事务包转换为Message响应事务包并传回AXI FIFO缓存模块，AXI FIFO缓存模块将分帧参数以及Message响应事务包进行缓存后输出Message响应事务包。The Message response transaction packet assembly module converts the Message request transaction packet after framing into a Message response transaction packet and transmits it back to the AXI FIFO buffer module. The AXI FIFO buffer module caches the framing parameters and the Message response transaction packet and then outputs the Message response transaction packet. 6.根据权利要求1所述的一种基于FPGA的RapidIO Message事务的乱序接收管理方法，其特征在于：6. The method for managing out-of-order reception of RapidIO Message transactions based on FPGA according to claim 1, characterized in that: 在步骤S4中，当Message分帧存储完成后，用于Message分帧统计计数的msg_rcnt数值加1，当检测到Message分帧统计计数msg_rcnt与Message分帧的分片数量msg_len相等时，将SRAM占用状态置为occupy_st[1:0]=2’b10，等待Message完整帧输出，输出完成后Message完整帧，将分帧统计计数msg_rcnt清零，将SRAM占用状态置为occupy_st[1：0]=2’b00；In step S4, when the Message frame storage is completed, the msg_rcnt value used for the Message frame statistics count is increased by 1. When it is detected that the Message frame statistics count msg_rcnt is equal to the number of fragments msg_len of the Message frame, the SRAM occupancy state is set to occupied_st[1:0]=2'b10, waiting for the Message complete frame to be output. After the output is completed, the Message complete frame is cleared, and the SRAM occupancy state is set to occupied_st[1:0]=2'b00; 若在预设的规定时间内占用的SRAM缓存通道未完成组包排序，当产生超时中断时，将Message分帧统计计数msg_rcnt清零，将SRAM占用状态置为occupy_st[1：0]=2’b00。If the occupied SRAM cache channel fails to complete the packet sorting within the preset specified time, when a timeout interrupt occurs, the message frame statistics count msg_rcnt is cleared and the SRAM occupancy status is set to occupied_st[1:0]=2’b00.
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