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CN118802816B - Data distribution circuit, method, medium and chip - Google Patents

Data distribution circuit, method, medium and chip Download PDF

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Publication number
CN118802816B
CN118802816B CN202411276603.4A CN202411276603A CN118802816B CN 118802816 B CN118802816 B CN 118802816B CN 202411276603 A CN202411276603 A CN 202411276603A CN 118802816 B CN118802816 B CN 118802816B
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data
sub
header
module
target
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CN118802816A (en
Inventor
杨龚轶凡
郑瀚寻
闯小明
靳翼冰
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Zhonghao Xinying Hangzhou Technology Co ltd
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Zhonghao Xinying Hangzhou Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9057—Arrangements for supporting packet reassembly or resequencing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The application discloses a data distribution circuit, a data distribution method, a medium and a chip. The circuit comprises: the device comprises a memory interaction module, a head information processing module, a data processing module and a data output module; the memory interaction module reads the data head and each sub data of the target data packet for the first time and sends the data head and each sub data to the head information processing module; the head information processing module determines a first matching relationship between the data head and each sub-data and each downstream channel; the memory interaction module reads the target data packet for the second time and sends the target data packet to the data processing module; the data processing module determines a second matching relation between the first-in first-out buffer sequence of the data output module and each downstream channel, and sends data to the data output module based on the first matching relation and the second matching relation; the data output module sends the data to the corresponding downstream channel. The data distribution circuit in this embodiment reads the target data packet twice successively, and does not need to register each sub data of the target data packet in the data processing process, so that too many registers are not needed.

Description

Data distribution circuit, method, medium and chip
Technical Field
The present application relates to the field of data processing in computing devices, and in particular, to a data distribution circuit, method, medium, and chip.
Background
In modern digital systems, the efficiency of data processing and transmission is critical to system performance, and as digital systems continue to increase in complexity, conventional single processing units have failed to meet the high throughput, low latency data processing requirements. Multi-channel architecture is a mainstream design trend to solve this problem.
In the field of multi-channel data, the existing design generally reads data from a memory, processes the data and transmits the data to a corresponding downstream channel, however, since a process of waiting for data processing is needed, the data needs to be stored in a register during data processing, a large number of registers are needed to temporarily store the data, and thus the area of a corresponding processing chip is increased and the power consumption is increased.
Disclosure of Invention
The application mainly aims to provide a data distribution circuit, a data distribution method, a medium and a chip, and aims to solve the problems that in the prior art, in multichannel data transmission, a large number of registers are needed for temporarily storing data, so that the area of a processing chip is increased and the power consumption is increased.
To achieve the above object, the present application provides a data distribution circuit including: the device comprises a memory interaction module, a head information processing module, a data processing module and a data output module;
The memory interaction module is configured to: in response to receiving a data reading instruction, reading a data head and each piece of sub data of a target data packet corresponding to the data reading instruction for the first time, and sending the data head and each piece of sub data to the head information processing module;
The header information processing module is configured to: in response to receiving the data head and each piece of sub data, determining a first matching relationship between the data head and each piece of sub data and each downstream channel, sending the first matching relationship to the data processing module, and sending a matching completion signal to the memory interaction module;
The memory interaction module is further configured to: in response to receiving the matching completion signal, reading the data header and each sub-data of the target data packet for the second time, and transmitting the data header and each sub-data to the data processing module;
The data processing module is configured to: in response to receiving the data header and each sub-data, determining a second matching relationship between a first-in first-out buffer sequence of the data output module and each downstream channel, and transmitting the data header and each sub-data to the first-in first-out buffer sequence of the data output module based on the first matching relationship and the second matching relationship;
The data output module is configured to: and transmitting the data header and the sub-data to the corresponding downstream channel in response to the received data header and the sub-data.
In an implementation of the present application, the memory interaction module is further configured to:
After receiving the data reading instruction, analyzing the data reading instruction, and determining the head address of the target data packet in a preset storage module;
Reading the data head of the target data packet from a preset storage module based on the head address;
determining the number of sub-data contained in the target data packet based on the data header;
And reading each piece of sub data from the storage module based on the head address and the number of the sub data.
In an implementation of the present application, the memory interaction module is further configured to: and reading the data head and each piece of sub data from each storage block of the storage module in parallel.
In an implementation of the present application, the memory interaction module is further configured to:
After each time the data head and each piece of sub data of the target data packet are obtained, rearranging the obtained data head and each piece of sub data so that the data head and each piece of sub data are cached into a first-in first-out cache sequence of the memory interaction module according to the sequence of each piece of sub data in the target data packet.
In an implementation of the present application, the header information processing module is further configured to:
extracting the data head and the first characteristic value of each sub data;
and determining a downstream channel matched with the data head and each piece of sub data based on the first characteristic value and preset register information of the data head and each piece of sub data.
In an implementation of the present application, the data processing module is further configured to:
And after receiving each piece of sub data, extracting the effective information of each piece of sub data to obtain target output data, wherein the target output data comprises a data head of the target data packet and each piece of extracted sub data, and the target output data is sent to a first-in first-out buffer sequence of the data output module based on the first matching relation and the second matching relation.
In an implementation of the present application, the data processing module is further configured to:
after the target data packet is obtained, extracting a second characteristic value of the target data packet;
And determining a second matching relationship between the first-in first-out buffer sequence of the data output module and each downstream channel based on the second characteristic value.
In an implementation of the present application, the data processing module is further configured to:
determining a target first-in first-out buffer sequence corresponding to the data head and each sub data in the data output module based on the first matching relation and the second matching relation, wherein the data head and the target first-in first-out buffer sequence corresponding to any sub data are matched with the same downstream channel in the first matching relation and the second matching relation;
and respectively sending the data head and each sub data to a corresponding target first-in first-out buffer sequence in the data output module.
In an implementation of the present application, the data output module is further configured to:
After the data head and each sub data are sent to the corresponding downstream channel, a transmission completion instruction is sent to the memory interaction module;
the memory interaction module is further configured to: and transmitting synchronization information to a preset synchronous memory module in response to receiving the transmission completion instruction, wherein the synchronization information comprises the number of sub-data transmitted by a downstream channel in the data transmission.
The application also provides a data distribution method applied to the data distribution circuit in any embodiment, which comprises the following steps:
Responding to a received data reading instruction, firstly reading a data head and each piece of sub data of a target data packet corresponding to the data reading instruction based on the memory interaction module, and sending the data head and each piece of sub data to the head information processing module;
Determining a first matching relation between the data head and each sub-data and each downstream channel based on the head information processing module, sending the first matching relation to the data processing module after the first matching relation is obtained, and sending a matching completion signal to the memory interaction module;
Responding to the memory interaction module receiving the matching completion signal, reading the data head and each piece of sub data of the target data packet based on the memory interaction module for the second time, and sending the data head and each piece of sub data to the data processing module;
Determining a second matching relation between the first-in first-out buffer sequence of the data output module and each downstream channel based on the data processing module, and sending the data head and each sub-data to the first-in first-out buffer sequence of the data output module based on the first matching relation and the second matching relation;
The data header and the respective sub-data are sent to the respective downstream channels based on the data processing module.
In the implementation of the present application, after the memory interaction module receives the data reading instruction, the data distribution method further includes:
based on the memory interaction module analyzing the data reading instruction, determining the head address of the target data packet in a preset storage module;
Reading the data head of the target data packet from a preset storage module based on the head address;
determining the number of sub-data contained in the target data packet based on the data header;
And reading each piece of sub data from the storage module based on the head address and the number of the sub data.
In the implementation of the application, the data head and each sub data are read in parallel from each storage block of the storage module based on the memory interaction module.
In the implementation of the present application, after the memory interaction module reads the header and each sub-data of the target data packet, the data distribution method further includes:
and rearranging the acquired data head and each piece of sub data so as to enable the data head and each piece of sub data to be cached into a first-in first-out cache sequence of the memory interaction module according to the sequence of the data head and each piece of sub data in the target data packet.
In the implementation of the present application, after the header information processing module acquires the data header and each sub-data, the first matching relationship is determined according to the following manner:
extracting the data head and the first characteristic value of each sub data;
and determining a downstream channel matched with the data head and each piece of sub data based on the first characteristic value and preset register information of the data head and each piece of sub data.
In an embodiment of the present application, after the data processing module receives each sub-data, the data distribution method further includes:
extracting effective information of each sub-data to obtain target output data, wherein the target output data comprises a data head of the target data packet and each extracted sub-data, and sending the target output data to a first-in first-out buffer sequence of the data output module based on the first matching relation and the second matching relation.
In the implementation of the present application, after the data processing module acquires the target data packet, the second matching relationship is determined according to the following manner:
Extracting a second characteristic value of the target data packet;
And determining a second matching relationship between the first-in first-out buffer sequence of the data output module and each downstream channel based on the second characteristic value.
In the implementation of the present application, the data distribution method further includes:
determining a target first-in first-out buffer sequence corresponding to the data head and each sub data in the data output module based on the first matching relation and the second matching relation, wherein the data head and the target first-in first-out buffer sequence corresponding to any sub data are matched with the same downstream channel in the first matching relation and the second matching relation;
And respectively sending the data head and each piece of sub data to a corresponding target first-in first-out buffer sequence in the data output module based on the data processing module.
In an embodiment of the present application, after the data output module sends the data header and the respective sub-data to the corresponding downstream channels, the data distribution method further includes:
Transmitting a transmission completion instruction to the memory interaction module based on the data output module;
and transmitting synchronization information to a preset synchronous memory module based on the memory interaction module, wherein the synchronization information comprises the number of sub-data transmitted by a downstream channel in the data transmission.
The application also proposes a readable storage medium comprising instructions which, when run on a computing device, cause the computing device to perform the method of any of the preceding claims.
The application also provides a chip comprising the data distribution circuit in any embodiment.
According to the embodiment of the application, the functions of data reading, data analysis, head information generation, data distribution and the like are modularized into the memory interaction module, the data processing module, the head information processing module and the data output module, so that the data transmission system is easier to expand and maintain, the modules can be flexibly increased or reduced according to actual requirements, and the data transmission system is suitable for applications of different scales. In addition, in the prior art, when data is transmitted, after the target data packet is read from the storage module, the target data packet needs to be processed to determine the matching relationship between the data header and each sub-data in the target data packet and the downstream channel, and in this process, the data header and each sub-data need to wait for the processing process and cannot be transmitted to the downstream channel, so a large number of registers are required to store the data header and each sub-data. In the embodiment of the application, for a data reading instruction, the target data packet is read twice successively, and when the target data packet is read for the first time, the first matching relation between the data head and each sub data in the target data packet and the downstream channel is determined, and after the first matching relation is obtained, the target data packet is read for the second time, and because the first matching relation between the data head and each sub data and the downstream channel is obtained when the target data packet is read for the first time, the target data packet can be directly sent without storing the target data packet, and therefore, a large number of registers are not needed, and the storage cost can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram illustrating an application scenario of a data distribution circuit in a multi-channel data transmission field according to an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating a storage of a target packet in a storage module according to an embodiment of the application;
FIG. 3 is a diagram showing the ordering of the data read from the memory module in a first-in-first-out (FIFO) buffer sequence of the memory interaction module according to an embodiment of the present application;
FIG. 4 is a diagram showing the ordering of the data read from the memory module in a first-in-first-out (FIFO) buffer sequence of the memory interaction module after rearrangement according to one embodiment of the present application;
FIG. 5 is a step diagram of a data distribution method according to an embodiment of the present application;
FIG. 6 is a block diagram of a readable storage medium according to an embodiment of the application.
Reference numerals:
100-data distribution circuit, 110-memory interaction module, 120-header information processing module, 130-data processing module, 140-data output module, 200-memory module, 300-controller, 400-synchronous memory module, 500-control and status register and 600-data transmission system.
The achievement of the objects, functional features and advantages of the present application will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The principles and spirit of the present application will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are presented merely to enable those skilled in the art to better understand and practice the application and are not intended to limit the scope of the application in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Those skilled in the art will appreciate that embodiments of the application may be implemented as a system, apparatus, method, or computer program product. Accordingly, the present disclosure may be embodied in the following forms, namely: complete hardware, complete software (including firmware, resident software, micro-code, etc.), or a combination of hardware and software.
According to an embodiment of the application, a data distribution circuit, a method, a medium and a chip are provided.
In this document, it should be understood that any number of elements in the drawings is for illustration and not limitation, and that any naming is used only for distinction and not for any limitation.
The principles and spirit of the present application are explained in detail below with reference to several representative embodiments thereof.
Exemplary apparatus
The present exemplary embodiment proposes a data distribution circuit 100, as shown in fig. 1, the data distribution circuit 100 including:
The device comprises a memory interaction module 110, a head information processing module 120, a data processing module 130 and a data output module 140;
The memory interaction module 110 is configured to: in response to receiving a data reading instruction, reading a data header and each sub-data of a target data packet corresponding to the data reading instruction for the first time, and sending the data header and each sub-data to the header information processing module 120;
the header information processing module 120 is configured to: in response to receiving the data header and each sub-data, determining a first matching relationship between the data header and each sub-data and each downstream channel, and sending the first matching relationship to the data processing module 130, and sending a matching completion signal to the memory interaction module 110;
The memory interaction module 110 is further configured to: in response to receiving the match completion signal, reading the header and each sub-data of the target packet a second time and transmitting the header and each sub-data to the data processing module 130;
The data processing module 130 is configured to: in response to receiving the data header and the respective sub-data, determining a second matching relationship between a first-in-first-out buffer sequence of the data output module 140 and the respective downstream channel, and transmitting the data header and the respective sub-data to the first-in-first-out buffer sequence of the data output module 140 based on the first matching relationship and the second matching relationship;
the data output module 140 is configured to: and transmitting the data header and the sub-data to the corresponding downstream channel in response to the received data header and the sub-data.
As shown in fig. 1, fig. 1 is an application scenario diagram of a data distribution circuit 100 in the field of multi-channel data transmission according to an embodiment of the present application. The data transmission system 600 is provided with a controller 300, a storage module 200, a synchronous memory module 400, a downstream channel and a data distribution circuit 100.
The storage module 200 stores a plurality of data packets in advance, each data packet includes a data header and a plurality of sub-data, and when the data packets are stored in the storage module 200, a storage address of the data header is located at a front edge of each sub-data. In addition, the ‌ data header generally includes the ‌ source, ‌ first address, ‌ protocol type, ‌ data size, and number of sub-data of the corresponding data packet. For example, in network communications, a data packet is composed of a binary data sequence consisting of electrical pulses, which contains two parts, header information (data packet) and data (respective sub-data). Header information such as source IP address, destination IP address, etc. is used to determine the routing of the data packets, ensuring that the data is properly transmitted in the network.
The controller 300 is configured to issue a data reading instruction to the data distribution circuit 100 according to a requirement, and it should be noted that, all data packets read by the data reading instruction are pre-stored in the storage module 200; after receiving the data reading instruction, the data distribution circuit 100 reads the data packet corresponding to the data reading instruction from the storage module 200, processes the data packet, and then distributes the processed data packet to each downstream channel, and after completing one-time data distribution, the synchronous memory module 400 synchronizes the information of the current data distribution.
In an embodiment of the present application, the memory interaction module 110 is further configured to: after receiving the data reading instruction, analyzing the data reading instruction, and determining the head address of the target data packet in a preset storage module 200; reading the data head of the target data packet from a preset storage module 200 based on the head address; determining the number of sub-data contained in the target data packet based on the data header; based on the head address and the number of sub-data, the respective sub-data is read from the memory module 200.
For example, in the embodiment of the present application, when a certain target data packet needs to be sent to the data reading device through the downstream channel, a data reading instruction related to the target data packet is sent to the memory interaction module 110 through the controller 300, and after the memory interaction module 110 receives the data reading instruction, the data reading instruction may be parsed, so as to determine the first address of the target data packet to be read in the data reading instruction in the preset storage module 200. In general, the data packet includes a data header and a plurality of sub-data that are stored in the storage module 200 in succession, and the data header is located at the forefront position, i.e., the head address position, and each sub-data is stored in succession after the head address. Therefore, after the memory interaction module 110 determines the first address of the target data packet, the header of the target data packet may be read from the first address in the storage module 200. After the memory interaction module 110 obtains the header of the target data packet, the number of sub-data included in the target data packet can be determined by analyzing the header, and then after the header address, all the sub-data of the target data packet can be read after the storage module 200 continuously reads the storage bits with the same number as the sub-data of the target data packet.
In an embodiment of the present application, the memory interaction module 110 is further configured to: the data header and the respective sub-data are read in parallel from the respective memory blocks of the memory module 200.
Wherein the memory module 200 comprises a plurality of memory blocks, each memory block further having a memory depth. For example, as shown in fig. 2, in the embodiment of the present application, the memory module 200 includes memory blocks Bank0-Bank15, each memory block has a memory depth of 16 (0-15), the target Data packet includes Data0-Data18, data0 is a Data header, data1-Data18 is each sub Data, and Data0-Data18 is pre-stored in each memory block of the memory module 200. If the memory interaction module 110 reads the Data from the memory module 200 serially, the Data in one memory block is read each time according to the sequence of banks 0-15, for example, data0 and Data16 in Bank0 are read for the first time, data1 and Data17 in Bank1 are read for the second time, data2 and Data18 in Bank3 are read for the third time, and so on until Data15 in Bank15 is read. When the reading method is used for serially reading the memory blocks one by one, the reading speed is low, and the time consumption is long. Thus, in an embodiment of the present application, the memory interaction module 110 may be configured to read from the storage module 200 in parallel.
For example, assuming that in the embodiment of the present application, the memory interaction module 110 is configured to read in parallel with a parallelism of 4, then data in four memory blocks are read at a time, for example, the first time of reading: (Data 0, data 16) (Data 1, data 17) (Data 2, data 18) (Data 3), the second reading (Data 4, data 5) (Data 6, data 7), and so on, the last reading (Data 12) (Data 13) (Data 14) (Data 15). The memory interaction module 110 is configured to read data from the storage module 200 in parallel, so that the time for reading the data can be reduced, the reading speed can be improved, the overall delay of the system can be reduced, and the capability of processing the real-time data can be improved.
In an embodiment of the present application, the memory interaction module 110 is further configured to:
After each acquisition of the header and each sub-data of the target data packet, the acquired header and each sub-data are rearranged, so that the header and each sub-data are cached in the first-in first-out cache sequence of the memory interaction module 110 according to the sequence of each sub-data in the target data packet.
As shown in fig. 3, the memory interaction module 110 reads the target Data packet according to the memory blocks in the memory module 200 when reading the target Data packet from the memory module 200, so that the read Data is sorted in the first-in first-out (FIFO) buffer sequence(s) of the memory interaction module 110 as shown in fig. 3, that is, the Data0-Data18 included in the target Data packet is not buffered in the FIFO of the memory interaction module 110 according to the order of the Data0-Data18 included in the target Data packet, and when the memory interaction module 110 sends the target Data packet to the header information processing module 120, the Data is also sent according to the order shown in fig. 3. Therefore, in the embodiment of the present application, the memory interaction module 110 is configured to rearrange the data header and each sub-data of the target data packet according to the order of each sub-data in the target data packet after the data header and each sub-data of the target data packet are acquired, and then buffer the rearranged data into the FIFO of the memory interaction module 110, as shown in fig. 4, so that when the memory interaction module 110 sends the data header and each sub-data to the header information processing module 120, the data header and each sub-data are sent according to the order of each sub-data in the target data packet, so that the header information processing module 120 is convenient to process the target data packet.
In an embodiment of the present application, the header information processing module 120 is further configured to:
extracting the data head and the first characteristic value of each sub data;
and determining a downstream channel matched with the data head and each piece of sub data based on the first characteristic value and preset register information of the data head and each piece of sub data.
In the embodiment of the present application, after the header information processing module 120 obtains the header and each sub-data of the target data packet sent by the memory interaction module 110, the first feature value may be extracted for the header and the sub-data. The first characteristic value of the header data and the first characteristic value of each sub-data include a characteristic address (feature ID) of each corresponding register information in the control and status register 500, so that each corresponding register information can be read from the control and status register 500 based on the characteristic address of the header data and each sub-data, and each corresponding register information can indicate each corresponding downstream channel ID. Accordingly, the header information processing module 120 may obtain the respective corresponding register information from the control and status register 500 based on the header data and the first characteristic value of each sub-data, and further determine the downstream channel, i.e., the first matching relationship, corresponding to the data header and each sub-data.
For example, in the embodiment of the present application, as shown in fig. 1, the downstream channel includes a channel 0-channel n, and taking the example that the target Data packet includes Data0-Data18, the first matching relationship can indicate the channel IDs corresponding to each of Data0-Data18, as shown in the following table 1:
TABLE 1
As shown in Table 1 above, data0-3 in the destination packet needs to be sent over downstream lane 0, data4-7 in the destination packet needs to be sent over downstream lane 1, data8-11 in the destination packet needs to be sent over downstream lane 2, data12-15 in the destination packet needs to be sent over downstream lane 3, and Data16-18 in the destination packet needs to be sent over downstream lane 4.
In the embodiment of the present application, after the first matching relationship is obtained by the header information processing module 120, the header information processing module 120 may send the obtained first matching relationship to the data processing module 130 and the data output module 140, in addition, the header information processing module 120 may send a matching completion signal to the memory interaction module 110, and after the memory interaction module 110 receives the matching completion signal sent by the header information processing module 120, the header and each sub-data of the target data packet may be read from the storage module for the second time, where the process of reading for the second time is the same as the process of reading for the first time, which is not described herein in detail. When the memory interaction module 110 reads the header and each sub-data of the target packet for the second time, it can send the header and each sub-data to the data processing module 130. It should be noted that, after the second acquisition of the header and each sub-data of the target data packet, the memory interaction module 110 may reorder the header and each sub-data of the target data packet and buffer the header and each sub-data into the FIFO of the memory interaction module 110 according to the sequence of each sub-data in the target data packet, so that when the target data packet sends the header data and each sub-data to the data processing module 130, the header data and each sub-data may also be sent according to the sequence of each sub-data in the target data packet.
In an embodiment of the present application, the data processing module 130 is further configured to:
after the target data packet is obtained, extracting a second characteristic value of the target data packet;
Based on the second eigenvalue, a second matching relationship between the first-in first-out buffer sequence of the data output module 140 and the respective downstream channels is determined.
In this embodiment of the present application, after the data processing module 130 obtains the header and each sub-data of the target data packet, the data processing module 130 may process the data header and the sub-data to obtain a second feature value of the target data packet, where the second feature value includes a feature address of the second feature value, and the data processing module 130 may obtain relevant register information in the state and control register 500 based on the feature address, where the register information at least includes a matching relationship between a first-in-first-out buffer sequence (FIFO) of the data output module 140 and each downstream channel. For example, as shown in table 2 below:
TABLE 2
As shown in table 2 above, the data buffered in the data output module 140FIFO 0-1 is sent to the downstream channel 0 by the data output module 140, the data buffered in the data output module 140FIFO 2-3 is sent to the downstream channel 1 by the data output module 140, the data buffered in the data output module 140FIFO 4-5 is sent to the downstream channel 2 by the data output module 140, the data buffered in the data output module 140FIFO 6-7 is sent to the downstream channel 3 by the data output module 140, and the data buffered in the data output module 140FIFO 8-9 is sent to the downstream channel 4 by the data output module 140.
In an embodiment of the present application, the data processing module 130 is further configured to:
Determining a target first-in first-out buffer sequence corresponding to the data head and each sub-data in the data output module 140 based on the first matching relationship and the second matching relationship, wherein the data head and the target first-in first-out buffer sequence corresponding to any sub-data are matched with the same downstream channel in the first matching relationship and the second matching relationship;
The header and each sub-data are sent to a corresponding target fifo sequence in the data output module 140, respectively.
As shown in table 1 and table 2, data 0-3 in the target Data packet needs to be sent through the downstream channel 0, where the downstream channel 0 corresponds to FIFO 0-1 of the Data processing module 130, so FIFO 0-1 of the Data output module 140 is the target FIFO sequence of Data 0-3, and Data 0-3 can be sent to FIFO 0-1 of the Data output module 140 based on the Data processing module 130; similarly, data 4-7 in the target packet needs to be sent through the downstream channel 1, and the downstream channel 1 corresponds to the FIFO 2-3 of the Data processing module 130, so that the FIFO 2-3 of the Data output module 140 is the target FIFO buffer sequence of Data 4-7, and Data 0-3 can be sent to the FIFO 0-1 of the Data output module 140 based on the Data processing module 130; data8-11 in the target Data packet needs to be sent through the downstream channel 2, and the downstream channel 2 corresponds to the FIFO 4-5 of the Data processing module 130, so that the FIFO 4-5 of the Data output module 140 is the target FIFO buffer sequence of Data8-11, and Data8-11 can be sent to the FIFO 4-5 of the Data output module 140 based on the Data processing module 130; data12-15 in the target Data packet needs to be sent through the downstream channel 3, and the downstream channel 3 corresponds to the FIFO 6-7 of the Data processing module 130, so that the FIFO 6-7 of the Data output module 140 is the target FIFO sequence of Data12-15, and Data12-15 can be sent to the FIFO 6-7 of the Data output module 140 based on the Data processing module 130; data 16-18 in the destination packet needs to be sent through downstream channel 4, and downstream channel 4 corresponds to FIFO 8-9 of Data processing module 130, so that FIFO 8-9 of Data output module 140 is the destination FIFO buffer sequence of Data 16-18, and Data 16-18 can be sent to FIFO 8-9 of Data output module 140 based on Data processing module 130.
In the embodiment of the present application, the data output module 140 is connected to the controller 300 of each downstream channel through the credit-based interface, and when each downstream channel controller 300 can receive data, the data is discharged from the FIFO of the data output module 140 and sent to the corresponding downstream channel, so that it can be ensured that the data can be transmitted only when each downstream channel can receive data, thereby reducing the probability of data loss and transmission error, and improving the reliability of data transmission.
In an embodiment of the present application, the data processing module 130 is further configured to:
And after receiving the sub-data, extracting the effective information of the sub-data to obtain target output data, wherein the target output data comprises a data head of the target data packet and the extracted sub-data, and sending the target output data to a first-in first-out buffer sequence of the data output module 140 based on the first matching relation and the second matching relation.
In the process of extracting the effective information, the effective information is extracted from each sub data only, and the ineffective information does not need to be sent to the data output module 140, so that the overhead of data transmission is reduced, and the transmission speed is increased. In addition, when the data processing module 130 extracts the effective information based on each sub-data to obtain each extracted sub-data, the number and the sequence of each extracted sub-data are the same as those of the original sub-data. For example, the sub Data included in the target Data packet includes Data1-18, after extracting the effective information from each sub Data, the sub Data still includes 18 extracted sub Data, and corresponds to Data1-18 one by one, for example, the effective information corresponding to Data1 is Data '1, then Data'1 is the extracted sub Data corresponding to Data1, the effective information corresponding to Data2 is Data '2, and Data'2 is the extracted sub Data corresponding to Data2, and so on, the effective information corresponding to Data18 is Data '18, and Data'18 is the extracted sub Data corresponding to Data 18.
In addition, it should be noted that, when extracting the effective information from each sub-Data, the first matching relationship between the Data header and each sub-Data determined by the header information processing module 120 and the downstream channel is still applicable to the extracted effective information, for example, the matching relationship between Data1-Data18 and the downstream channel, namely, the matching relationship between Data'1-18 and the downstream channel; in addition, when the data is transmitted to the data transmission module, the data head and each extracted sub data are transmitted according to the first matching relation and the second matching relation. For example, data 0 and Data'1-3 are sent to FIFOs 0-1 of the Data output module 140 based on the Data processing module 130; sending Data'4-7 to FIFOs 0-1 of the Data output module 140 based on the Data processing module 130; sending Data'8-11 to FIFOs 4-5 of Data output module 140 based on Data processing module 130; sending Data' 12-15 to FIFOs 6-7 of Data output module 140 based on Data processing module 130; data' 16-18 is sent to FIFOs 8-9 of Data output module 140 based on Data processing module 130.
In the embodiment of the present application, the functions of data reading, data parsing, header information generation, data distribution, etc. are modularized into the memory interaction module 110, the data processing module 130, the header information processing module 120 and the data output module 140, so that the data transmission system 600 is easier to expand and maintain, and the modules can be flexibly increased or decreased according to actual requirements, so as to adapt to applications of different scales. In addition, in the prior art, when data is transmitted, after the target data packet is read from the storage module 200, the target data packet needs to be processed to determine the matching relationship between the data header and each sub-data in the target data packet and the downstream channel, and in this process, the data header and each sub-data need to wait for the processing process and cannot be transmitted to the downstream channel, so a large number of registers are required to store the data header and each sub-data. In the embodiment of the application, for a data reading instruction, the target data packet is read twice successively, and when the target data packet is read for the first time, the first matching relation between the data head and each sub data in the target data packet and the downstream channel is determined, and after the first matching relation is obtained, the target data packet is read for the second time, and because the first matching relation between the data head and each sub data and the downstream channel is obtained when the target data packet is read for the first time, the target data packet can be directly sent without storing the target data packet, and therefore, a large number of registers are not needed, and the storage cost can be reduced.
Exemplary method
As shown in fig. 5, the present exemplary embodiment proposes a data distribution method, which is applied to the data distribution circuit described in any one of the above exemplary embodiments of the present exemplary apparatus, and in the embodiment of the present application, the data distribution method includes the following steps S100 to S500:
Step S100: responding to a received data reading instruction, firstly reading a data head and each piece of sub data of a target data packet corresponding to the data reading instruction based on the memory interaction module, and sending the data head and each piece of sub data to the head information processing module;
step S200: determining a first matching relation between the data head and each sub-data and each downstream channel based on the head information processing module, sending the first matching relation to the data processing module after the first matching relation is obtained, and sending a matching completion signal to the memory interaction module;
step S300: responding to the memory interaction module receiving the matching completion signal, reading the data head and each piece of sub data of the target data packet based on the memory interaction module for the second time, and sending the data head and each piece of sub data to the data processing module;
step S400: determining a second matching relation between the first-in first-out buffer sequence of the data output module and each downstream channel based on the data processing module, and sending the data head and each sub-data to the first-in first-out buffer sequence of the data output module based on the first matching relation and the second matching relation;
Step S500: the data header and the respective sub-data are sent to the respective downstream channels based on the data processing module.
The specific implementation of steps S100-S500 refers to various embodiments of the exemplary apparatus, and is not described herein in detail.
In the embodiment of the present application, after the memory interaction module receives the data reading instruction, the data distribution method further includes:
based on the memory interaction module analyzing the data reading instruction, determining the head address of the target data packet in a preset storage module;
Reading the data head of the target data packet from a preset storage module based on the head address;
determining the number of sub-data contained in the target data packet based on the data header;
And reading each piece of sub data from the storage module based on the head address and the number of the sub data.
In the embodiment of the application, the data head and each sub data are read in parallel from each storage block of the storage module based on the memory interaction module.
In the embodiment of the present application, after the memory interaction module reads the data header and each sub data of the target data packet, the data distribution method further includes:
And rearranging the acquired data head and each piece of sub data so as to enable the data head and each piece of sub data to be cached into a first-in first-out cache sequence of the memory interaction module according to the data sequence of each piece of sub data in the target data packet.
In the embodiment of the present application, after the header information processing module acquires the data header and each sub-data, the first matching relationship is determined according to the following manner:
extracting the data head and the first characteristic value of each sub data;
and determining a downstream channel matched with the data head and each piece of sub data based on the first characteristic value and preset register information of the data head and each piece of sub data.
In an embodiment of the present application, after the data processing module receives each sub-data, the data distribution method further includes:
extracting effective information of each sub-data to obtain target output data, wherein the target output data comprises a data head of the target data packet and each extracted sub-data, and sending the target output data to a first-in first-out buffer sequence of the data output module based on the first matching relation and the second matching relation.
In the embodiment of the present application, after the data processing module acquires the target data packet, the second matching relationship is determined according to the following manner:
Extracting a second characteristic value of the target data packet;
And determining a second matching relationship between the first-in first-out buffer sequence of the data output module and each downstream channel based on the second characteristic value.
In an embodiment of the present application, the data distribution method further includes:
determining a target first-in first-out buffer sequence corresponding to the data head and each sub data in the data output module based on the first matching relation and the second matching relation, wherein the data head and the target first-in first-out buffer sequence corresponding to any sub data are matched with the same downstream channel in the first matching relation and the second matching relation;
And respectively sending the data head and each piece of sub data to a corresponding target first-in first-out buffer sequence in the data output module based on the data processing module.
In an embodiment of the present application, after the data output module sends the data header and the respective sub-data to the corresponding downstream channels, the data distribution method further includes:
Transmitting a transmission completion instruction to the memory interaction module based on the data output module;
and transmitting synchronization information to a preset synchronous memory module based on the memory interaction module, wherein the synchronization information comprises the number of sub-data transmitted by a downstream channel in the data transmission.
The data distribution method provided by the embodiment of the present application is applied to the data distribution circuit described in any of the above embodiments, so that the data distribution circuit has at least all the beneficial effects of the above data distribution circuit, and is not described in detail herein.
Exemplary Medium
Having described the method, medium and system of the exemplary embodiment of the present application, next, a computer readable storage medium of the exemplary embodiment of the present application will be described with reference to fig. 6, and referring to fig. 6, the computer readable storage medium is shown as an optical disc 70, on which a computer program (i.e., a program product) is stored, where the computer program, when executed by a processor, implements the steps described in the above method embodiment, for example, in response to receiving a data reading instruction, reads, for the first time, a data header and each sub-data of a target data packet corresponding to the data reading instruction based on the memory interaction module, and sends the data header and each sub-data to the header information processing module; determining a first matching relation between the data head and each sub-data and each downstream channel based on the head information processing module, sending the first matching relation to the data processing module after the first matching relation is obtained, and sending a matching completion signal to the memory interaction module; responding to the memory interaction module receiving the matching completion signal, reading the data head and each piece of sub data of the target data packet based on the memory interaction module for the second time, and sending the data head and each piece of sub data to the data processing module; determining a second matching relation between the first-in first-out buffer sequence of the data output module and each downstream channel based on the data processing module, and sending the data head and each sub-data to the first-in first-out buffer sequence of the data output module based on the first matching relation and the second matching relation; the data header and the respective sub-data are sent to the respective downstream channels based on the data processing module. The specific implementation of each step is not repeated here. It should be noted that examples of the computer readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical and magnetic storage media, which are not described herein in detail.
Exemplary chip
Having described the methods, circuits, and media of exemplary embodiments of the present application, the chips of exemplary embodiments of the present application are described next.
In an embodiment of the present application, a chip is provided, including the data distribution circuit described in any one of the above embodiments. The chip includes the data distribution circuit in any of the above embodiments, so that all the beneficial effects of the data distribution circuit in the above embodiments are not described herein.
Finally, it should be noted that: the above examples are only specific embodiments of the present application, and are not intended to limit the scope of the present application, but it should be understood by those skilled in the art that the present application is not limited thereto, and that the present application is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Furthermore, although the operations of the methods of the present application are depicted in the drawings in a particular order, this is not required or suggested that these operations must be performed in this particular order or that all of the illustrated operations must be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform.

Claims (20)

1.一种数据分发电路，包括：内存交互模块、头信息处理模块、数据处理模块和数据输出模块；1. A data distribution circuit, comprising: a memory interaction module, a header information processing module, a data processing module and a data output module; 所述内存交互模块被配置为：响应于收到数据读取指令，第一次读取所述数据读取指令对应的目标数据包的数据头和各个子数据，并将所述数据头和所述各个子数据发送至所述头信息处理模块；The memory interaction module is configured to: in response to receiving a data read instruction, read a data header and each sub-data of a target data packet corresponding to the data read instruction for the first time, and send the data header and each sub-data to the header information processing module; 所述头信息处理模块被配置为：响应于接收到所述数据头和各个子数据，确定所述数据头及所述各个子数据与各个下游通道的第一匹配关系，并将所述第一匹配关系发送至所述数据处理模块，以及向所述内存交互模块发送匹配完成信号；The header information processing module is configured to: in response to receiving the data header and each sub-data, determine a first matching relationship between the data header and each sub-data and each downstream channel, send the first matching relationship to the data processing module, and send a matching completion signal to the memory interaction module; 所述内存交互模块还被配置为：响应于收到所述匹配完成信号，第二次读取所述目标数据包的数据头和各个子数据，并将所述数据头和所述各个子数据发送至所述数据处理模块；The memory interaction module is further configured to: in response to receiving the matching completion signal, read the data header and each sub-data of the target data packet for a second time, and send the data header and each sub-data to the data processing module; 所述数据处理模块被配置为：响应于接收到所述数据头和所述各个子数据，确定所述数据输出模块的先进先出缓存序列与所述各个下游通道的第二匹配关系，并基于所述第一匹配关系和所述第二匹配关系，将所述数据头和所述各个子数据发送至所述数据输出模块的先进先出缓存序列；The data processing module is configured to: in response to receiving the data header and the respective sub-data, determine a second matching relationship between a first-in-first-out cache sequence of the data output module and the respective downstream channels, and send the data header and the respective sub-data to the first-in-first-out cache sequence of the data output module based on the first matching relationship and the second matching relationship; 所述数据输出模块被配置为：响应于接收到的所述数据头和所述各个子数据，将所述数据头和所述各个子数据发送至相应的下游通道。The data output module is configured to: in response to the received data header and the respective sub-data, send the data header and the respective sub-data to a corresponding downstream channel. 2.如权利要求1所述的数据分发电路，所述内存交互模块还被配置为：2. The data distribution circuit according to claim 1, wherein the memory interaction module is further configured to: 在收到所述数据读取指令后，解析所述数据读取指令，确定所述目标数据包在预设存储模块中的首地址；After receiving the data read instruction, parsing the data read instruction, determining the first address of the target data packet in the preset storage module; 基于所述首地址从预设存储模块中读取所述目标数据包的数据头；Reading a data header of the target data packet from a preset storage module based on the first address; 基于所述数据头确定所述目标数据包所包含的子数据的个数；Determining the number of sub-data contained in the target data packet based on the data header; 基于所述首地址和所述子数据的个数，从所述存储模块中读取所述各个子数据。Based on the first address and the number of the sub-data, each sub-data is read from the storage module. 3.如权利要求2所述的数据分发电路，所述内存交互模块还被配置为：从所述存储模块的各个存储块中并行读取所述数据头和所述各个子数据。3. According to the data distribution circuit as described in claim 2, the memory interaction module is also configured to: read the data header and the respective sub-data in parallel from the respective storage blocks of the storage module. 4.如权利要求1所述的数据分发电路，所述内存交互模块还被配置为：4. The data distribution circuit according to claim 1, wherein the memory interaction module is further configured to: 在每次获取到所述目标数据包的数据头和各个子数据后，将获取到的数据头和各个子数据重排，以使所述数据头和所述各个子数据按照各自在所述目标数据包内的顺序缓存至所述内存交互模块的先进先出缓存序列中。After each acquisition of the data header and each sub-data of the target data packet, the acquired data header and each sub-data are rearranged so that the data header and each sub-data are cached in the first-in-first-out cache sequence of the memory interaction module according to their respective order in the target data packet. 5.如权利要求1所述的数据分发电路，所述头信息处理模块还被配置为：5. The data distribution circuit according to claim 1, wherein the header information processing module is further configured to: 提取所述数据头和所述各个子数据的第一特征值；Extracting the first characteristic value of the data header and each sub-data; 基于所述数据头和所述各个子数据的第一特征值及预设寄存信息，确定所述数据头和所述各个子数据所匹配的下游通道。Based on the first characteristic values of the data header and each sub-data and the preset registration information, a downstream channel matching the data header and each sub-data is determined. 6.如权利要求1所述的数据分发电路，所述数据处理模块还被配置为：6. The data distribution circuit according to claim 1, wherein the data processing module is further configured to: 在收到所述各个子数据后，提取所述各个子数据的有效信息，得到目标输出数据，所述目标输出数据包括所述目标数据包的数据头和提取后的各个子数据，并基于所述第一匹配关系和所述第二匹配关系，将所述目标输出数据发送至所述数据输出模块的先进先出缓存序列。After receiving the sub-data, the valid information of the sub-data is extracted to obtain the target output data, which includes the data header of the target data packet and the extracted sub-data, and based on the first matching relationship and the second matching relationship, the target output data is sent to the first-in-first-out cache sequence of the data output module. 7.如权利要求1所述的数据分发电路，所述数据处理模块还被配置为：7. The data distribution circuit according to claim 1, wherein the data processing module is further configured to: 在获取到所述目标数据包后，提取所述目标数据包的第二特征值；After acquiring the target data packet, extracting a second characteristic value of the target data packet; 基于所述第二特征值，确定所述数据输出模块的先进先出缓存序列与所述各个下游通道的第二匹配关系。Based on the second characteristic value, a second matching relationship between the first-in-first-out cache sequence of the data output module and each of the downstream channels is determined. 8.如权利要求1所述的数据分发电路，所述数据处理模块还被配置为：8. The data distribution circuit according to claim 1, wherein the data processing module is further configured to: 基于所述第一匹配关系和所述第二匹配关系，确定所述数据头和所述各个子数据在所述数据输出模块内对应的目标先进先出缓存序列，其中，所述数据头和任一所述子数据对应的目标先进先出缓存序列，在所述第一匹配关系和所述第二匹配关系中均与同一个下游通道匹配；Based on the first matching relationship and the second matching relationship, determining a target first-in-first-out cache sequence corresponding to the data header and each sub-data in the data output module, wherein the target first-in-first-out cache sequence corresponding to the data header and any of the sub-data matches the same downstream channel in both the first matching relationship and the second matching relationship; 将所述数据头和所述各个子数据分别发送至各自在所述数据输出模块中对应的目标先进先出缓存序列。The data header and each sub-data are respectively sent to the corresponding target first-in-first-out cache sequence in the data output module. 9.如权利要求1所述的数据分发电路，所述数据输出模块还被配置为：9. The data distribution circuit according to claim 1, wherein the data output module is further configured to: 在将所述数据头和所述各个子数据发送至相应的下游通道后，向所述内存交互模块发送传输完成指令；After sending the data header and each sub-data to the corresponding downstream channel, sending a transmission completion instruction to the memory interaction module; 所述内存交互模块还被配置为：响应于接收到所述传输完成指令，向预设同步内存模块发送同步信息，所述同步信息包括本次数据传输向下游通道所发送的子数据的个数。The memory interaction module is further configured to: in response to receiving the transmission completion instruction, send synchronization information to the preset synchronization memory module, the synchronization information including the number of sub-data sent to the downstream channel in this data transmission. 10.一种数据分发方法，运用于如权利要求1-9任一项所述的数据分发电路，所述数据分发方法包括：10. A data distribution method, applied to the data distribution circuit according to any one of claims 1 to 9, the data distribution method comprising: 响应于收到数据读取指令，基于所述内存交互模块第一次读取所述数据读取指令对应的目标数据包的数据头和各个子数据，并将所述数据头和所述各个子数据发送至所述头信息处理模块；In response to receiving a data read instruction, the memory interaction module reads a data header and each sub-data of a target data packet corresponding to the data read instruction for the first time, and sends the data header and each sub-data to the header information processing module; 基于所述头信息处理模块确定所述数据头及所述各个子数据与各个下游通道的第一匹配关系，并在得到所述第一匹配关系后，将所述第一匹配关系发送至所述数据处理模块，以及向所述内存交互模块发送匹配完成信号；Determine a first matching relationship between the data header and each sub-data and each downstream channel based on the header information processing module, and after obtaining the first matching relationship, send the first matching relationship to the data processing module, and send a matching completion signal to the memory interaction module; 响应于所述内存交互模块收到所述匹配完成信号，基于所述内存交互模块第二次读取所述目标数据包的数据头和各个子数据，并将所述数据头和所述各个子数据发送至所述数据处理模块；In response to the memory interaction module receiving the matching completion signal, the memory interaction module reads the data header and each sub-data of the target data packet for the second time, and sends the data header and each sub-data to the data processing module; 基于所述数据处理模块确定所述数据输出模块的先进先出缓存序列与所述各个下游通道的第二匹配关系，并基于所述第一匹配关系和所述第二匹配关系，将所述数据头和所述各个子数据发送至所述数据输出模块的先进先出缓存序列；Determine a second matching relationship between a first-in-first-out cache sequence of the data output module and each downstream channel based on the data processing module, and send the data header and each sub-data to the first-in-first-out cache sequence of the data output module based on the first matching relationship and the second matching relationship; 基于所述数据处理模块将所述数据头和所述各个子数据发送至相应的下游通道。The data header and each sub-data are sent to a corresponding downstream channel based on the data processing module. 11.如权利要求10所述的数据分发方法，在所述内存交互模块收到所述数据读取指令后，所述数据分发方法还包括：11. The data distribution method according to claim 10, after the memory interaction module receives the data reading instruction, the data distribution method further comprises: 基于所述内存交互模块解析所述数据读取指令，确定所述目标数据包在预设存储模块中的首地址；Parsing the data read instruction based on the memory interaction module to determine the first address of the target data packet in the preset storage module; 基于所述首地址从预设存储模块中读取所述目标数据包的数据头；Reading a data header of the target data packet from a preset storage module based on the first address; 基于所述数据头确定所述目标数据包所包含的子数据的个数；Determining the number of sub-data contained in the target data packet based on the data header; 基于所述首地址和所述子数据的个数，从所述存储模块中读取所述各个子数据。Based on the first address and the number of the sub-data, each sub-data is read from the storage module. 12.如权利要求11所述的数据分发方法，还包括：基于所述内存交互模块从所述存储模块的各个存储块中并行读取所述数据头和所述各个子数据。12. The data distribution method according to claim 11 further comprises: reading the data header and the sub-data in parallel from the storage blocks of the storage module based on the memory interaction module. 13.如权利要求10所述的数据分发方法，在所述内存交互模块读取到所述目标数据包的数据头和各个子数据后，所述数据分发方法还包括：13. The data distribution method according to claim 10, after the memory interaction module reads the data header and each sub-data of the target data packet, the data distribution method further comprises: 将获取到的数据头和各个子数据重排，以使所述数据头和所述各个子数据按照各自在所述目标数据包内顺序缓存至所述内存交互模块的先进先出缓存序列中。The acquired data header and each sub-data are rearranged so that the data header and each sub-data are cached in a first-in-first-out cache sequence of the memory interaction module according to their respective sequences in the target data packet. 14.如权利要求10所述的数据分发方法，在所述头信息处理模块获取到所述数据头和所述各个子数据后，按照如下方式确定所述第一匹配关系：14. The data distribution method according to claim 10, after the header information processing module obtains the data header and each sub-data, the first matching relationship is determined in the following manner: 提取所述数据头和所述各个子数据的第一特征值；Extracting the first characteristic value of the data header and each sub-data; 基于所述数据头和所述各个子数据的第一特征值及预设寄存信息，确定所述数据头和所述各个子数据所匹配的下游通道。Based on the first characteristic values of the data header and each sub-data and the preset registration information, a downstream channel matching the data header and each sub-data is determined. 15.如权利要求10所述的数据分发方法，在所述数据处理模块收到所述各个子数据后，所述数据分发方法还包括：15. The data distribution method according to claim 10, after the data processing module receives the sub-data, the data distribution method further comprises: 提取所述各个子数据的有效信息，得到目标输出数据，所述目标输出数据包括所述目标数据包的数据头和提取后的各个子数据，并基于所述第一匹配关系和所述第二匹配关系，将所述目标输出数据发送至所述数据输出模块的先进先出缓存序列。Extract valid information of each sub-data to obtain target output data, wherein the target output data includes a data header of the target data packet and each extracted sub-data, and based on the first matching relationship and the second matching relationship, send the target output data to a first-in-first-out cache sequence of the data output module. 16.如权利要求10所述的数据分发方法，在所述数据处理模块获取到所述目标数据包后，按照如下方式确定所述第二匹配关系：16. The data distribution method according to claim 10, after the data processing module obtains the target data packet, the second matching relationship is determined in the following manner: 提取所述目标数据包的第二特征值；Extracting a second characteristic value of the target data packet; 基于所述第二特征值，确定所述数据输出模块的先进先出缓存序列与所述各个下游通道的第二匹配关系。Based on the second characteristic value, a second matching relationship between the first-in-first-out cache sequence of the data output module and each of the downstream channels is determined. 17.如权利要求10所述的数据分发方法，还包括：17. The data distribution method according to claim 10, further comprising: 基于所述第一匹配关系和所述第二匹配关系，确定所述数据头和所述各个子数据在所述数据输出模块内对应的目标先进先出缓存序列，其中，所述数据头和任一所述子数据对应的目标先进先出缓存序列，在所述第一匹配关系和所述第二匹配关系中均与同一个下游通道匹配；Based on the first matching relationship and the second matching relationship, determining a target first-in-first-out cache sequence corresponding to the data header and each sub-data in the data output module, wherein the target first-in-first-out cache sequence corresponding to the data header and any of the sub-data matches the same downstream channel in both the first matching relationship and the second matching relationship; 基于所述数据处理模块将所述数据头和所述各个子数据分别发送至各自在所述数据输出模块中对应的目标先进先出缓存序列。Based on the data processing module, the data header and each sub-data are respectively sent to the corresponding target first-in-first-out cache sequence in the data output module. 18.如权利要求10所述的数据分发方法，在所述数据输出模块将所述数据头和所述各个子数据发送至相应的下游通道后，所述数据分发方法还包括：18. The data distribution method according to claim 10, after the data output module sends the data header and the sub-data to the corresponding downstream channel, the data distribution method further comprises: 基于所述数据输出模块向所述内存交互模块发送传输完成指令；Sending a transmission completion instruction to the memory interaction module based on the data output module; 基于内存交互模块向预设同步内存模块发送同步信息，所述同步信息包括本次数据传输向下游通道所发送的子数据的个数。The memory interaction module sends synchronization information to the preset synchronization memory module, where the synchronization information includes the number of sub-data sent to the downstream channel for this data transmission. 19.一种可读存储介质，其包括指令，当其在计算设备上运行时，使得计算设备执行如权利要求10-18任一项所述的方法。19. A readable storage medium comprising instructions, which, when executed on a computing device, causes the computing device to execute the method according to any one of claims 10 to 18. 20.一种芯片，包括如权利要求1-9任一项所述的数据分发电路。20. A chip comprising the data distribution circuit according to any one of claims 1 to 9.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112804027A (en) * 2019-11-14 2021-05-14 上海讯析电子科技有限公司 Data packet generation method and device and data reading method and device
CN116361209A (en) * 2023-02-16 2023-06-30 四川九洲防控科技有限责任公司 Method, system and equipment for reporting radar processing information

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022104611A1 (en) * 2020-11-18 2022-05-27 京东方科技集团股份有限公司 Data distribution system and data distribution method
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CN115902830A (en) * 2022-12-04 2023-04-04 桂林理工大学 Water measurement LiDAR multi-channel high-speed real-time synchronous acquisition and storage system
CN117676398A (en) * 2023-12-01 2024-03-08 京信网络系统股份有限公司 Multi-channel data alignment method, device, system and storage medium

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112804027A (en) * 2019-11-14 2021-05-14 上海讯析电子科技有限公司 Data packet generation method and device and data reading method and device
CN116361209A (en) * 2023-02-16 2023-06-30 四川九洲防控科技有限责任公司 Method, system and equipment for reporting radar processing information

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