CN119200810A

CN119200810A - Thread running method, device and electronic device

Info

Publication number: CN119200810A
Application number: CN202411195863.9A
Authority: CN
Inventors: 龙伟
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2024-08-28
Filing date: 2024-08-28
Publication date: 2024-12-27

Abstract

The present application discloses a thread operation method, device and electronic device, belonging to the field of terminal technology. The method comprises: when the application is in a scene switching state, determining the key thread associated with the scene switching; assigning the key thread to the target processor core for operation; when the target processor core is running the key thread, adjusting the operating frequency of the target processor core from the first frequency to the second frequency, wherein the second frequency is greater than the first frequency.

Description

Thread running method and device and electronic equipment

Technical Field

The application belongs to the technical field of terminals, and particularly relates to a thread running method and device and electronic equipment.

Background

In the process of running an application program containing a plurality of scenes on a device such as a mobile phone, a computer and the like, all scenes are not loaded at one time usually due to the limitations of technology and engines, but only the scene currently required by a user is loaded, and when the user needs to switch from the current scene to a new scene, the new scene is loaded again. Since a new scene requires a relatively long loading time, the time consumed for scene switching is long, which has a certain influence on the use experience of the application.

In order to solve the above-mentioned problem, in the related art, each time an application is in a state of scene change, the frequency of all processor cores in the processor is increased to improve the performance of the processor and reduce the time consumption of the scene change. However, this method of reducing time consumption adds additional power consumption. Therefore, how to balance performance and power consumption is a problem to be solved.

Disclosure of Invention

The embodiment of the application aims to provide a thread running method and device and electronic equipment, so as to balance performance and power consumption of an application program of the existing equipment in a scene switching process.

In a first aspect, an embodiment of the present application provides a method for running a thread, where the method includes:

Determining a key thread associated with scene switching when the application program is in a scene switching state;

Distributing the key thread to a target processor core for running;

And under the condition that the target processor core runs the key thread, adjusting the running frequency of the target processor core from a first frequency to a second frequency, wherein the second frequency is larger than the first frequency.

In a second aspect, an embodiment of the present application provides a thread running apparatus, where the apparatus includes:

The determining module is used for determining a key thread associated with scene switching when the application program is in a scene switching state;

The distribution module is used for distributing the key threads to a target processor core for running;

And the adjusting module is used for adjusting the operation frequency of the target processor core from a first frequency to a second frequency under the condition that the target processor core operates the key thread, wherein the second frequency is larger than the first frequency.

In a third aspect, an embodiment of the application provides an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method as provided in the first aspect.

In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which when executed by a processor perform the steps of the method as provided in the first aspect.

In a fifth aspect, an embodiment of the present application provides a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being configured to execute programs or instructions to implement a method as provided in the first aspect.

In a sixth aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement a method as provided in the first aspect.

In the method, the device and the electronic equipment for operating the threads, the key threads related to scene switching can be determined, the key threads are distributed to the proper target processor cores to operate, and the operating frequency of the target processor cores is increased under the condition that the key threads operate on the target processor cores. In this way, it is ensured that critical threads associated with scene cuts run on high performance processor cores, and by adjusting the operating frequency of the processor cores, it is ensured that these critical tasks can obtain sufficient processor resources during scene cuts. Meanwhile, the application only improves the operating frequency of the processor core where the key thread is located when the key thread operates, but not improves the operating frequency of all the processor cores for a long time, can improve the efficiency of scene switching with lower power consumption, and reduces unnecessary power consumption expenditure. And finally, balance performance and power consumption are realized.

Drawings

FIG. 1 is a flow diagram of a method of operating a thread according to one embodiment of the present application;

FIG. 2 is a schematic diagram of a thread running device according to another embodiment of the present application;

fig. 3 is a schematic structural diagram of an electronic device according to another embodiment of the present application;

fig. 4 is a schematic hardware structure of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or otherwise described herein, and that the objects identified by "first," "second," etc. are generally of a type not limited to the number of objects, for example, the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

In order to solve the technical problems, the application provides a thread running method. The thread running method provided by the embodiment of the application is described in detail below through specific embodiments and application scenes thereof with reference to the accompanying drawings.

As shown in fig. 1, fig. 1 is a flow chart of a thread running method according to an embodiment of the present application, where the method may include:

S101, determining a key thread associated with scene switching when an application program is in a scene switching state;

In this embodiment, the state of scene switching refers to a process in which an application program switches from one scene or view to another scene or view. In this process, the application needs to load and render new content, so this state can involve a large number of data processing and graphics rendering operations, and scene switching takes a long time. For example, the application may be a game application in which scene switching is required when switching from one game level to another game level, or a multimedia application in which scene switching is required when switching from one video play scene to another video play scene.

A critical thread refers to a thread in a system or application that takes on the main workload and has a direct impact on performance and response time. Such threads are typically high priority, ensuring that they complete tasks in time to avoid system bottlenecks or delays.

While in a state where the application is associated with scene cuts, the critical thread may be a critical task in the scene cuts, and the critical thread may directly affect the efficiency and time consumption of the scene cuts. For example, a critical thread may be a task that loads resources such as images, audio, and model files that are needed for a new scene, and a critical thread may also be a task that renders images in a new scene.

In some embodiments, S101 comprises:

and determining a key thread associated with scene switching in the case that the frame interval of the application program is greater than a threshold value.

In this embodiment, the frame interval of the application program refers to the interval of the generation time of the two adjacent frames, and the application program can continuously monitor the interval of the generation time of the two adjacent frames, and the interval of the generation time of the two adjacent frames is larger because more contents need to be loaded in the scene switching state. If the frame interval is monitored to be smaller than or equal to the preset threshold value, the application program can be considered to be in a state of scene switching.

In this way as described above, it is possible to accurately determine whether the application is in the state of scene change.

In some embodiments, S101 comprises:

and determining the task which wakes up the rendering task of the application program in the target time period as a key thread associated with scene switching.

In this embodiment, in determining a key thread associated with scene change, a rendering task for rendering an image in an application program may be first determined, and then, based on the determined rendering task, a task that wakes up the rendering task within a target period of time may be determined. Specifically, the task that wakes up the rendering task is a task for notifying or activating the rendering task to start executing. Both the rendering task and the task that wakes up the rendering task within the target time period may be determined to be critical threads associated with scene cuts. The target time period may be a first time period before the current time, where the first time period may be 1 second or 3 seconds.

For example, in the case where the application is a game application, the rendering task is a task for rendering a game scene, a character, and a special effect, and the task that wakes up the rendering task may be a task for processing user input, physical engine calculation, or AI logic, and after these tasks are completed, the rendering task may be waken up to perform image rendering.

By the method, all tasks directly related and indirectly related to image rendering can be quickly identified, and accurately determined to be key threads.

In some embodiments, the number of critical threads is less than or equal to the number of processor cores.

In this embodiment, after determining that the task of the rendering task of the application program is awakened in the target period of time is a critical thread, the number of critical threads at this time may be acquired, the number of processor cores in the electronic device may be acquired, and the critical threads may be adjusted based on the number of processor cores, so that the number of critical threads is less than or equal to the number of processor cores.

In particular, since critical threads are critical tasks that have a greater impact on the efficiency of scene cuts that require optimization, each processor core is only able to allocate one critical thread at most. Taking the number of key threads as N, the number of processor cores as M as an example, and N and M are positive integers. Then, when the number N of critical threads related to image rendering is greater than the number M of processor cores, a task having the greatest influence on system performance needs to be selected from the N critical threads for priority processing. Under the condition that one processor core corresponds to one key thread, M key threads with the maximum CPU utilization rate can be selected from N key threads to serve as key threads needing to be processed preferentially, and tasks except the M key threads are modified to be non-key threads.

When the number N of critical threads associated with image rendering is less than or equal to the number M of processor cores, the task processor may have sufficient resources to optimize all critical threads, so all N critical threads may be reserved for optimization as critical threads.

In this embodiment, by using the method, the key thread with high CPU utilization rate can be used as the key thread, and it can be ensured that the system resource is preferentially allocated to the task with the greatest influence on performance among the tasks related to image rendering, so as to maximize the system performance and response speed, and improve the efficiency of image rendering and scene switching as much as possible.

S102, distributing the key thread to a target processor core for operation;

In the embodiment of the application, after the critical thread is determined, the critical thread bears the main workload and has direct influence on the performance and response time, so that the priority of the critical thread is higher, and the critical thread needs to be distributed to a target processor core for running in order to ensure that the critical thread is processed preferentially, wherein the target processor core can be the processor core with the best performance in a processor or the processor core with the lowest load state in the processor.

In some embodiments, the number of critical threads is greater than 1, and s102 comprises:

And distributing the key thread with the highest CPU utilization rate to the core operation of the ultra-large core processor.

In this embodiment, one processor may include a plurality of processor cores that may be individually operated with different processor cores having different performances, and the plurality of processor cores may be divided into a super large core processor core, a large core processor core, and a small core processor core based on the performances of the different processor cores. The performance of the oversized core processor core is higher than that of the large core processor core, and the performance of the large core processor core is higher than that of the small core processor core.

If there are also multiple critical threads, then the processor (Central Processing Unit, CPU) usage for the critical threads may be based. The CPU utilization of a critical thread refers to the proportion of the total run time of the critical thread that occupies the processor core over a period of time. The CPU utilization can characterize the actual load condition of the critical thread, and after determining the CPU utilization of the critical thread, the processor cores can be allocated to the critical thread based on the CPU utilization of the critical thread.

Specifically, if the CPU utilization of the critical thread is high, the critical thread may be allocated to the processor core with better performance, and if the CPU utilization of the critical thread is low, the critical thread may be allocated to the processor core with poorer performance, so that the critical thread with the highest CPU utilization may be allocated to the oversized core processor core with the best performance to run. In this way, the thread running efficiency can be ensured.

For example, in the case that P processor cores are included in the processor and the number of critical threads is also P, the P critical threads may be sequentially allocated to P processor cores with performance from high to low in order of from high to low in CPU usage of the P critical threads, where each processor core is allocated to one critical thread, and P is a positive integer greater than 1.

In this embodiment, if the processor includes P processor cores and the critical threads are also exactly P, the P critical threads may be sequentially allocated to P processor cores with performance from high to low in order of from high to low in CPU usage of the P critical threads.

For example, P may be 3, where the processor includes a core 1, a core 2, and a core 3, where the core 1 is the highest performing processor core, i.e., the oversized core processor core, the core 2 is the next highest performing processor core, i.e., the oversized core processor core, and the core 3 is the lowest performing processor core, i.e., the small core processor core, and the 3 critical threads include a task A, a task B, and a task C, where the CPU utilization of the task A is 70%, the CPU utilization of the task B is 60%, the CPU utilization of the task C is 50%, and the task A may be allocated to the core 1, the task B to the core 2, and the task C to the core 3.

In this way, it is ensured that high load tasks are distributed to the high performance cores, thereby optimizing overall system performance and response speed. By the mode, the resources of the processor can be effectively utilized, and the processing efficiency of the system is improved.

S103, under the condition that the target processor core runs the key thread, adjusting the running frequency of the target processor core from a first frequency to a second frequency, wherein the second frequency is larger than the first frequency.

In this embodiment, the operating frequency of the processor core, i.e., the number of oscillation cycles the processor core executes per second. Since the critical thread is a critical task related to scene switching in the scene switching state, in the process that the critical thread runs on the target processor core, the running frequency of running the target processor core needs to be increased to increase the processing speed of the critical thread.

Specifically, when the key thread is not running, the running frequency of the target processor core is the initial first frequency, and when the key thread is detected to run on the target processor core, the running frequency of the target processor core can be increased from the initial first frequency to the second frequency.

In some embodiments, the adjusting the operating frequency of the target processor core from a first frequency to a second frequency comprises:

the method comprises the steps of adjusting a minimum constraint value of a task utilization rate corresponding to a key thread to be a first proportion, and adjusting a maximum constraint value of the task utilization rate corresponding to the key thread to be a second proportion, wherein the first proportion is larger than a first default proportion of the minimum constraint value, the second proportion is larger than a second default proportion of the maximum constraint value, and operating frequencies corresponding to the first default proportion and the second default proportion are the first frequency;

And adjusting the operating frequency of the target processor core from the first frequency to the second frequency according to the adjusted first proportion and second proportion.

In this embodiment, the task utilization is used to indicate the busyness of the processor. The minimum constraint value and the maximum constraint value of the task utilization rate together form a constraint condition of the proportion of the running time of the key thread to the total time, wherein the minimum constraint value of the task utilization rate corresponding to the key thread is used for representing, the key thread obtains the minimum proportion of processor time in the executing process, and the maximum constraint value of the task utilization rate corresponding to the key thread is used for representing, and the key thread obtains the maximum proportion of processor time in the executing process.

The application program can adjust the operating frequency corresponding to the key thread based on the minimum constraint value and the maximum constraint value of the task utilization rate when the task is operated. Illustratively, in the case where both the minimum constraint value and the maximum constraint value are scaled up, in order to guarantee that more resources are available to critical threads, an optimal balance of performance and energy efficiency may be achieved by dynamically scaling up the processor frequency.

Specifically, the first default ratio is a default ratio of a preset minimum constraint value of the task utilization rate, the second default ratio is a default ratio of a preset maximum constraint value of the task utilization rate, after the critical thread is determined, the minimum constraint value and the maximum constraint value of the corresponding task utilization rate of the critical thread can be increased on the basis of the default ratio, the minimum constraint value is adjusted from the first default ratio to the first ratio, the maximum constraint value is adjusted from the second default ratio to the second ratio, and therefore, the application program can adjust the running frequency of the target processor core when the critical thread runs from the initial first frequency to the second frequency based on the adjusted first ratio and second ratio.

Illustratively, the first default proportion of task utilization is 30%, the second default proportion of task utilization is 50%, the first proportion is 40%, and the second proportion is 70%. Then, after determining the critical thread, the minimum constraint value of the task utilization of the critical thread may be increased from 30% to 40%, and the maximum constraint value of the task utilization of the critical thread may be increased from 50% to 70%. In this way, the operating frequency of the target processor core during the operation of the critical thread can be adjusted from the initial first frequency to the second frequency based on the adjusted first proportion and the second proportion, so that the execution duration of the critical thread is shortened.

In this way, the processor frequency is dynamically adjusted by increasing the minimum constraint value and the maximum constraint value of the task utilization, so as to achieve the optimal balance of performance and energy efficiency.

In some embodiments, the task information of the critical thread is stored in a critical thread list, and if a critical thread is removed from the critical thread list, the minimum constraint value of the task utilization of the removed critical thread is adjusted to be a first default proportion, and the maximum constraint value of the task utilization is adjusted to be the second default proportion.

In this embodiment, the critical thread list is a data structure or collection that stores critical tasks, i.e., critical threads, that are identified as important for system performance and task execution in a particular scenario. The tasks stored in the critical thread list are critical tasks with higher priority in the current scene, and more resources need to be allocated or better optimized.

Then, in the state that the application program is in scene switching, the task associated with image rendering may be first stored as a critical task that is important in the critical thread list, then the number of critical threads and the number of processor cores may be compared, if the number N of tasks associated with image rendering is greater than the number M of processor cores, M of the N critical threads that have the greatest influence on the system performance need to be selected as a final critical thread, and critical threads other than the M critical threads are removed from the critical thread list, and the adjustment of the task utilization and the allocation of the processor cores are performed on the critical threads in the critical thread list.

At this time, the critical thread in the critical thread list is in a critical state, if the critical thread is updated, there is a critical thread that the critical thread is originally in the critical state, after the update, the critical thread is cancelled from the critical state, and is no longer the critical thread. Then the critical thread needs to be removed from the critical thread list, after which the minimum constraint value of the task utilization of the critical thread needs to be reduced to a first default ratio and the maximum constraint value of the task utilization needs to be reduced to a second default ratio in order to avoid excessive processor resources occupied by the critical thread that cancels the critical state.

By the method, the resources of the processor can be guaranteed to be allocated to the most critical tasks at present in real time, waste of the processor resources is avoided, and additional power consumption is avoided.

In the application, the key thread associated with the scene switching can be determined and distributed to the proper target processor core for running, and in the case that the key thread runs on the target processor core, the running frequency of the target processor core is increased. In this way, it is ensured that critical threads associated with scene cuts run on high performance processor cores, and by adjusting the operating frequency of the processor cores, it is ensured that these critical tasks can obtain sufficient processor resources during scene cuts. Meanwhile, the application only improves the operating frequency of the processor core where the key thread is located when the key thread operates, but not improves the operating frequency of all the processor cores for a long time, can improve the efficiency of scene switching with lower power consumption, and reduces unnecessary power consumption expenditure. And finally, balance performance and power consumption are realized.

FIG. 2 is a schematic structural diagram of a thread running device according to another embodiment of the present application, where, as shown in FIG. 2, the thread running device may include:

a determining module 201, configured to determine a key thread associated with scene switching when the application is in a state of scene switching;

an allocation module 202, configured to allocate the critical thread to a target processor core operation;

and the adjusting module 203 is configured to adjust the operating frequency of the target processor core from a first frequency to a second frequency when the target processor core is running the critical thread, where the second frequency is greater than the first frequency.

In another alternative example, the determining module 201 includes:

and the first determining unit is used for determining a key thread associated with scene switching under the condition that the frame interval of the application program is larger than a threshold value.

In another alternative example, the determining module 201 includes:

And the second determining unit is used for determining the task which is awakened by the rendering task of the application program in the target time period as the key thread associated with scene switching.

In another alternative example, the number of critical threads is less than or equal to the number of processor cores.

In another alternative example, the number of critical threads is greater than 1, and the allocation module 202 includes:

And the distribution unit is used for distributing the key thread with the highest CPU utilization rate to the core operation of the ultra-large core processor.

The running device of the thread in the embodiment of the application can be electronic equipment, and also can be a component in the electronic equipment, such as an integrated circuit or a chip. The electronic device may be a terminal, or may be other devices than a terminal. By way of example, the electronic device may be a Mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a Mobile internet appliance (Mobile INTERNET DEVICE, MID), an augmented reality (augmented reality, AR)/Virtual Reality (VR) device, a robot, a wearable device, an ultra-Mobile personal computer (UMPC), a netbook or a personal digital assistant (personal DIGITAL ASSISTANT, PDA), etc., a server, a network attached storage (NetworkAttached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine, a self-service machine, etc., a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine, a self-service machine, etc., and the embodiments of the present application are not limited in particular.

The running device of the thread in the embodiment of the application can be a device with an operating system. The operating system may be an Android operating system, an IOS operating system, or other possible operating systems, and the embodiment of the present application is not limited specifically.

The thread running device provided in the embodiment of the present application can implement each process implemented by the method embodiment of fig. 1, and in order to avoid repetition, details are not repeated here.

Optionally, as shown in fig. 3, the embodiment of the present application further provides an electronic device 100, including a processor 110, a memory 119, and a program or an instruction stored in the memory 119 and capable of being executed on the processor 110, where the program or the instruction implements each process of the above-mentioned embodiment of the thread running method when executed by the processor 110, and the same technical effects can be achieved, and for avoiding repetition, a description is omitted herein.

The electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device.

Referring to fig. 4 in combination, fig. 4 is a schematic hardware structure of an electronic device implementing an embodiment of the present application. The electronic device 100 includes, but is not limited to, a radio frequency unit 121, a network module 122, an audio output unit 123, an input unit 124, a sensor 125, a display unit 126, a user input unit 127, an interface unit 128, a memory 129, and a processor 120.

Those skilled in the art will appreciate that the electronic device 100 may further include a power source (e.g., a battery) for powering the various components, and that the power source may be logically coupled to the processor 120 via a power management system to perform functions such as managing charging, discharging, and power consumption via the power management system. The electronic device structure shown in fig. 4 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than shown, or may combine certain components, or may be arranged in different components, which are not described in detail herein.

The processor 120 is configured to determine a key thread associated with scene switching when the application is in a state of scene switching;

a processor 120 for distributing the critical thread to a target processor core operation;

And a processor 120 configured to adjust an operating frequency of the target processor core from a first frequency to a second frequency in a case where the target processor core is operating the critical thread, wherein the second frequency is greater than the first frequency.

In another alternative example, the processor 120 is further configured to:

In another alternative example, processor 120 is further configured to:

In another alternative example, the number of critical threads is greater than 1, and the processor 120 is further configured to allocate the critical thread with the highest CPU usage to the very large core processor core operation.

It should be appreciated that in embodiments of the present application, the input unit 124 may include a graphics processor (Graphics Processing Unit, GPU) 1241 and a microphone 1242, with the graphics processor 1241 processing image data of still pictures or video obtained by an image capture device (e.g., a camera) in a video capture mode or an image capture mode. The display unit 126 may include a display panel 1261, and the display panel 1261 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 127 includes at least one of a touch panel 1271 and other input devices 1272. Touch panel 1271 is also referred to as a touch screen. Touch panel 1271 may include two parts, a touch detection device and a touch controller. Other input devices 1272 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein.

The memory 129 may be used to store software programs and various data. The memory 129 may mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 129 may include volatile memory or nonvolatile memory, or the memory 129 may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (RandomAccess Memory, RAM), static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate Synchronous dynamic random access memory (Double DATA RATE SDRAM, DDRSDRAM), enhanced Synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCH LINK DRAM, SLDRAM), and Direct random access memory (DRRAM). Memory 129 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.

Processor 120 may include one or more processing units, and optionally processor 120 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, and the like, and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 120.

The embodiment of the application also provides a readable storage medium, and the readable storage medium stores a program or an instruction, which when executed by a processor, implements each process of the above-mentioned thread operation method embodiment, and can achieve the same technical effects, so that repetition is avoided, and no further description is given here.

The processor is a processor in the electronic device in the above embodiment. Readable storage media include computer readable storage media such as computer readable memory ROM, random access memory RAM, magnetic or optical disks, and the like.

The embodiment of the application further provides a chip, the chip comprises a processor and a communication interface, the communication interface is coupled with the processor, the processor is used for running programs or instructions, the processes of the running method embodiment of the threads can be realized, the same technical effects can be achieved, and the repetition is avoided, and the description is omitted here.

It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.

Embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the respective processes of the embodiments of the method of operating a thread as described above, and achieve the same technical effects, and are not repeated herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims

1. A method of operating a thread, comprising:

Distributing the key thread to a target processor core for running;

2. The method of claim 1, wherein determining the critical thread associated with the scene cut while the application is in the state of the scene cut comprises:

3. The method of claim 1, wherein the determining the critical thread associated with the scene cut comprises:

4. A method according to claim 3, wherein the number of critical threads is less than or equal to the number of processor cores.

5. The method of claim 1, wherein the number of critical threads is greater than 1, the assigning the critical threads to target processor core operations comprising:

6. A thread running apparatus, comprising:

7. The apparatus of claim 6, wherein the means for determining comprises:

8. The apparatus of claim 6, wherein the means for determining comprises:

9. The apparatus of claim 8, wherein the number of critical threads is less than or equal to the number of processor cores.

10. The apparatus of claim 6, wherein the number of critical threads is greater than 1, the allocation module comprising:

11. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method of operating a thread as claimed in any one of claims 1 to 5.