WO2024245116A1 - Task processing method and apparatus, and electronic device - Google Patents

Abstract

The present application relates to the technical field of computers. Provided are a task processing method and apparatus, and an electronic device. The method comprises: according to first parameter information of a first task, determining a scheduling priority of the first task, wherein the first parameter information comprises at least one of a task type and a task importance level; according to second parameter information of the first task, selecting a target processor core from among N processor cores, wherein the second parameter information comprises computing power demand information and the scheduling priority, with N being an integer greater than 1; and according to the scheduling priority of the first task, executing the first task on the target processor core.

Description

Task processing method, device and electronic equipment

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to the Chinese patent application filed with the China Patent Office on May 30, 2023, with application number 202310626134.3 and title “Task processing method, device and electronic device”, the entire contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of computer technology, and in particular to a task processing method, device and electronic equipment.

Background Art

A multi-core central processing unit (CPU) is a CPU with multiple processor cores, each of which can execute instructions independently, and multiple processor cores can execute different tasks at the same time, thereby improving the performance and efficiency of the processor. In addition, current operating systems are usually multi-threaded environments, and each processor core can execute multiple threads at the same time, thereby achieving concurrent execution. At present, fair scheduling of tasks on the CPU is usually based on the Completely Fair Scheduler (CFS), where CFS is a time-based scheduling algorithm that divides the CPU time into time slices and allocates a certain time slice to each process. Each task is processed within its corresponding time slice. However, this fair scheduling method is difficult to guarantee the processing effect of some tasks.

Summary of the invention

The embodiments of the present application provide a task processing method, device and electronic device, which can ensure the processing speed of some tasks and thus improve the fluency of these tasks.

In a first aspect, an embodiment of the present application provides a task processing method, the method comprising:

Determining a scheduling priority of the first task according to first parameter information of the first task, wherein the first parameter information includes at least one of a task type and a task importance level;

Selecting a target processor core from N processor cores according to second parameter information of the first task, wherein the second parameter information includes computing power requirement information and scheduling priority, and N is an integer greater than 1;

The first task is executed on the target processor core according to the scheduling priority of the first task.

In a second aspect, an embodiment of the present application provides a task processing device, the device comprising:

A first determination module, configured to determine a scheduling priority of the first task according to first parameter information of the first task, wherein the first parameter information includes at least one of a task type and a task importance level;

A first selection module, configured to select a target processor core from N processor cores according to second parameter information of the first task, wherein the second parameter information includes computing power requirement information and scheduling priority, and N is an integer greater than 1;

An execution module is used to execute the first task on the target processor core according to the scheduling priority of the first task.

In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps in the task processing method described in the first aspect are implemented.

In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps in the task processing method described in the first aspect are implemented.

In a fifth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the first aspect.

In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method described in the first aspect.

In a seventh aspect, an embodiment of the present application provides an electronic device, which is configured to execute the method described in the first aspect.

In an embodiment of the present application, the scheduling priority of the task is determined based on at least one of the task type and the task importance level, and the task is processed based on the scheduling priority. This can achieve priority scheduling of some tasks (for example, foreground tasks, etc.), thereby improving the processing speed of these tasks. In addition, in an embodiment of the present application, a target processor core is selected from N processor cores to process the task based on computing power demand information and scheduling priority. This is conducive to selecting more suitable processor cores (for example, processor cores with the strongest processing power or the largest remaining computing power, etc.) for processing some tasks, thereby improving the processing efficiency and fluency of these tasks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of a task processing method provided in an embodiment of the present application;

FIG2 is a schematic diagram of a multi-processor core provided in an embodiment of the present application;

FIG3 is a flow chart of another task processing method provided in an embodiment of the present application;

FIG4 is a schematic diagram of the structure of a task processing device provided in an embodiment of the present application;

FIG5 is a schematic diagram of a structure of an electronic device provided in an embodiment of the present application;

FIG. 6 is a second schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

Specific embodiments

The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, rather than to describe a specific order or precedence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and do not limit the number of objects. For example, the first object can be one, In addition, "and/or" in the specification and claims indicates at least one of the connected objects, and the character "/" generally indicates that the objects connected before and after are in an "or" relationship.

The task processing method, device and electronic device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

Referring to FIG. 1 , FIG. 1 is a flowchart of a task processing method provided in an embodiment of the present application, as shown in FIG. 1 , comprising the following steps:

Step 101: Determine a scheduling priority of a first task according to first parameter information of the first task, wherein the first parameter information includes at least one of a task type and a task importance level.

In this embodiment, the first task may be any task to be processed or scheduled.

The above task types can be reasonably set according to actual needs. For example, the above task types can include foreground tasks or background tasks, or the above task types can include multimedia tasks (for example, audio tasks, video tasks or game tasks, etc.) or non-multimedia tasks, etc. In some optional embodiments, the above front and back tasks can be further divided into video tasks located in the foreground, game tasks located in the foreground, tasks of small window applications located in the foreground, etc. Exemplarily, the task type can be identified based on one or more information such as the application package name, whether it is visible, whether it has focus, the state of the audio, and whether the input operation is frequent.

The above-mentioned task importance level is determined according to at least one of the task type, load size, computing power requirement information, etc. The above-mentioned computing power requirement information can be used to indicate the computing power value required to execute the task, for example, it can be a computing power value obtained by statistics based on the computing power values consumed by executing the same task multiple times in history, or it can be pre-divided into multiple computing power levels. The above-mentioned computing power requirement information can be used to indicate the computing power level corresponding to the task, for example, it can be pre-divided into a first computing power level and a second computing power level, the first computing power level is used to indicate that the required computing power is relatively large, and the second computing power level is used to indicate that the required computing power is relatively small, and the corresponding relationship between different tasks and computing power levels can be pre-established, for example, multimedia tasks (for example, audio tasks, video tasks or game tasks, etc.) correspond to the first computing power level, and non-multimedia tasks correspond to the second computing power level.

In some optional embodiments, task types may be divided first, and for tasks of the same task type, the task importance level of each task may be further determined. For example, tasks may be divided into foreground tasks and background tasks. For foreground tasks, the task importance level of each foreground task may be further determined. For example, the task importance level of multimedia foreground tasks (e.g., audio tasks, video tasks, or game tasks, etc.) is greater than the task importance level of non-multimedia foreground tasks.

The above scheduling priorities can be used to indicate the order in which tasks are scheduled, wherein a task with a higher scheduling priority is scheduled first. For example, in the same processor core, the scheduling priority of task a is scheduling priority a1, and the scheduling priority of task b is scheduling priority b1. If scheduling priority a1 is higher than scheduling priority b1, task a is scheduled before task b.

In one embodiment, if the first parameter information includes a task type, the scheduling priority of the first task can be determined according to the task type of the first task. For example, a corresponding relationship between the task type and the scheduling priority can be pre-established. For example, the foreground task corresponds to the scheduling priority a1, the background task corresponds to the second scheduling priority b1, and the first scheduling priority Level a1 is higher than the second scheduling priority b1, and thus the scheduling priority of the first task can be quickly determined based on the above correspondence and the task type of the first task.

In another embodiment, if the first parameter information includes the task importance level, the scheduling priority of the first task can be determined according to the task importance level of the first task. Exemplarily, a correspondence between the task importance level and the scheduling priority can be established in advance. For example, a task with a higher task importance level has a higher corresponding scheduling priority. Furthermore, the scheduling priority of the first task can be quickly determined based on the above correspondence and the task importance level of the first task.

In another embodiment, if the first parameter information includes task type and task importance level, the scheduling priority of the first task can be determined according to the task type and task importance level of the first task. Exemplarily, a correspondence between task type, task importance level and scheduling priority can be established. For example, the foreground task with task importance level a corresponds to scheduling priority a11, the foreground task with task importance level b corresponds to scheduling priority a12, and the background task corresponds to scheduling priority a2. If a is greater than b, the scheduling priority a11 is higher than the scheduling priority a12, and the scheduling priority a12 is higher than the scheduling priority a2. Therefore, the scheduling priority of the first task can be quickly determined based on the above-mentioned correspondence and the task type and task importance level of the first task.

Step 102: Select a target processor core from N processor cores according to second parameter information of the first task, wherein the second parameter information includes computing power requirement information and scheduling priority, and N is an integer greater than 1.

In this embodiment, the above computing power demand information and scheduling priority can refer to the above-mentioned related instructions and will not be repeated here.

The processing capabilities of each of the N processor cores may be the same; or, the N processor cores may include at least two types of processor cores with different processing capabilities. For example, the N processor cores may include a first type of processor core, a second type of processor core, and a third type of processor core, wherein the processing capability of the first type of processor core is stronger than that of the second type of processor core, and the processing capability of the second type of processor core is stronger than that of the third type of processor core. Exemplarily, as shown in FIG2 , it includes 1 large processor core, 4 medium processor cores, and 3 small processor cores, wherein processor cores of different sizes correspond to different processing capabilities, for example, the capability of a large processor core may be 3 times or even 4 times greater than that of a small processor core. Among them, the measurement index of the processing capability of the processor core may include but is not limited to the total computing power value of the processor core, that is, the larger the total computing power value, the stronger the processing capability, wherein the measurement index of the total computing power value may include but is not limited to the computing speed, cache size, etc.

Exemplarily, when the scheduling priority of the first task is higher than the preset priority, the processor core selection range of the first task can be determined from N processor cores based on the computing power requirement information of the first task, and the target processor core is selected from the processor core selection range; alternatively, the target load of each processor core can be calculated based on the scheduling priority of the first task, wherein the above-mentioned target load can be the sum of the loads of all tasks on the processor core whose scheduling priorities meet preset conditions, and the target processor core is selected from the N processor cores based on the computing power requirement information of the first task and the target load of each processor core. For example, the processor core selection range of the first task can be determined from N processor cores based on the computing power requirement information of the first task, and the processor core with the smallest target load can be selected as the target processor core from the processor core selection range.

Step 103: Execute the first task on the target processor core according to the scheduling priority of the first task.

In this embodiment, the target processor core schedules the tasks with higher scheduling priorities with higher priority. For example, the target processor core includes a foreground task a and a background task b, and the scheduling priority of the foreground task a is higher than the scheduling priority of the background task b. Then the target processor core schedules the foreground task a first, and schedules the background task b after processing all the foreground tasks a. It should be noted that for tasks with the same scheduling priority, they can be scheduled in sequence based on the order of the tasks in the task queue.

The task processing method provided in the embodiment of the present application determines the scheduling priority of the task according to at least one of the task type and the task importance level, and processes the task based on the scheduling priority, so that priority scheduling of some tasks (for example, foreground tasks, etc.) can be achieved, thereby improving the processing speed of these tasks. In addition, the embodiment of the present application selects a target processor core from N processor cores to process the task according to computing power demand information and scheduling priority, which is conducive to selecting more suitable processor cores (for example, processor cores with the strongest processing power or the largest remaining computing power, etc.) for processing some tasks, thereby improving the processing efficiency and fluency of these tasks.

Optionally, selecting a target processor core from N processor cores according to the second parameter information of the first task includes:

Calculate a first remaining computing power value of each processor core of the N processor cores according to the scheduling priority of the first task, the first remaining computing power value of the processor core is the difference between the total computing power value of the processor core and the first computing power value, and the first computing power value is the sum of the computing power values required for the load of all tasks in the processor core whose scheduling priority is higher than or equal to the scheduling priority of the first task;

A target processor core is determined according to the computing power requirement information of the first task and a first remaining computing power value of each processor core of the N processor cores.

The above-mentioned computing power requirement information, scheduling priority and N processor cores can be found in the relevant description of the aforementioned embodiment and will not be elaborated here.

In this embodiment, the sum of the load required computing power values of all tasks with a scheduling priority higher than or equal to the scheduling priority of the first task in each processor core can be calculated respectively, that is, the first computing power value of each processor core, and then the difference between the total computing power value of each processor core and the first computing power value is used as the first remaining computing power value of the processor core. For example, the scheduling priority of the first task is 3, and for the processor core CPU-7, the load required computing power value load-7 of all tasks with a scheduling priority higher than or equal to 3 in CPU-7 can be calculated, and the first remaining computing power value free-7 can be calculated based on the total computing power value cap-7 of CPU-7, that is, free-7 = cap-7–load-7.

After obtaining the first remaining computing power value of each of the N processor cores, the target processor core can be determined based on the computing power requirement information of the first task and the first remaining computing power value of each of the N processor cores. For example, a processor core can be selected as the target processor core from the processor cores whose first remaining computing power values can meet the computing power requirement information of the first task.

In this embodiment, when the N processor cores include at least two types of processor cores with different processing capabilities, processor core selection is performed based on the first remaining computing power value of each processor core, which is conducive to preferentially selecting a processor core with a stronger processing capability to process tasks with a higher scheduling priority, thereby improving the processing speed and fluency of tasks with a higher scheduling priority; when the processing capabilities of the N processor cores are all the same, the processor core selection is performed based on the first remaining computing power value of each processor core, thereby preferentially selecting a processor core with a stronger processing capability to process tasks with a higher scheduling priority; Performing processor core selection based on the first remaining computing power value of each processor core is beneficial to reducing the impact of tasks with lower scheduling priorities on tasks with higher scheduling priorities, and improving the processing speed of tasks with higher scheduling priorities.

Optionally, determining the target processor core according to the computing power requirement information of the first task and the first remaining computing power value of each processor core of the N processor cores includes:

Determining a first processor core selection range according to the computing power requirement information of the first task, wherein the N processor cores include at least two types of processor cores, different types of processor cores in the at least two types of processor cores have different processing capabilities, and the first processor core selection range includes at least two processor cores in the N processor cores;

The target processor core is determined according to the first remaining computing power values of the processor cores within the first processor core selection range.

In this embodiment, each type of processor core may include one or more processor cores. For example, the N processor cores may include a first type of processor core and a second type of processor core, wherein the first type of processor core includes L processor cores, the second type of processor core includes K processor cores, L+K=N, and the processing capability of the first type of processor core is stronger than that of the second type of processor core, then the processor core with the smallest first load may be selected from the L processor cores as the first processor core.

It should be noted that the processing capabilities of the multiple processor cores included in each type of processor core may be the same, or the difference between the processing capabilities of the multiple processor cores included in each type of processor core is within a preset range. It should also be noted that the structures or models of the multiple processor cores included in each type of processor core may be the same or different.

In practical applications, the computing power requirement information of each task can be pre-statisticed through experimental simulation and other methods, and then a correspondence between the computing power requirement information and the processor core selection range can be established based on the computing power requirement information of each task, wherein the computing power of the processor core within the above processor core selection range can meet the computing power requirement information of the corresponding task.

In some optional embodiments, when the above-mentioned computing power requirement information is the computing power level, a correspondence between the computing power level and the processor core selection range can be established, wherein different computing power levels correspond to different processor core selection ranges, and the higher the computing power level (that is, the more computing power required), the stronger the processing capability of the processor core within the corresponding processor core selection range. This is conducive to preferentially selecting processor cores with stronger processing capabilities to process tasks requiring greater computing power.

For example, the above-mentioned N processor cores include 8 processor cores, namely CPU-0 to CPU-7, among which CPU-7 is a large processor core, CPU-4 to CPU-6 are all medium processor cores, and CPU-0 to CPU-3 are all small processor cores, among which the processing power of the large processor core is stronger than that of the medium processor core, and the processing power of the medium processor core is stronger than that of the small processor core. Task A is a task of a small window application (for example, a small window task of a video application or a small window task that should be included in instant messaging, etc.), which requires less computing power, and the corresponding processor core selection range is CPU-0 to CPU-6, that is, Task A can select a processor core from CPU-0 to CPU-6; Task B is a game task, which requires more computing power, and the corresponding processor core selection range is CPU-0 to CPU-7, that is, Task B can select a processor core from CPU-0 to CPU-7.

In this embodiment, when there are multiple tasks with the same scheduling priority (for example, multiple foreground tasks), the selection range of the processor cores corresponding to each task can be determined based on the computing power requirement information of each task, and the selection range of the processor cores corresponding to each task can be determined respectively. The processor core corresponding to each task is selected within the selection range of the processor core corresponding to the task. This can reduce the situation where multiple tasks with the same scheduling priority but different computing power requirements select the same processor core. This can not only reduce the mutual influence between the above-mentioned multiple tasks, but also reduce the overhead of migrating tasks on different processor cores.

In some optional embodiments, the first processor core selection range can be determined based on the computing power requirement information of the first task, and then the first remaining computing power value of each processor core within the first processor core selection range can be calculated based on the scheduling priority of the first task, and the target processor core can be determined based on the first remaining computing power value of each processor core within the first processor core selection range. This can reduce the calculation of the remaining computing power of the processor core and save system resources.

Optionally, determining the target processor core according to the first remaining computing power value of each processor core within the first processor core selection range includes:

Determine the processor core with the largest first remaining computing power value within the first processor core selection range as the target processor core;

or,

A processor core with the largest first remaining computing power value among target class processor cores within the first processor core selection range is determined as a target processor core, wherein the target class processor core is a class of processor cores with the strongest processing capability within the first processor core selection range.

In one implementation, the processor core with the largest first remaining computing power value within the first processor core selection range is determined as the target processor core, which can ensure that the first task can be processed as quickly as possible, thereby improving the timeliness of the first task processing.

In another embodiment, selecting a processor core with the largest first residual computing power value from a class of processor cores with the strongest processing capabilities can ensure that the first task is processed by the processor core with the strongest processing capabilities. This can not only improve the processing speed of the first task, but also improve the fluency of the first task.

The processor core of the type with the strongest processing capability in the first processor core selection range may be, for example, a processor core of the type with the largest total computing power value in the first processor core selection range.

Optionally, selecting a target processor core from N processor cores according to the second parameter information of the first task includes:

When the first task satisfies the first condition, selecting a target processor core from the N processor cores according to the second parameter information of the first task;

The first condition includes any one of the following: the task type is a foreground task, the task importance level is greater than a preset level, and the scheduling priority is greater than a preset priority.

The above preset levels and preset priorities can be reasonably set according to actual needs, and this embodiment does not limit this.

Specifically, the processor core selection method provided in the embodiment of the present application can be used to select a processor core for the first task only when the first task meets the first condition. For example, the first computing power value of each of the N processor cores is calculated according to the scheduling priority of the first task, wherein the first computing power value is the sum of the computing power values required for the load of all tasks in the processor core whose scheduling priority is higher than or equal to the scheduling priority of the first task, and the first remaining computing power value of each processor core in the N processor cores is determined according to the first computing power value of each processor core in the N processor cores and the total computing power value, and the processor core used to execute the first task is determined according to the computing power requirement information of the first task and the first remaining computing power value of each processor core in the N processor cores.

When the first task does not meet the first condition, the existing processor core selection method can be used. For example, the load computing power value corresponding to each processor core in the above-mentioned N processor cores is calculated separately. The load computing power value is the sum of the computing power values required for all loads in the processor core, and the processor core with the smallest load computing power value can be selected as the processor core for executing the above-mentioned first task.

In this embodiment, when the first condition is met, the target processor core is selected from N processor cores according to the second parameter information of the first task. This can not only ensure the processing effect of foreground tasks or some more important tasks, such as processing efficiency and fluency, but also reduce the complexity of processor core selection for tasks that do not meet the first condition (for example, background tasks or some less important tasks, etc.), thereby reducing system resource overhead.

Optionally, the first parameter information includes the task type, and the task type includes a foreground task or a background task;

The determining the scheduling priority of the first task according to the first parameter information of the first task includes:

In a case where the task type of the first task is a foreground task, determining the scheduling priority of the first task to be a first scheduling priority;

When the task type of the first task is a background task, determining the scheduling priority of the first task to be a second scheduling priority;

The first scheduling priority is higher than the second scheduling priority.

Exemplarily, a task can be distinguished as a foreground task or an acquired task based on whether there is a visible interface for the task, whether there are foreground services and services that the foreground depends on are being executed, whether there is a broadcast being executed, whether there is a database that the foreground depends on is being executed, etc. For example, if a task has no visible interface, no foreground services and services that the foreground depends on are being executed, no broadcast being executed, and no database that the foreground depends on is being executed, then the task is determined to be a background task; otherwise, the task is determined to be a foreground task.

In this embodiment, the scheduling priority of the foreground task is higher than the scheduling priority of the background task, which can ensure that the foreground task can be scheduled before the background task, thereby reducing the jamming of the foreground task and improving the fluency of the foreground task.

The embodiment of the present application is described below with reference to FIG3 .

Step 201: scene recognition.

In this embodiment, the scene recognition module can be used to identify the scenes of multiple foreground applications, and the highest scheduling priority is set for the foreground process (i.e., task). Otherwise, under unfair scheduling, low-priority foreground applications are easily affected by high-priority foreground applications, which can easily cause lag.

For example, application A switches to the foreground, triggering a scene change notification to the scene recognition module, and application B switches to the foreground, triggering a scene change notification to the scene recognition module.

Step 202, determine whether there are multiple foreground applications.

For example, the scene recognition module determines the foreground processes of application A and application B. If both application A and application B are foreground applications, then it belongs to a multi-foreground application scene. In this step, if there are multiple foreground applications, step 203 can be executed.

Step 203, calculate the computing power value required by each foreground application (ie, the computing power requirement information mentioned above).

For example, the CPU computing power requirement of each foreground process (i.e., task) can be evaluated according to the type of foreground process (i.e., task) to allocate CPU resources. For example, the usage scenario (e.g., playing games, listening to music, sliding small windows, etc.) can be identified according to information such as the application package name, whether it is visible, whether it has focus, the audio status, and whether the input operation is frequent, and the computing power requirement of the application process can be determined.

For example, game processes that require high computing power can be run on large and medium processor cores first. Foreground processes that require slightly lower computing power (such as small window application processes) can be run on other medium or small processor cores. This can reduce the additional system overhead caused by frequent migration of different foreground processes running on the same processor core.

It should be noted that the scheduling system can only manage the scheduling of processes without caring about the type of application, computing power requirements and other information. Therefore, the above process can be completed through the above-mentioned scene recognition module.

Step 204: If the scene recognition module determines that application A has a high demand for CPU computing power, the processor core selection range of application A (such as a game application) can be determined to be CPU-0 to CPU-7.

For example, CPU-7 is a large processor core, CPU-4 to CPU-6 are all medium processor cores, and CPU-0 to CPU-3 are all small processor cores, wherein the processing capability of the large processor core is stronger than that of the medium processor core, and the processing capability of the medium processor core is stronger than that of the small processor core.

It should be noted that the computing power required for each application process can be determined in advance through experimental simulation. For example, each application process can be tested through experimental simulation to see how much computing power is required to avoid frame drops and sound jams, etc., and then the range of processor core selection corresponding to each application process can be determined.

Step 205: Select processor cores through unfair scheduling, and give priority to selecting processor cores CPU-7 and CPU-6 for application A.

Because application A is a process with high scheduling priority, there is no restriction on the CPU cores on which it can run, and it can run on CPU-7 and CPU-6. According to the unfair scheduling load core selection logic, it will be scheduled to CPU-7 and CPU-6 first, because CPU-7 and CPU-6 have strong computing power and there is no other process with high scheduling priority running, so there is a lot of remaining capacity.

For example, when application A is a foreground process and has a high demand for CPU computing power, application A can be preferentially scheduled to large processor cores and medium processor cores through unfair scheduling. For example, if application A is identified as a game application (such as determined as a game application based on the application package name) and is in the foreground (for example, it is known that it is in a battle scene based on the game's software development kit (sdk)), the scheduling priority of application A can be set to the highest scheduling priority, for example, set its scheduling priority to 3, which is the highest scheduling priority, and prioritize application A to CPU-7 and CPU-6.

Step 206: If the scene recognition module determines that application B has a lower demand for CPU computing power, the processor core selection range of application B (such as a small window application) can be determined to be CPU-0 to CPU-5.

Step 207: Select processor cores through unfair scheduling, and give priority to selecting processor cores CPU-5 and CPU-4 for application B.

Because application B can only run on CPU-0 to CPU-5, it will be scheduled to CPU-5 and CPU-4 first according to the unfair scheduling load core selection logic. Because application B is selected from CPU-0 to CPU-5, CPU-5 and CPU-4 have strong processing capabilities and more surplus computing capacity, so it is easier to run on CPU-5 and CPU-4, and there are not many application processes with high scheduling priority running on CPU-5 and CPU-4.

As can be seen from the above, in the example, application B (such as a video window application) occupies CPU-4 to CPU-5 at most, and can avoid competing with application A (such as a game application) for CPU-6 and CPU-7. In this way, both application A and application B have the highest scheduling priority. In the case of priority, the highest priority is guaranteed for scheduling on each processor core, which can ensure the smoothness of each application.

It should be noted that in the unfair scheduling processor core selection method of this example, the processor core selected by the process with high scheduling priority will ignore the load of the low scheduling priority process on each processor core, and calculate the remaining computing power value on each processor core (that is, the first remaining computing power value mentioned above), and then select the processor core with the largest remaining computing power value. For example, when selecting a processor core for application process A with a scheduling priority of 3, since CPU-7 to CPU-0 can be selected, when calculating the remaining computing power value of CPU-7, the load of processes greater than or equal to 3 in the task queue on CPU-7 will be calculated, and the load of processes less than 3 will not be calculated (because the load of processes with priority 2 and priority 1 will not affect the process with priority 3, where the scheduling priority order is: 3 is higher than 2, and 2 is higher than 1).

It should also be noted that, for background tasks, their scheduling priority can be set to a low scheduling priority for unfair scheduling, for example, their scheduling priority can be set to 0.

The task processing method provided in the embodiment of the present application can be executed by a task processing device. In the embodiment of the present application, the task processing device provided in the embodiment of the present application is described by taking the task processing method executed by the task processing device as an example.

Referring to FIG. 4 , FIG. 4 is a schematic diagram of the structure of a task processing device provided in an embodiment of the present application. As shown in FIG. 4 , the task processing device 400 includes:

A first determination module 401 is used to determine the scheduling priority of the first task according to first parameter information of the first task, wherein the first parameter information includes at least one of a task type and a task importance level;

A first selection module 402, configured to select a target processor core from N processor cores according to second parameter information of the first task, wherein the second parameter information includes computing power requirement information and scheduling priority, and N is an integer greater than 1;

The execution module 403 is configured to execute the first task on the target processor core according to the scheduling priority of the first task.

Optionally, the second parameter information includes computing power requirement information and scheduling priority;

The first selection module comprises:

a calculation unit, configured to calculate a first remaining computing power value of each of the N processor cores according to the scheduling priority of the first task, the first remaining computing power value of the processor core being a difference between a total computing power value of the processor core and a first computing power value, the first computing power value being a sum of computing power values required for a load of all tasks in the processor core whose scheduling priority is higher than or equal to the scheduling priority of the first task;

A determination unit is used to determine a target processor core according to the computing power requirement information of the first task and a first remaining computing power value of each processor core in the N processor cores.

Optionally, the determining unit is specifically configured to:

Determining a first processor core selection range according to the computing power requirement information of the first task, wherein the N processor cores include at least two types of processor cores, different types of processor cores in the at least two types of processor cores have different processing capabilities, and the first processor core selection range includes at least two processor cores in the N processor cores;

The target processor core is determined according to the first remaining computing power values of the processor cores within the first processor core selection range.

Optionally, the determining unit is specifically configured to:

Determine the processor core with the largest first remaining computing power value within the first processor core selection range as the target processor core;

or,

A processor core with the largest first remaining computing power value among target class processor cores within the first processor core selection range is determined as a target processor core, wherein the target class processor core is a class of processor cores with the strongest processing capability within the first processor core selection range.

Optionally, the first selection module is specifically used to:

When the first task satisfies the first condition, selecting a target processor core from the N processor cores according to the second parameter information of the first task;

The first condition includes any one of the following: the task type is a foreground task, the task importance level is greater than a preset level, and the scheduling priority is greater than a preset priority.

Optionally, the first parameter information includes the task type, and the task type includes a foreground task or a background task;

The first determining module is specifically used for:

In a case where the task type of the first task is a foreground task, determining the scheduling priority of the first task to be a first scheduling priority;

When the task type of the first task is a background task, determining the scheduling priority of the first task to be a second scheduling priority;

The first scheduling priority is higher than the second scheduling priority.

The task processing device in the embodiment of the present application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR)/virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc. It can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., and the embodiment of the present application is not specifically limited.

The task processing device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

The task processing device provided in the embodiment of the present application can implement each process implemented in the above method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described here.

Optionally, as shown in Figure 5, an embodiment of the present application also provides an electronic device 500, including a processor 501 and a memory 502, and the memory 502 stores a program or instruction that can be executed on the processor 501. When the program or instruction is executed by the processor 501, the various steps of the above-mentioned task processing method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

It should be noted that the electronic devices in the embodiments of the present application include mobile electronic devices and non-mobile electronic devices.

FIG. 6 is a schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.

The electronic device 600 includes but is not limited to: a radio frequency unit 601, a network module 602, an audio output unit 603, an input unit 604, a sensor 605, a display unit 606, a user input unit 607, an interface unit 608, a memory 609, and a processor 610.

Those skilled in the art will appreciate that the electronic device 600 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 610 through a power management system, so that the power management system can manage charging, discharging, and power consumption. The electronic device structure shown in FIG6 does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown, or combine certain components, or arrange components differently, which will not be described in detail here.

The processor 610 is configured to determine a scheduling priority of the first task according to first parameter information of the first task, wherein the first parameter information includes at least one of a task type and a task importance level;

The processor 610 is further configured to select a target processor core from N processor cores according to second parameter information of the first task, wherein the second parameter information includes computing power requirement information and scheduling priority, and N is an integer greater than 1;

The processor 610 is further configured to execute the first task on the target processor core according to the scheduling priority of the first task.

Optionally, the second parameter information includes computing power requirement information and scheduling priority;

The processor 610 is specifically configured to:

Calculate a first remaining computing power value of each processor core in the N processor cores according to the scheduling priority of the first task, the first computing power value being the sum of computing power values required for the load of all tasks in the processor core whose scheduling priority is higher than or equal to the scheduling priority of the first task;

A target processor core is determined according to the computing power requirement information of the first task and a first remaining computing power value of each processor core of the N processor cores.

Optionally, the processor 610 is specifically configured to:

Determining a first processor core selection range according to the computing power requirement information of the first task, wherein the N processor cores include at least two types of processor cores, different types of processor cores in the at least two types of processor cores have different processing capabilities, and the first processor core selection range includes at least two processor cores in the N processor cores;

The target processor core is determined according to the first remaining computing power values of the processor cores within the first processor core selection range.

Optionally, the processor 610 is specifically configured to:

Determine the processor core with the largest first remaining computing power value within the first processor core selection range as the target processor core;

or,

A processor core with the largest first remaining computing power value among target class processor cores within the first processor core selection range is determined as a target processor core, wherein the target class processor core is a class of processor cores with the strongest processing capability within the first processor core selection range.

Optionally, the processor 610 is specifically configured to:

When the first task satisfies the first condition, selecting a target processor core from the N processor cores according to the second parameter information of the first task;

The first condition includes any one of the following: the task type is a foreground task, the task importance level is greater than a preset level, and the scheduling priority is greater than a preset priority.

Optionally, the first parameter information includes the task type, and the task type includes a foreground task or a background task;

The processor 610 is specifically configured to:

In a case where the task type of the first task is a foreground task, determining the scheduling priority of the first task to be a first scheduling priority;

When the task type of the first task is a background task, determining the scheduling priority of the first task to be a second scheduling priority;

The first scheduling priority is higher than the second scheduling priority.

It should be understood that in the embodiment of the present application, the input unit 604 may include a graphics processing unit (GPU) 6041 and a microphone 6042, and the graphics processor 6041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 606 may include a display panel 6061, and the display panel 6061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 607 includes a touch panel 6071 and at least one of other input devices 6072. The touch panel 6071 is also called a touch screen. The touch panel 6071 may include two parts: a touch detection device and a touch controller. Other input devices 6072 may include, but are not limited to, a physical keyboard, function keys (such as a volume control key, a switch key, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

The memory 609 can be used to store software programs and various data. The memory 609 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 609 may include a volatile memory or a non-volatile memory, or the memory 609 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory The memory 609 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

The processor 610 may include one or more processing units; optionally, the processor 610 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 610.

An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the above-mentioned task processing method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned task processing method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned task processing method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

Through the above description of the implementation methods, those skilled in the art can clearly understand that the above embodiment methods can be implemented by means of software plus a necessary general hardware platform, or by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application essentially or in other words contributes to the prior art. The disclosed part may be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present application.

The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims (17)

A task processing method, the method comprising: Determining a scheduling priority of the first task according to first parameter information of the first task, wherein the first parameter information includes at least one of a task type and a task importance level; Selecting a target processor core from N processor cores according to second parameter information of the first task, wherein the second parameter information includes computing power requirement information and scheduling priority, and N is an integer greater than 1; The first task is executed on the target processor core according to the scheduling priority of the first task. The method according to claim 1, wherein the selecting a target processor core from N processor cores according to the second parameter information of the first task comprises: Calculate a first remaining computing power value of each processor core of the N processor cores according to the scheduling priority of the first task, the first remaining computing power value of the processor core is the difference between the total computing power value of the processor core and the first computing power value, and the first computing power value is the sum of the computing power values required for the load of all tasks in the processor core whose scheduling priority is higher than or equal to the scheduling priority of the first task; A target processor core is determined according to the computing power requirement information of the first task and a first remaining computing power value of each processor core of the N processor cores. The method according to claim 2, wherein the determining the target processor core according to the computing power requirement information of the first task and the first remaining computing power value of each processor core of the N processor cores comprises: Determining a first processor core selection range according to the computing power requirement information of the first task, wherein the N processor cores include at least two types of processor cores, different types of processor cores in the at least two types of processor cores have different processing capabilities, and the first processor core selection range includes at least two processor cores in the N processor cores; The target processor core is determined according to the first remaining computing power values of the processor cores within the first processor core selection range. The method according to claim 3, wherein determining the target processor core according to the first remaining computing power value of each processor core within the first processor core selection range comprises: Determine the processor core with the largest first remaining computing power value within the first processor core selection range as the target processor core; or, A processor core with the largest first remaining computing power value among target class processor cores within the first processor core selection range is determined as a target processor core, wherein the target class processor core is a class of processor cores with the strongest processing capability within the first processor core selection range. The method according to any one of claims 1 to 4, wherein the selecting a target processor core from N processor cores according to the second parameter information of the first task comprises: When the first task satisfies the first condition, selecting a target processor core from the N processor cores according to the second parameter information of the first task; The first condition includes any one of the following: the task type is a foreground task, the task importance level is greater than a preset level, and the scheduling priority is greater than a preset priority. The method according to any one of claims 1 to 4, wherein the first parameter information includes the task type, and the task type includes a foreground task or a background task; The determining the scheduling priority of the first task according to the first parameter information of the first task includes: In a case where the task type of the first task is a foreground task, determining the scheduling priority of the first task to be a first scheduling priority; When the task type of the first task is a background task, determining the scheduling priority of the first task to be a second scheduling priority; The first scheduling priority is higher than the second scheduling priority. A task processing device, comprising: A first determination module, configured to determine a scheduling priority of the first task according to first parameter information of the first task, wherein the first parameter information includes at least one of a task type and a task importance level; A first selection module, configured to select a target processor core from N processor cores according to second parameter information of the first task, wherein the second parameter information includes computing power requirement information and scheduling priority, and N is an integer greater than 1; An execution module is used to execute the first task on the target processor core according to the scheduling priority of the first task. The apparatus according to claim 7, wherein the first selection module comprises: a calculation unit, configured to calculate a first remaining computing power value of each of the N processor cores according to the scheduling priority of the first task, the first remaining computing power value of the processor core being a difference between a total computing power value of the processor core and a first computing power value, the first computing power value being a sum of computing power values required for a load of all tasks in the processor core whose scheduling priority is higher than or equal to the scheduling priority of the first task; A determination unit is used to determine a target processor core according to the computing power requirement information of the first task and a first remaining computing power value of each processor core in the N processor cores. The apparatus according to claim 8, wherein the determining unit is specifically configured to: Determining a first processor core selection range according to the computing power requirement information of the first task, wherein the N processor cores include at least two types of processor cores, different types of processor cores in the at least two types of processor cores have different processing capabilities, and the first processor core selection range includes at least two processor cores in the N processor cores; The target processor core is determined according to the first remaining computing power values of the processor cores within the first processor core selection range. The apparatus according to claim 9, wherein the determining unit is specifically configured to: Determine the processor core with the largest first remaining computing power value within the first processor core selection range as the target processor core; or, A processor core with the largest first remaining computing power value among target class processor cores within the first processor core selection range is determined as a target processor core, wherein the target class processor core is a class of processor cores with the strongest processing capability within the first processor core selection range. The device according to any one of claims 7 to 10, wherein the first selection module is specifically configured to: When the first task satisfies the first condition, selecting a target processor core from the N processor cores according to the second parameter information of the first task; The first condition includes any one of the following: the task type is a foreground task, the task importance level is greater than a preset level, and the scheduling priority is greater than a preset priority. The device according to any one of claims 7 to 10, wherein the first parameter information includes the task type, and the task type includes a foreground task or a background task; The first determining module is specifically used for: In a case where the task type of the first task is a foreground task, determining the scheduling priority of the first task to be a first scheduling priority; When the task type of the first task is a background task, determining the scheduling priority of the first task to be a second scheduling priority; The first scheduling priority is higher than the second scheduling priority. An electronic device comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the task processing method as described in any one of claims 1 to 6 are implemented. A readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the task processing method according to any one of claims 1 to 6 are implemented. A chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the steps of the task processing method according to any one of claims 1 to 6. A computer program product, wherein the computer program product is executed by at least one processor to implement the steps of the task processing method according to any one of claims 1 to 6. An electronic device, wherein the electronic device is configured to execute the steps of the task processing method as described in any one of claims 1 to 6.