CN119156001A - Memory preparation method, memory, device and equipment - Google Patents
Memory preparation method, memory, device and equipment Download PDFInfo
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- CN119156001A CN119156001A CN202411136041.3A CN202411136041A CN119156001A CN 119156001 A CN119156001 A CN 119156001A CN 202411136041 A CN202411136041 A CN 202411136041A CN 119156001 A CN119156001 A CN 119156001A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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Abstract
The application provides a preparation method of a memory, the memory, a device and equipment, wherein the method comprises the steps of forming a first semiconductor structure and a first active structure which are stacked in sequence on a substrate, wherein the doping concentration of the first semiconductor structure is the same as that of a second active structure; ion implantation is performed on the first semiconductor structure in a region close to the first active structure to form a BL structure between the first semiconductor structure and the first active structure, the first semiconductor structure, the BL structure and the first active structure are self-aligned in the BL region, a first memory is formed based on the first active structure, the first memory is reworked and a substrate is removed to expose the first semiconductor structure, the first semiconductor structure is etched in the BL region to form a second active structure, a second memory is formed based on the second active structure, and the BL structure is shared by the first source drain structure of the first memory and the second source drain structure of the second memory. The application can improve the integration level of the memory.
Description
Technical Field
The present application relates to the field of integrated semiconductors, and in particular, to a method for manufacturing a memory, a device, and an apparatus.
Background
Dynamic random access memory (dynamic random access memory, DRAM) typically employs a structure of a transistor and a capacitor (1T 1C) as the memory cells of the chip. With the continued evolution of architecture, the area of DRAM memory cells is 4F 2 (F is the feature size). However, as moore's law continues, the area scaling of conventional DRAMs encounters bottlenecks. There is a need for a method that can reduce the area of DRAM memory cells and increase the memory density.
Disclosure of Invention
The application provides a preparation method of a memory, the memory, a device and equipment, which can reduce the area of a storage unit of the memory and improve the storage density and the integration level.
In a first aspect, an embodiment of the application provides a method for manufacturing a memory, the method comprises the steps of forming a stacked structure on a substrate, wherein the stacked structure comprises a first semiconductor structure and a first active structure which are sequentially stacked in a first direction, the doping concentration of the first semiconductor structure is the same as that of the first active structure, ion implantation is conducted on the first semiconductor structure in a region close to the first active structure to form a bit line BL structure, the BL structure is located between the first semiconductor structure and the first active structure, the first semiconductor structure, the BL structure and the first active structure are self-aligned in the BL region along the first direction, a first memory is formed based on the first active structure, the first memory is reworked and the substrate is removed to expose the first semiconductor structure, the first semiconductor structure is etched in the BL region to form a second active structure, and a second memory is formed based on the second active structure, wherein the BL structure is shared by a first source drain structure in the first memory and a second source drain structure in the first memory.
In one possible embodiment, forming a stacked structure on a substrate includes sequentially stacking a first material layer and a second material layer on the substrate along a first direction, etching the first material layer and the second material layer along a BL direction to form a first semiconductor structure and a second semiconductor structure, and etching the second semiconductor structure along a WL direction to form a first active structure.
In one possible embodiment, ion implantation is performed on the first semiconductor structure in a region adjacent to the first active structure to form a bit line BL structure, including ion implantation is performed on the first semiconductor structure in the BL region in a region adjacent to the first active structure to form a third semiconductor structure in the BL region, and annealing is performed on the third semiconductor to form the BL structure.
In one possible implementation, forming the first memory based on the first active structure includes forming a first transistor based on the first active structure, forming a first capacitance structure on the first transistor, forming the second memory based on the second active structure includes forming a second transistor based on the second active structure, and forming a second capacitance structure on the second transistor.
In one possible embodiment, forming the first transistor based on the first active structure comprises forming a first gate structure based on the first active structure, removing the first gate structure in the BL region to form a first groove, depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of a first mask, the first mask is positioned on the first active structure, removing the first mask to form a second groove, and forming a first source drain structure in the second groove.
In one possible embodiment, the first gate structure comprises a first gate electrode layer and a first gate dielectric layer surrounding the first gate electrode layer, wherein the first gate electrode layer is lower than the first gate dielectric layer in height, the first gate structure is removed in the BL region to form a first groove, the first groove comprises the steps of forming a sacrificial layer on the first gate electrode layer in the BL region, the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer, and the bottom of the sacrificial layer and the first gate electrode layer below the sacrificial layer are anisotropically etched to form the first groove.
In one possible implementation, forming a first capacitance structure over a first transistor includes forming a first dielectric layer over a first source-drain structure, etching a first portion of the first dielectric layer to expose the first source-drain structure, and forming the first capacitance structure over the first source-drain structure.
In one possible embodiment, forming the second transistor based on the second active structure comprises forming a second gate structure based on the second active structure, removing the second gate structure in the BL region to form a third groove, depositing an insulating material on the second gate structure in the WL region and in the third groove to form a second insulating layer, wherein the upper surface of the second insulating layer is flush with the upper surface of a second mask, the second mask is positioned on the second active structure, removing the second mask to form a fourth groove, and forming a second source drain structure in the fourth groove.
In a second aspect, an embodiment of the present application provides a memory, where the memory is made by using the preparation method described in the first aspect and any embodiment of the first aspect, and the memory includes a BL structure, a first memory, and a second memory, where the second memory is disposed opposite to the first memory, and a first source drain structure in the second memory and a second source drain structure in the first memory share the BL structure.
In a third aspect, an embodiment of the present application provides a semiconductor device including a memory as described in the second aspect above.
In a fourth aspect, an embodiment of the present application provides an electronic device, including a circuit board and a semiconductor device as described in the third aspect, where the semiconductor device is disposed on the circuit board.
In the present application, a first memory (front memory) is prepared by forming a first semiconductor structure and a first active structure on a substrate, then performing ion implantation in a region on the first semiconductor adjacent to the first active structure to form a BL structure located between the first semiconductor structure and the first active structure, the first semiconductor structure, the BL structure and a second active structure being self-aligned in the BL region, then preparing the first memory (front memory) based on the front active structure (first active structure), rewinding the front memory and removing the substrate to expose the first semiconductor structure, then etching the first semiconductor structure in the BL region to form a second active structure, and finally preparing a second memory (back memory) based on the second active structure. The application ensures the self alignment of the front and back BL through BL area integrated molding. Through wafer bonding and rewinding, two storage units with the size of 4F 2 are integrated on the front side and the back side, so that the equivalent area of the memory is 2F 2, the area of the storage unit of the memory is reduced, and the storage density and the integration level of the memory are improved. In addition, the BL structure is formed by the ion implantation method, the steps are simple, and the cost can be saved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic flow chart of an embodiment of a method for manufacturing a memory according to the present application;
FIG. 2 is a schematic top view of a memory according to an embodiment of the application;
FIGS. 3 to 24 are schematic views of structures of a memory during a manufacturing process according to embodiments of the present application;
fig. 25 is a schematic diagram of a memory according to an embodiment of the application.
The figures above:
10. Memory, 11, first transistor (front side transistor), 111, first active structure, 112, first source drain structure, 113, first gate structure, 1131, first gate dielectric layer, 1132, first gate electrode layer, 12, second transistor, 121, second active structure, 122, second source drain structure, 123, second gate structure, 1231, second gate dielectric layer, 1232, second gate electrode layer, 13, third insulating layer, 14, carrier wafer, 20, substrate, 21, first material layer, 22, second material layer, 23, first mask, 24, active structure, 241, first semiconductor structure, 242, second semiconductor structure, 25, first shallow trench isolation structure, 26, third mask, 27, third semiconductor structure, 28, BL structure, 29, second shallow trench isolation structure, 30, 31, sacrificial layer, 32, first recess, 33, first oxide layer, 34, second insulating layer, 35, second recess, 36, first capacitor layer, 37, second capacitor layer, 40, second capacitor dielectric layer, 42, second capacitor dielectric layer, 43, second capacitor dielectric layer, 42, first capacitor dielectric layer, 42, second capacitor layer, 42, active structure and third capacitor dielectric layer.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.
While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits. With the continuous development of transistor technology, a flip-chip stacked transistor has been developed, in which active regions of upper and lower homologous transistors are formed by etching, and the flip-chip stacked transistor is fabricated on the front and back sides of a wafer by chamfering, so that the disadvantages of the conventional schemes can be overcome.
In a DRAM, ferroelectric random access memory (ferroelectric random access memory, feRAM), or other memory, the memory cells may include transistor and capacitor structures. The transistor is arranged on the substrate, the capacitor structure is positioned at one end of the transistor far away from the substrate, and the transistor is electrically connected with the capacitor structure.
Taking DRAM as an example, the basic composition of DRAM is 1T1C. At present, the DRAM mainly has three forms, wherein the area of the first DRAM is 8F 2, the first DRAM is realized by horizontally placing a transistor and a capacitor structure, the area of the second DRAM is 6F 2, the arrangement density can be increased by inclining the placement positions of the transistor and the capacitor structure, so that the smaller integrated area is realized, the area of the third DRAM is 4F 2, and the volume in the vertical direction is fully utilized by vertically placing the transistor and the capacitor structure, so that the smaller area of the DRAM is scaled.
At the moment of further shrinking the size of integrated circuits, there is a need for a method that can reduce the area of memory cells of a memory and increase the memory density.
Based on the above, the embodiment of the application provides a preparation method of a memory, which can reduce the area of a memory unit of the memory and improve the memory density and the integration level.
In some embodiments, the memory may include a plurality of memory cells, each of which may include a flip-chip stacked transistor and a capacitive structure (capacitor), wherein the capacitive structure is electrically connected to the flip-chip stacked transistor.
In some embodiments, the flip-chip stacked transistor may include a gate structure, a source structure, and a drain structure, and the capacitor structure may be electrically connected to the source structure of the flip-chip stacked transistor and the capacitor structure, or the drain structure of the flip-chip stacked transistor may be electrically connected to the capacitor structure, and the flip-chip stacked transistor controls writing, changing, or reading information in the capacitor structure. I.e., flip-chip stacked transistors, as select devices (or switching devices) may control writing, modifying, or reading of information in the capacitive structure.
In some embodiments, a capacitive structure may include a first electrode and a second electrode, and a capacitive dielectric layer between the first electrode and the second electrode. Illustratively, the first electrode may be electrically connected to the drain structure of the flip-chip stacked transistor and the second electrode may be grounded.
In some embodiments, a plurality of Word Line (WL) structures and a plurality of Bit Line (BL) structures may be further included in the memory cell, wherein the WL structures may be connected to the gate structures of the flip-chip stacked transistors, thereby controlling the turn-on and turn-off of the flip-chip stacked transistors. The BL structure may be connected to a source structure or a drain structure of the flip-chip stacked transistor, thereby writing data into a capacitance structure connected to the flip-chip stacked transistor when the flip-chip stacked transistor is turned on.
In some embodiments, the flip-chip stacked transistor may include at least two transistors, for example, a first transistor and a second transistor, where the first transistor and the second transistor are disposed opposite to each other, and the second active structure of the first transistor and the first active structure of the second transistor are formed through the same process, so it may be understood that the first transistor and the second transistor share the active structure.
In the embodiment of the present application, the first transistor and the second transistor in the flip-chip stacked transistor are transistors of the same type, such as a vertical channel transistor (VERTICAL CHANNEL transistor, VCT), which may also be referred to as a vertical gate-all transistor.
Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a memory according to an embodiment of the present application, as shown in fig. 1, the method for manufacturing a memory according to an embodiment of the present application may include:
And S110, forming a stacked structure on the substrate.
The stacked structure comprises a first semiconductor structure and a second active structure which are sequentially stacked in a first direction, wherein the first semiconductor structure and the second active structure are self-aligned in the WL region along the first direction. The first direction is the growth direction of the substrate, i.e. the direction of growth from the bottom upwards.
In some embodiments, the implementation process of the step S110 may be divided into a first step of sequentially stacking a first material layer and a second material layer on a substrate along a first direction, a second step of etching the first material layer and the second material layer in a WL area to form a first semiconductor structure and a second semiconductor structure, and a third step of etching the second semiconductor structure in a BL area to form a first active structure.
In step one, the first material layer is doped the same as the second material layer.
The substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or the like.
It will be appreciated that the first material layer is doped the same as the second material layer, so that the same doped first material layer and second material layer can be etched later as an active structure common to the front side transistor (first transistor) and the back side transistor (second transistor) in a flip-chip stacked transistor.
Since the memory cell of the memory includes the WL region and the BL region, after the first material layer and the second material layer are sequentially stacked on the substrate, the WL region and the BL region may be etched to form the active structure. First, the first material layer and the second material layer may be etched in the WL region based on the step two to form a first semiconductor structure and a second semiconductor structure.
In some embodiments, the second step may be implemented by forming a first mask on the second material layer, the first mask being used to locate the WL region, and etching the first material layer and the second material layer based on the first mask to form the first semiconductor structure and the second semiconductor structure. That is, after forming a mask by photolithography, etching is performed in the BL direction to form the first semiconductor structure and the second semiconductor structure.
It will be appreciated that a first mask may be formed over the second material layer first, the first mask being used to locate the WL region, whereby the first mask covers a portion of the second material layer in the WL region and the entire second material layer in the BL region, such that the second material layer and the first material layer are etched based on the first mask, and the second semiconductor structure and the first semiconductor structure may be formed. Wherein the second semiconductor structure comprises a first active structure in the WL area and a second material layer in the BL area. The first semiconductor structure includes a second active structure in the WL area and a first material layer in the BL area.
Illustratively, the etching process may be at least one of dry etching, wet etching, reactive ion etching, and the like.
After forming the first semiconductor structure and the second semiconductor structure, the second semiconductor structure may be etched in the BL region based on step three to form the first active structure. That is, etching is performed in the BL direction, and etching is stopped on the first material layer to form the first active structure.
In some embodiments, the implementation of the third step may be that a third mask is formed on the first mask, the third mask being used for the BL region, and the first mask and the second semiconductor structure are etched based on the third mask to form the first active structure.
It will be appreciated that the BL region may be located through a third mask formed over the first mask, the third mask covering a portion of the first mask over the BL region and the WL region over the entire first mask, such that when etched down based on the third mask, the second material layer in the BL region may be etched to form the first active structure. When etching downwards based on the third mask, the first material layer can be used as an etching stop layer, namely, based on the third mask, the first mask and the second semiconductor structure are etched downwards, so that a first active structure is formed, and the structure in the WL region is not affected.
In some embodiments, after etching the WL region to form the first semiconductor structure and the second semiconductor structure, an oxide material may be deposited on the substrate to form a first shallow trench isolation (shallow trench isolation, STI) structure.
It is appreciated that an oxide material may be deposited on the substrate and thinned such that the upper surface of the shallow trench isolation structure formed is flush with the upper surface of the first mask. The oxide material forming the shallow trench isolation structure may be, for example, any of silicon nitride (SiN, si3N 4), silicon dioxide (SiO 2), silicon oxycarbide (SiCO), or the like. The thinning process may be, for example, a chemical-mechanical planarization (CMP) process or the like.
In step S120, ion implantation is performed on the first semiconductor structure in a region close to the first active structure to form a BL structure.
The BL structure is located between the first semiconductor structure and the first active structure, the first semiconductor structure, the BL structure and the first active structure are self-aligned along a first direction in the BL area, and the doping concentration of the BL structure is different from that of the first semiconductor structure.
In some embodiments, the implementation of step S120 may be that ion implantation is performed on a region of the first semiconductor structure in the BL region, which is close to the first active structure, to form a third semiconductor structure in the BL region, and annealing is performed on the third semiconductor structure to form the BL structure.
It will be appreciated that the third mask formed above covers the entire first mask in the WL region, i.e. the third mask covers the entire WL region, and thus ion implantation may be performed on the region of the first semiconductor structure in the BL region close to the first active structure based on the third mask formed above to form the third semiconductor structure. And then annealing the third semiconductor structure, wherein ions are diffused and moved into the active structure which is positioned in the same horizontal direction as the third semiconductor structure due to the temperature rise during annealing, so that a BL structure is formed, wherein the BL structure is discontinuous in a WL region and continuous in the BL region.
In some embodiments, the doping concentration of the third semiconductor may be higher than the doping concentration of the first semiconductor structure, which may form a BL structure with a higher doping concentration. The BL structure is used as a data transmission channel, the doping concentration of the BL structure mainly influences the data transmission efficiency and the noise performance, and the higher doping concentration can improve the conductivity of the BL structure and reduce the resistance, so that the data transmission speed is increased.
In some implementations, the third mask may be removed after the BL structure is formed.
In some embodiments, after forming the BL active structure, an oxide material may be deposited on the BL structure to form a second shallow trench isolation structure.
It is understood that after the first shallow trench isolation structure and the second shallow trench isolation structure are formed, the first shallow trench isolation structure and the second shallow trench isolation structure may be thinned to a predetermined height to expose the gate region of the front side transistor for subsequent fabrication of the gate structure of the front side transistor.
Step S130, forming a first memory based on the first active structure.
In some embodiments, the implementation of step S130 may include two steps, forming a first transistor based on the first active structure, and forming a first capacitance structure on the first transistor.
In some embodiments, forming the first transistor based on the first active structure may be performed by forming a first gate structure based on the first active structure, removing the first gate structure in the BL region to form a first recess, depositing an insulating material on the first gate structure in the WL region and in the first recess to form a first insulating layer, an upper surface of the first insulating layer being flush with an upper surface of the first mask, removing the first mask to form a second recess, and forming a first source drain structure in the second recess.
It will be appreciated that after the first shallow trench isolation structure and the second shallow trench isolation structure are thinned to a predetermined height, the gate region of the front side transistor is exposed, i.e., a first gate recess is formed between the first active structures, such that an insulating material may be deposited at the first gate recess to form a first gate dielectric layer, and a metal material may be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate electrode layer and the first gate dielectric layer surrounding the first gate electrode layer together form a first gate structure. The height of the first gate dielectric layer may be higher than the height of the first gate electrode layer.
For example, the first gate dielectric layer may be composed of a silicon oxide layer and a high K hafnium oxide layer, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.
By way of example, the first gate electrode layer may be composed of multiple layers of electrode materials, each layer of electrode material including, but not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals.
Since the WL structure in the WL region is connected to the gate structure of the transistor, the first gate structure in the WL region is necessary, and the first gate structure in the BL region may not exist, and thus the first gate structure in the BL region may be selectively removed.
In some embodiments, removing the first gate structure in the BL region and forming the first recess may be performed by forming a sacrificial layer on the first gate electrode layer in the BL region, wherein an upper surface of the sacrificial layer is flush with an upper surface of the first gate dielectric layer, and anisotropically etching a bottom of the sacrificial layer and the first gate electrode layer under the sacrificial layer to form the first recess.
It can be appreciated that a sacrificial layer attached to the bottom of the first gate electrode layer, the sidewall of the first gate dielectric layer, and the sidewall of the first mask may be deposited on the first gate electrode layer in the BL region, the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer, and then the bottom of the sacrificial layer and the first gate electrode layer under the sacrificial layer are anisotropically etched to obtain the first recess. Since the anisotropic etch is from the bottom of the sacrificial layer down, and there is also a portion of the first gate electrode layer under the sidewalls of the sacrificial layer, this portion of the first gate electrode layer remains.
The insulating material may be, for example, oxide, nitride, or the like. In the deposition of the sacrificial layer, a very thin film may be deposited on the surface of the substrate by atomic layer deposition (atomic layer deposition, ALD).
In some embodiments, the sacrificial layer may be removed after the first recess is formed.
It will be appreciated that after forming the first recess, an insulating material may be deposited over the first gate structure in the WL region and within the first recess to form a first insulating layer, an upper surface of the first insulating layer being flush with an upper surface of the first mask. And then removing the first mask to form a second groove, and forming a first source-drain structure of the front-side transistor in the second groove. The first insulating layer is used for being isolated from the first source-drain structure of the front-side transistor. In the case that the transistor formed in the embodiment of the present application is VCT, the source structure and the drain structure of VCT are approximately symmetrical, so for convenience of explanation, the first source-drain structure referred to in the embodiment of the present application is simply referred to as a first source structure and/or a first drain structure. In addition, the same is true for the second source drain structure which appears later.
For example, a metal material may be first ion-implanted into the second recess, and then annealed to form a silicide, where the silicide is used as the first source drain structure, and this is only exemplary, and may be determined according to needs in actual operation. In the case of using silicide as the first source structure, the BL structure may be used as the first drain structure. In the case of silicide as the first drain structure, the BL structure may be used as the first source structure.
In some embodiments, an insulating material may be deposited on the first gate structure in the WL region, forming an isolation layer, so that only the BL region is processed. In this manner, the isolation layer over the WL region may be removed after the sacrificial layer is removed, so that the first insulating layer is formed on both the WL region and the BL region.
In some embodiments, after the sacrificial layer is removed, an oxide material may also be deposited within the first recess in the BL region, forming a first oxide layer. A first insulating layer is then formed over the first oxide layer in the BL region and the first gate structure in the WL region. The first oxide layer may also be formed by ALD deposition, for example.
After forming the first source drain structure, a capacitance structure of the front side memory may be formed on the front side transistor.
In some embodiments, forming the first capacitor structure on the first transistor may be performed by forming a first dielectric layer on the first source-drain structure, etching a first portion of the first dielectric layer to expose the first source-drain structure, and forming the first capacitor structure on the first source-drain structure.
It will be appreciated that a first capacitor structure comprising a first electrode and a second electrode and a capacitor dielectric layer between the first electrode and the second electrode may be formed by depositing an insulating medium over the first source drain structure, forming a first dielectric layer, then etching a portion of the first dielectric layer to expose the underlying first source drain structure, and depositing a layer of metal material over the first source drain structure, then depositing a dielectric material, and then depositing a layer of metal material. The first dielectric layer between the first capacitor structures can be used as an isolation structure between the first capacitor structures.
And step 140, rewinding the first memory and removing the substrate to expose the first semiconductor structure.
In some embodiments, the step S140 may be implemented by rewinding the first memory and removing the substrate, and thinning the first shallow trench isolation structure to a predetermined height to expose the first semiconductor structure, where the thinned first shallow trench isolation structure is used to isolate the first transistor from the second transistor.
It will be appreciated that after the first capacitor structure is formed, the first capacitor structure may be bonded to a carrier wafer, then the first capacitor structure is reworked, and the substrate is removed, so that the first semiconductor structure is exposed, facilitating subsequent fabrication of the backside memory.
In some embodiments, an insulating material (e.g., silicon oxide) may be deposited over the first capacitor structure to form a third insulating layer and bonded to the carrier wafer, after which the first capacitor structure is reworked and the substrate removed.
After the substrate is removed, the upper surface of the first semiconductor structure is flush with the upper surface of the first shallow trench isolation structure, so that the first shallow trench isolation structure can be thinned to a preset height, and the first semiconductor structure is exposed. The preset height can be set according to actual requirements, which is not limited in the embodiment of the present application.
And step S150, etching the first semiconductor structure in the BL area to form a second active structure.
It is appreciated that the first semiconductor structure formed as described above includes the second active structure in the WL area and the first material layer in the BL area. Therefore, after rewinding, the etching back area needs to be stopped at the BL structure to form a second active structure, that is, the first material layer is etched along the WL direction to form the second active structure, where the second active structure includes the second active structure in the WL area and the second active structure in the BL area.
In some embodiments, after the first shallow trench isolation structure is thinned, a second mask may be formed on the first material layer in the BL region and the second active structure in the WL region, where the second mask is used to locate the second active structure in the BL region, so that when the first material layer in the BL region is etched down based on the second mask, the second active structure in the BL region may be formed, and the structure in the WL region is not affected.
In some embodiments, after forming the second active structure, an oxide material may be deposited over the BL structure in the BL region to form a third shallow trench isolation structure.
It is understood that after the first shallow trench isolation structure and the third shallow trench isolation structure are formed, the first shallow trench isolation structure and the third shallow trench isolation structure may be thinned to a predetermined height to expose the gate region of the back side transistor for subsequent fabrication of the gate structure of the back side transistor.
Step S160, forming a second memory based on the second active structure.
In some embodiments, the implementation of step S160 may include two steps of forming a second transistor based on the second active structure, and forming a second capacitance structure on the second transistor.
In some embodiments, forming the second transistor based on the second active structure may be performed by forming a second gate structure based on the second active structure, removing the second gate structure in the BL region to form a third recess, depositing an insulating material on the second gate structure in the WL region and in the second recess to form a second insulating layer, an upper surface of the second insulating layer being flush with an upper surface of a second mask located on the second active structure, removing the second mask to form a fourth recess, and forming a second source drain structure in the fourth recess.
It will be appreciated that after thinning the first shallow trench isolation structure and the third shallow trench isolation structure to a predetermined height, the gate region of the back side transistor is exposed, i.e., a second gate recess is formed between the second active structures, such that an insulating material may be deposited at the second gate recess to form a second gate dielectric layer, and a metal material may be deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together form a second gate structure. The height of the second gate dielectric layer may be higher than the height of the second gate electrode layer.
In some embodiments, removing the second gate structure in the BL region and forming the third recess may be performed by forming a sacrificial layer on the second gate electrode layer in the BL region, the upper surface of the sacrificial layer being flush with the upper surface of the second gate dielectric layer, anisotropically etching the bottom of the sacrificial layer and the second gate electrode layer under the sacrificial layer to form the third recess.
It can be appreciated that a sacrificial layer attached to the bottom of the second gate electrode layer, the sidewall of the second gate dielectric layer, and the sidewall of the second mask may be deposited on the second gate electrode layer in the BL region, the upper surface of the sacrificial layer is flush with the upper surface of the second gate dielectric layer, and then the bottom of the sacrificial layer and the second gate electrode layer under the sacrificial layer are anisotropically etched to obtain the third recess. Since the anisotropic etch is from the bottom of the sacrificial layer down and there is also a portion of the second gate electrode layer under the sidewalls of the sacrificial layer, this portion of the second gate electrode layer remains.
In some embodiments, the sacrificial layer may be removed after the third recess is formed.
After forming the third recess, an insulating material may be deposited on the second gate structure in the WL region and in the third recess to form a second insulating layer, an upper surface of the second insulating layer being flush with an upper surface of the second mask. And removing the second mask to form a fourth groove, and forming a second source-drain structure of the back side transistor in the fourth groove.
In some embodiments, an insulating material may be deposited on the second gate structure in the WL region, forming an isolation layer, so that only the BL region is processed. In this manner, the isolation layer over the WL region may be removed after the sacrificial layer is removed, so that the second insulating layer is formed on both the WL region and the BL region.
In some embodiments, after the sacrificial layer is removed, an oxide material may also be deposited in the third recess in the BL region, forming a second oxide layer. A second insulating layer is then formed over the second oxide layer in the BL region and the second gate structure in the WL region. The second oxide layer may also be formed by ALD deposition, for example.
After forming the second source drain structure, a capacitance structure of the back side memory may be formed on the back side transistor.
In some embodiments, forming the second capacitor structure on the second transistor may be performed by forming a second dielectric layer on the second source-drain structure, etching a first portion of the second dielectric layer to expose the second source-drain structure, and forming the second capacitor structure on the second source-drain structure.
It will be appreciated that a second capacitor structure comprising a first electrode and a second electrode and a capacitor dielectric layer between the first electrode and the second electrode may be formed by depositing an insulating medium over the second source drain structure, forming a second dielectric layer, then etching a portion of the second dielectric layer to expose the underlying second source drain structure, and depositing a layer of metal material over the second source drain structure, then depositing a dielectric material, and then depositing a layer of metal material. The second dielectric layer between the second capacitor structures can be used as an isolation structure between the second capacitor structures.
In the present application, a first memory (front memory) is prepared by forming a first semiconductor structure and a second active structure on a substrate, then performing ion implantation in a region on the first semiconductor adjacent to the second active structure to form a BL structure located between the first semiconductor structure and the first active structure, the first semiconductor structure, the BL structure and the first active structure being self-aligned in the BL region, then preparing the first memory (front memory) based on the front active structure (first active structure), rewinding the front memory and removing the substrate to expose the first semiconductor structure, then etching the first semiconductor structure in the BL region to form the second active structure, and finally preparing a second memory (back memory) based on the second active structure. The application ensures the self alignment of the front and back BL through BL area integrated molding. Through wafer bonding and rewinding, two storage units with the size of 4F 2 are integrated on the front side and the back side, so that the equivalent area of the memory is 2F 2, the area of the storage unit of the memory is reduced, and the storage density and the integration level of the memory are improved. In addition, the BL structure is formed by the ion implantation method, the steps are simple, and the cost can be saved.
The following describes a method for manufacturing a memory according to an embodiment of the present application, taking VCT as an example. Fig. 2 is a schematic top view of the memory according to the embodiment of the present application, and for ease of understanding, only BL structure, WL structure and capacitor structure are shown in the top view. The A-A 'direction is the tangential direction of the memory along the BL structure, and the B-B' direction is the tangential direction of the memory along the WL structure.
Fig. 3 to 24 are schematic structural diagrams of a memory in a manufacturing process according to an embodiment of the present application, and fig. 25 is a schematic structural diagram of a memory according to an embodiment of the present application. Fig. 3 to 25 (a) are sectional views of the memory along a sectional direction (i.e., A-A 'direction) of the BL structure, and fig. 3 to 25 (B) are sectional views of the memory along a sectional direction (i.e., B-B' direction) of the WL structure.
In one example, the process of preparing memory 10 may include the steps of:
A first step of sequentially forming a first material layer 21 and a second material layer 22 on an original substrate 20, and forming a first mask 23 on the second material layer 22, wherein the first mask 23 is used for defining an active structure of a WL region, resulting in a structure as shown in fig. 3.
The first material layer and the second material layer are doped the same and are used for forming an active structure shared by the front-side transistor and the back-side transistor.
The second step is to etch the second material layer 22 and the first material layer 21 of the WL area in sequence up to the substrate 20 based on the first mask 23 to form a self-aligned semiconductor structure 24, wherein the semiconductor structure 24 includes a first semiconductor structure 241 and a second semiconductor structure 242, resulting in the structure shown in fig. 4.
Third, oxide material is deposited on the substrate 20 in the WL area to form the first shallow trench isolation structure 25, and CMP is performed to the upper surface of the first mask 23 to obtain the structure shown in fig. 5.
And fourthly, forming a third mask 26 through photoetching and etching, and preparing for WL etching, wherein the third mask 26 is used for defining an active structure of the WL region, so as to obtain the structure shown in figure 6.
And fifthly, etching according to the WL photoetching layout, namely, etching based on the third mask 26, so as to form a first active structure 111, thereby obtaining the structure shown in fig. 7.
In a sixth step, ion implantation is performed on the first semiconductor structure 251 based on the third mask 26 to form a third semiconductor structure 27 in the BL region, resulting in the structure shown in fig. 8.
Wherein the doping concentration of the third semiconductor structure 27 is higher than the doping concentration of the first semiconductor structure 251.
And seventh, annealing to promote ion diffusion and form a fully connected BL structure 28, thereby obtaining the structure shown in FIG. 9.
As shown in fig. 9 (a), the BL structure is a continuous structure in the BL region. As shown in fig. 9 (b), the BL structure is a discontinuous structure in the WL region. This step can ensure self-alignment of the BL direction.
Eighth step, etching the third mask 26, depositing a second shallow trench isolation structure 29 on the BL structure in the BL region, and CMP the first shallow trench isolation structure and the second shallow trench isolation structure to a certain height to obtain the structure shown in FIG. 10.
And a ninth step of selectively depositing an insulating material on the surface of the first active structure 111 to form a first gate dielectric layer 1131, thereby obtaining the structure shown in fig. 11.
A tenth step of depositing a metal material on the first gate dielectric layer 1131 and CMP to a certain height to form a first gate electrode layer 1132, thereby obtaining the structure shown in fig. 12.
The first gate dielectric layer 1131 and the first gate electrode layer 1132 form the first gate structure 113, and the height of the first gate dielectric layer 1131 is higher than the height of the first gate electrode layer 1132.
An eleventh step of forming an isolation layer 30 by photolithography and etching to cover the WL region so that only the BL region is processed later, resulting in the structure shown in fig. 13.
A twelfth step of depositing a sacrificial layer 31 attached to the bottom of the first gate electrode layer 1132, the sidewall of the first gate dielectric layer 1131, and the sidewall of the first mask 23 on the first gate electrode layer 1132 to obtain the structure shown in fig. 14.
Thirteenth, the bottom of the sacrificial layer 31 and the first gate electrode layer 1132 under the sacrificial layer 31 are anisotropically etched, and then the sacrificial layer 31 is removed to form the first recess 32, resulting in the structure shown in fig. 15.
It will be appreciated that the anisotropic etch is from the bottom of the sacrificial layer down and that there is also a portion of the first gate electrode layer below the sidewalls of the sacrificial layer, so that this portion of the first gate electrode layer remains, see fig. 15 (a).
Illustratively, in depositing the sacrificial layer, a very thin sacrificial layer may be deposited on the substrate surface by ALD deposition.
A fourteenth step is to deposit an oxide material in the first recess 32 to form a first oxide layer 33, resulting in the structure shown in fig. 16.
A fifteenth step is to remove the isolation layer 30 over the WL area and deposit an insulating material (e.g. SiN) in both areas to form a first insulating layer 34, resulting in the structure shown in fig. 17.
Sixteenth, the first mask 23 is selectively etched to form the second recess 35, resulting in the structure shown in fig. 18.
Seventeenth, forming a first source-drain structure 112 in the second recess 35, and depositing an insulating medium on the first source-drain structure 112 to form a first dielectric layer 36, thereby obtaining the structure shown in fig. 19.
For example, a metal material may be deposited by ion implantation in the second recess 35, and then annealed to form a silicide as the first source drain structure.
Eighteenth, etching a portion of first dielectric layer 36 to expose first source drain structure 112 and forming first capacitor structure 37 over first source drain structure 112, resulting in the structure shown in fig. 20.
The first capacitor structure may include deposition of a metal upper plate, deposition of a dielectric layer, and deposition of a metal lower plate, and fig. 20 is merely a simplified representation.
Here, the first drain structure of the first transistor is connected to the BL structure 28, and the first source structure of the first transistor is connected to the first capacitor structure 37.
Nineteenth, an insulating material is deposited on the first capacitor structure 37 to form the third insulating layer 13, and the third insulating layer 13 is bonded to the carrier wafer 14, followed by rewinding to obtain the structure shown in fig. 21.
The twentieth step is to remove the substrate 20 to the first shallow trench isolation structure 25, resulting in the structure shown in fig. 22.
In a twenty first step, a second mask 38 is formed and etching is performed based on the second mask 38 to form a second active structure 121, resulting in the structure shown in fig. 23.
Twenty-second, depositing oxide material on the BL structure in the BL region and CMP to a height to form a third shallow trench isolation structure 39, resulting in the structure shown in fig. 24.
Twenty-third, a second transistor and a second capacitor structure 43 are fabricated, resulting in the structure shown in fig. 25.
It may be appreciated that, first, an insulating material is selectively deposited on the surface of the second active structure 121 to form a second gate dielectric layer 1231, and a metal material is deposited on the second gate dielectric layer 1231 and CMP is performed to a certain height to form a second gate electrode layer 1232, so that the second gate structure 123 may be formed. And then forming an isolation layer by photoetching and etching to cover the WL region, so that the BL region is conveniently processed. Thereafter, a sacrificial layer may be deposited on the second gate electrode layer 1232 to adhere to the bottom of the second gate electrode layer 1242, the sidewalls of the second gate dielectric layer 1231, and the sidewalls of the second mask 38, the bottom of the sacrificial layer and the second gate electrode layer 1232 under the sacrificial layer are anisotropically etched, then the sacrificial layer is removed to form a recess, an oxide material is deposited in the recess to form the second oxide layer 40, an isolation layer over the WL area is removed, an insulating material (e.g., siN) is deposited in both areas to form the second insulating layer 41, the second mask 38 is selectively etched to form a recess, the second drain structure 122 is formed in the recess, and an insulating medium is deposited on the second source drain structure 122 to form the second dielectric layer 42, a portion of the second dielectric layer 42 is etched to expose the second source drain structure 122, and the second capacitor structure 43 is formed on the second source drain structure 122. Here, the second drain structure of the second transistor is connected to the BL structure 28, and the second source structure of the second transistor is connected to the second capacitor structure 43.
Reference may be made here to the ninth to eighteenth steps.
The application ensures the self alignment of the front and back BL through BL area integrated molding. Through wafer bonding and rewinding, two storage units with the size of 4F 2 are integrated on the front side and the back side, so that the equivalent area of the memory is 2F 2, the area of the storage unit of the memory is reduced, and the storage density and the integration level of the memory are improved. In addition, the BL structure is formed by ion implantation, the steps are simple, and the cost can be saved.
Further, the application starts from the specific process flow of the self-aligned flip-chip stacked transistor, combines with the manufacturing flow of the 4F 2 DRAM, ensures the self alignment of the BL area through BL integrated molding, realizes the manufacturing of the front and back DRAM through wafer bonding of the inverted film, has the volume equivalent of 2F 2, and realizes further miniaturization under the size of an integrated circuit.
Further, the memory provided by the embodiment of the application can be detected by using a detection and analysis instrument, such as a scanning electron microscope (scanning electron microscope, SEM), a transmission electron microscope (transmission electron microscope, TEM), a scanning transmission electron microscope (scanning transmission electron microscopy, STEM) and the like. Taking TEM as an example, the embodiment of the present application may detect the structure of the memory by using a TEM section method, and observe that the 1T1C structure exists in the basic structure of the memory on both the front and back sides. And a cross-section of the substrate is cut to see an initially complete silicon substrate, followed by ion implantation to form the BL structure.
The embodiment of the application provides a semiconductor device, which comprises the memory of the embodiment. The specific limitation of the memory may be referred to the above memory, and will not be described herein.
The embodiment of the application provides electronic equipment, which comprises a circuit board and the semiconductor device in the embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device comprises the memory. The specific limitation of the memory may be referred to the above memory, and will not be described herein.
In the description of the embodiments of the present application, the descriptions of the terms "one embodiment," "an example," "a particular example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (11)
1. A method of manufacturing a memory, the method comprising:
Forming a stacked structure on a substrate, wherein the stacked structure comprises a first semiconductor structure and a first active structure which are sequentially stacked in a first direction, and the doping concentration of the first semiconductor structure is the same as that of the first active structure;
Performing ion implantation on the first semiconductor structure in a region close to the first active structure to form a bit line BL structure, wherein the BL structure is positioned between the first semiconductor structure and the first active structure, and the first semiconductor structure, the BL structure and the first active structure are self-aligned in the BL region along the first direction;
forming a first memory based on the first active structure;
rewinding the first memory and removing the substrate to expose the first semiconductor structure;
Etching the first semiconductor structure in the BL area to form a second active structure;
And forming a second memory based on the second active structure, wherein the BL structure is shared by a first source-drain structure in the first memory and a second source-drain structure in the second memory.
2. The method of claim 1, wherein forming a first stack structure on a substrate comprises:
Sequentially stacking a first material layer and a second material layer along the first direction on the substrate;
Etching the first material layer and the second material layer in a word line WL region to form the first semiconductor structure and the second semiconductor structure;
and etching the second semiconductor structure in the BL area to form the first active structure.
3. The method of claim 1, wherein the performing an ion implantation on the first semiconductor structure in a region proximate to the first active structure to form a bit line BL structure comprises:
Performing ion implantation on a region, close to the first active structure, of the first semiconductor structure in the BL region to form a third semiconductor structure in the BL region;
and annealing the third semiconductor to form the BL structure.
4. The method of claim 1, wherein forming a first memory based on the first active structure comprises:
Forming a first transistor based on the first active structure;
forming a first capacitor structure on the first transistor;
the forming a second memory based on the second active structure includes:
Forming a second transistor based on the second active structure;
A second capacitance structure is formed over the second transistor.
5. The method of claim 4, wherein forming a first transistor based on the first active structure comprises:
Forming a first gate structure based on the first active structure;
removing the first grid structure in the BL area to form a first groove;
depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of a first mask, and the first mask is positioned on the first active structure;
removing the first mask to form a second groove;
and forming a first source drain structure in the second groove.
6. The method of claim 5, wherein the first gate structure comprises a first gate electrode layer and a first gate dielectric layer surrounding the first gate electrode layer, the first gate electrode layer having a height that is lower than a height of the first gate dielectric layer;
the removing the first gate structure in the BL region to form a first recess includes:
Forming a sacrificial layer on the first gate electrode layer in the BL region, wherein the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer;
and anisotropically etching the bottom of the sacrificial layer and the first gate electrode layer positioned below the sacrificial layer to form the first groove.
7. The method of claim 5 or 6, wherein forming a first capacitance structure on the first transistor comprises:
Forming a first dielectric layer on the first source drain structure;
etching a first part of the first dielectric layer to expose the first source drain structure;
And forming the first capacitor structure on the first source-drain structure.
8. The method of claim 4, wherein forming a second transistor based on the second active structure comprises:
forming a second gate structure based on the second active structure;
Removing the second grid structure in the BL area to form a third groove;
Depositing an insulating material on the second gate structure in the WL region and in the third groove to form a second insulating layer, wherein the upper surface of the second insulating layer is flush with the upper surface of a second mask, and the second mask is positioned on the second active structure;
removing the second mask to form a fourth groove;
And forming a second source drain structure in the fourth groove.
9. A memory prepared using the preparation method according to any one of claims 1 to 8, comprising:
A BL structure;
A first memory;
The second memory is arranged opposite to the first memory, and the BL structure is shared by a first source-drain structure in the second memory and a second source-drain structure in the first memory.
10. A semiconductor device according to claim 9, comprising a memory.
11. An electronic device comprising a circuit board and the semiconductor device according to claim 10, wherein the semiconductor device is provided on the circuit board.
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| WO2020263340A1 (en) * | 2019-06-27 | 2020-12-30 | Sandisk Technologies Llc | Ferroelectric memory device containing a series connected select gate transistor and method of forming the same |
| CN115377008A (en) * | 2021-05-19 | 2022-11-22 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN115440732A (en) * | 2022-09-15 | 2022-12-06 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
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| CN111952312A (en) * | 2019-05-17 | 2020-11-17 | 三星电子株式会社 | semiconductor device |
| WO2020263340A1 (en) * | 2019-06-27 | 2020-12-30 | Sandisk Technologies Llc | Ferroelectric memory device containing a series connected select gate transistor and method of forming the same |
| CN115377008A (en) * | 2021-05-19 | 2022-11-22 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN115440732A (en) * | 2022-09-15 | 2022-12-06 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
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