CN119135168A

CN119135168A - High-precision successive approximation ADC test circuit and test method

Info

Publication number: CN119135168A
Application number: CN202411159389.4A
Authority: CN
Inventors: 杨良春; 何文博
Original assignee: Beijing Sinodynetest Science & Technology Co ltd
Current assignee: Beijing Sinodynetest Science & Technology Co ltd
Priority date: 2024-08-22
Filing date: 2024-08-22
Publication date: 2024-12-13

Abstract

The present application provides a high-precision successive approximation ADC test circuit and test method, which relates to the field of analog-to-digital converter testing. The circuit of the present application mainly includes a control bus terminal, a control comparison module, an integrator module, a power supply module and an input signal conditioning module. Among them, the control bus terminal generates an initial digital signal to generate an adjustment control signal according to the key weight carry point that is easy to introduce DNL errors, and controls the power supply module to charge and discharge the integrator module. The integrator module integrates the input current and outputs an integral voltage proportional to the integral value to the input signal conditioning module. The input signal conditioning module generates an analog input signal ADIN according to the integral voltage to perform analog-to-digital conversion on the ADC under test, outputs a digital code value, and generates a target voltage signal. Through this test circuit structure and test process, the DNL error characteristics of the ADC can be accurately evaluated.

Description

High-precision successive approximation type ADC test circuit and test method

Technical Field

The application relates to the field of analog-to-digital converter testing, in particular to a high-precision successive approximation type ADC (analog-to-digital converter) testing circuit and a testing method.

Background

Successive approximation analog-to-digital converters (SAR ADCs) are widely used in various electronic devices due to their low power consumption, high speed and high resolution. With the continuous development of technology, the requirements on the accuracy of the ADC are also higher and higher. However, in practical applications, the ADC often has Differential Nonlinearity (DNL) errors, that is, inconsistent jump steps between adjacent code values, resulting in reduced conversion accuracy.

Currently, a common method for testing differential nonlinear errors of an ADC is to generate an analog signal corresponding to an input range of the ADC using a high-precision digital-to-analog converter (DAC), and measure an output digital code value of the ADC. By comparing the difference between the ideal code value and the actual code value, the DNL error can be calculated. However, this approach has certain limitations. Firstly, the cost of the high-precision DAC is high, linearity and stability of an output signal of the high-precision DAC are difficult to ensure, and extra test errors are easy to introduce. Secondly, the method needs to traverse the whole input range of the ADC, and has longer test time and lower efficiency. In addition, as the conversion characteristics of the ADC have differences at different code values, simply and equally spacing scanning input signals is difficult to accurately capture DNL errors at key code values, and the reliability of test results is affected.

Disclosure of Invention

The application provides a high-precision successive approximation type ADC test circuit and a test method, which are used for improving the accuracy of the performance evaluation of an ADC.

In a first aspect, the application provides a high-precision successive approximation type ADC test circuit, which comprises a control bus end, a control comparison module, an integrator module, a power supply module and an input signal conditioning module;

The control comparison module is electrically connected with the ADC to be tested, the control comparison module is electrically connected with the integrator module, the integrator module is electrically connected with the input signal conditioning module, the input signal conditioning module is electrically connected with the ADC to be tested, the power supply module is electrically connected with the control comparison module, the integrator module and the input signal conditioning module, and the control bus end is electrically connected with the control comparison module;

The control bus terminal is used for generating an initial digital signal according to a key weight bit position point which is easy to introduce DNL error and outputting the initial digital signal to the control comparison module to start a test;

the control comparison module is used for generating an initial control signal according to the digital signal;

The control comparison module is also used for generating an adjusting control signal according to the data output by the tested ADC;

The power supply module is used for charging or discharging the integrator module according to the initial control signal or the adjustment control signal;

the integrator module is used for integrating input current according to the initial control signal or the adjustment control signal output by the control comparison module to obtain an integrated value and outputting an integrated voltage proportional to the integrated value to the input signal conditioning module;

the input signal conditioning module is used for generating an analog input signal ADIN according to the integrated voltage to carry out analog-to-digital conversion on the tested ADC and outputting a digital code value;

The input signal conditioning module is further configured to generate a target voltage signal according to the integrated voltage.

By adopting the technical scheme, the high-precision successive approximation type ADC test circuit provided by the invention realizes high-efficiency and accurate test of ADC differential nonlinear errors through a carefully designed hardware structure and test method. The test circuit comprises a control bus end, a control comparison module, an integrator module, a power supply module and an input signal conditioning module, wherein the modules are connected reasonably and electrically to form a complete test system. The control bus terminal generates an initial digital signal to generate an initial control signal according to a key bit position point which is easy to introduce DNL error, and generates an adjustment control signal according to data output by the tested ADC. The power supply module charges or discharges the integrator module according to the initial control signal or the adjusting control signal, so that the accurate control of the test signal is realized. The integrator module integrates the input current according to the initial control signal or the adjustment control signal output by the control comparison module to obtain an integral value, and outputs an integral voltage proportional to the integral value to the input signal conditioning module. The input signal conditioning module generates an analog input signal ADIN according to the integrated voltage to carry out analog-to-digital conversion on the tested ADC, outputs a digital code value and also generates a target voltage signal according to the integrated voltage. Through the cooperative work of the hardware structure, the test circuit can be a high-precision successive approximation type ADC test circuit, so that the voltage value of the output of the operational amplifier after differential amplification is stabilized at a level corresponding to a preset digital signal. The automatic adjustment mechanism can effectively compensate for environmental interference and device drift in the test process, and ensure the precision and stability of test signals, thereby improving the reliability of test results. Compared with the traditional method for generating the test signal by using the high-precision DAC, the method does not need to use an expensive DAC device, reduces the test cost, and simultaneously avoids extra errors caused by insufficient linearity and stability of the DAC output signal.

Optionally, the value of the initial digital signal is related to the reference voltage of the ADC under test, the supply voltage of the DAC, and the input voltage range of the ADC under test.

By adopting the technical scheme, the high-precision successive approximation type ADC test circuit provided by the invention can accurately control the output voltage of the test circuit in the range of the input voltage of the tested ADC when generating the value of the initial digital signal, so that the test failure or error caused by the exceeding range of the test signal is avoided. Meanwhile, the test circuit can output a test signal matched with the tested ADC according to the value of the initial digital signal, so that the smooth running of the test process and the accuracy of the test result are ensured. Meanwhile, by optimizing the selection of test points, key code values which are easy to introduce errors are tested, and the testing efficiency and the testing precision are improved.

Optionally, the control comparison module comprises a control signal generation unit, a data comparison unit and a logic judgment unit, wherein the control signal generation unit is electrically connected with the data comparison unit and the logic judgment unit in sequence;

The control signal generation unit is used for determining an input digital quantity DB according to the digital signal;

The control signal generation unit is also used for generating an output digital quantity DA according to the data output by the tested ADC;

The data comparison unit is used for comparing a preset digital quantity B with the input digital quantity DB to obtain an initial comparison result;

The data comparison unit is further used for comparing the preset digital quantity B with the output digital quantity DA to obtain an adjustment comparison result;

The logic judging unit is used for generating the corresponding control signal to the power supply module according to the initial comparison result or the adjustment comparison result.

By adopting the technical scheme, the high-precision successive approximation type ADC test circuit provided by the invention adopts the combination of the control signal generation unit, the data comparison unit and the logic judgment unit in the design of the control comparison module, and realizes the accurate control and automatic adjustment of the test process through reasonable electric connection and functional division. The control signal generating unit generates an output digital quantity DA according to the digital signal, and provides a basis for subsequent data comparison and logic judgment. The data comparison unit compares the preset digital quantity B with the input digital quantity DB and the output digital quantity DA respectively to obtain an initial comparison result and an adjustment comparison result, and provides a basis for the decision of the logic judgment unit. The logic judging unit generates a corresponding control signal to the power supply module according to the initial comparison result or the adjustment comparison result, and realizes automatic adjustment and feedback control of the test circuit. By controlling the cooperative work of the comparison module, the test circuit can dynamically adjust the test signal according to the output data of the tested ADC, so that the test signal is stabilized at a level corresponding to a preset digital signal, and the self-adaption and the robustness of the test process are ensured. Compared with the traditional open loop test method, the invention introduces a closed loop feedback control mechanism, dynamically adjusts the test signal by monitoring the output data of the tested ADC in real time, effectively compensates the environmental interference and the device drift in the test process, and improves the test precision and the reliability. Meanwhile, by reasonably dividing the functional units of the control comparison module, the modularization and structuring of the test process are realized, and the maintainability and expandability of the test circuit are improved. The design of the control signal generating unit, the data comparing unit and the logic judging unit clearly reflects the logic flow of the test process, is convenient to understand and optimize, and provides convenience for further improvement of the test circuit. Therefore, in the design of the control comparison module, the self-adaption and the robustness of the test process are realized by introducing a closed-loop feedback control mechanism, and the test precision and the reliability are improved. Meanwhile, through the modularized and structured design, maintainability and expandability of the test circuit are enhanced, and powerful technical support is provided for testing of the high-precision ADC.

Optionally, the integrator module comprises an operational amplifier and an integrating capacitor;

the integrating capacitor is connected with the operational amplifier in parallel, and the operational amplifier is electrically connected with the control comparison module.

By adopting the technical scheme, the high-precision successive approximation type ADC test circuit provided by the invention adopts a structure that an operational amplifier and an integrating capacitor are connected in parallel in the design of an integrator module, and realizes accurate integration and voltage output of input current through reasonable electrical connection and device selection. The operational amplifier is used as a core device of the integrator, has the characteristics of high gain, high input impedance and low output impedance, and can amplify and convert tiny input current to obtain output voltage in direct proportion to an integral value. The integrating capacitor is connected with the operational amplifier in parallel, plays a key role in a feedback loop of the operational amplifier, and converts a current signal into a voltage signal by continuously integrating an input current, thereby realizing the conversion and the processing of the signal. Meanwhile, the capacitance value of the integrating capacitor directly influences the sensitivity and the time constant of the integrator, and the performance of the integrator can be optimized and the testing precision and speed can be improved by reasonably selecting the capacitance value of the integrating capacitor. Compared with the traditional resistor feedback integrator, the invention adopts a capacitive feedback mode, avoids noise and drift of a resistor device, and improves the stability and reliability of the integrator. Through the parallel design of the operational amplifier and the integrating capacitor, the integrator module can convert the control signal output by the control comparison module into a voltage signal in direct proportion to the integral value, and a foundation is provided for subsequent signal conditioning and ADC conversion. The output voltage of the integrator module is accurately controlled and regulated and stabilized at a level corresponding to a preset digital signal, so that the accuracy and consistency of the test signal are ensured. Therefore, in the design of the integrator module, the invention realizes accurate integration and voltage output of input current through the parallel structure of the operational amplifier and the integrating capacitor, and improves the stability and reliability of the integrator. Meanwhile, the capacity value of the integrating capacitor is reasonably selected, so that the performance of the integrator is optimized, and the testing precision and speed are improved. The accurate output of the integrator module provides a reliable basis for subsequent signal conditioning and ADC conversion, ensures the accuracy and consistency of the whole test circuit, and provides a powerful technical guarantee for the test of the high-precision ADC.

Optionally, the input signal conditioning module comprises an adder and a differential amplifier;

the adder is electrically connected with the differential amplifier, and the differential amplifier is electrically connected with the ADC to be tested.

By adopting the technical scheme, the high-precision successive approximation type ADC test circuit provided by the invention adopts the combination of the adder and the differential amplifier in the design of the input signal conditioning module, and realizes the accurate conditioning and processing of the integrator output signal through reasonable electric connection and functional division. And the adder receives the integrated voltage output by the integrator module and superimposes the integrated voltage with other signals to obtain a composite signal. The differential amplifier receives the composite signal output by the adder, converts the composite signal into a differential signal, and amplifies the differential signal to obtain an analog input signal ADIN proportional to the integrated voltage. Through the cascade design of the adder and the differential amplifier, the input signal conditioning module can accurately condition the integral voltage, inhibit common mode interference and improve the quality and the integrity of signals. Compared with a single-ended signal, the differential signal has stronger anti-interference capability and noise suppression capability, can effectively reduce electromagnetic interference and noise in a test environment, and improves test precision and reliability. Meanwhile, through the amplification effect of the differential amplifier, the amplitude of the analog input signal ADIN is improved, the driving capability of the signal is enhanced, and the normal operation of the tested ADC is ensured. In addition, the high common mode rejection ratio and the low offset voltage characteristic of the differential amplifier further improve the precision and stability of the test signal. The accurate output of the input signal conditioning module directly influences the conversion performance of the ADC to be tested, and the reasonable design of the adder and the differential amplifier ensures that the analog input signal ADIN corresponds to a preset digital signal, thereby providing reliable input for the accurate conversion of the ADC. Meanwhile, the input signal conditioning module also generates a target voltage signal according to the integrated voltage, and provides a reference for evaluation and calibration of test results. Through accurate conditioning and processing of the input signal conditioning module, the test circuit can provide high-quality and low-noise analog input signals for the tested ADC, and the requirement of high-precision testing is met. Therefore, in the design of the input signal conditioning module, the invention realizes the accurate conditioning and processing of the output signal of the integrator through the combination of the adder and the differential amplifier, and improves the quality and the integrity of the test signal. The differential signal transmission mode is adopted, so that the anti-interference capability and the noise suppression capability are enhanced, and the test precision and reliability are improved. Meanwhile, the amplitude and stability of the analog input signal ADIN are ensured through the amplification function and excellent characteristics of the differential amplifier, and reliable input is provided for accurate conversion of the tested ADC. The accurate output of the input signal conditioning module provides reference for evaluation and calibration of test results, further improves the performance and reliability of a test circuit, and provides powerful technical support for testing of high-precision ADC.

Optionally, the parameters of the measured ADC include a reference voltage Vref, a supply voltage VS, and an input voltage range Vrange of the measured ADC, and the preset digital quantity B is determined according to the parameters of the measured ADC, where b≡ (VS/Vrange) ×2ζ≡n, n is the resolution of the measured ADC.

By adopting the technical scheme, the preset digital quantity B is determined according to parameters of the ADC to be tested, namely B is approximately equal to (VS/Vrange) x 2≡N, wherein VS is a power supply voltage, vrange is an input voltage range of the ADC to be tested, and N is resolution of the ADC to be tested. The setting mode has the advantages that the determination of the preset digital quantity B comprehensively considers key parameters such as the power supply voltage VS, the input voltage range Vrange, the resolution N and the like of the tested ADC. Since B≡ (VS/Vrange) ×2≡N, it can be seen that the preset digital quantity B is proportional to the supply voltage VS, inversely proportional to the input voltage range Vrange, and increases exponentially with increasing resolution N. The relation accurately reflects the conversion characteristic of the ADC, and provides a reasonable reference standard for the subsequent DNL error test.

On the other hand, the application also provides a high-precision successive approximation type ADC test method, which comprises the following steps:

selecting a group of representative test code values according to the resolution and the test requirement of the ADC to be tested;

generating a corresponding initial digital signal according to the test code value, and sequentially inputting the initial digital signal into the high-precision successive approximation type ADC test circuit to obtain an initial measurement voltage;

And determining DNL error according to the initial measurement voltage, and evaluating the ADC to be tested according to the DNL error to obtain an evaluation result.

By adopting the technical scheme, the method and the device select a group of representative test code values, generate corresponding initial digital signals according to the test code values, sequentially input the initial digital signals into the high-precision successive approximation type ADC test circuit to obtain initial measurement voltage, determine DNL errors according to the initial measurement voltage, and evaluate the tested ADC based on the DNL errors to obtain an evaluation result. The method fully utilizes the high-precision characteristic of the high-precision successive approximation type ADC test circuit, and can accurately acquire the nonlinear error characteristic of the ADC by accurately measuring the actual output voltage of the tested ADC under different code values. By selecting representative test code values, the performance of the ADC in the whole input range can be comprehensively evaluated, and the pertinence and the effectiveness of the test are improved. Meanwhile, the nonlinearity degree of the ADC can be quantitatively evaluated by analyzing DNL errors, and an important basis is provided for subsequent calibration and optimization.

In summary, one or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:

1. According to the application, a group of representative test code values are selected, corresponding initial digital signals are generated according to the test code values, the initial digital signals are sequentially input into a high-precision successive approximation type ADC test circuit to obtain initial measurement voltage, DNL errors are determined according to the initial measurement voltage, and the tested ADC is evaluated based on the DNL errors, so that an evaluation result is obtained. The method fully utilizes the high-precision characteristic of the high-precision successive approximation type ADC test circuit, and can accurately acquire the nonlinear error characteristic of the ADC by accurately measuring the actual output voltage of the tested ADC under different code values. By selecting representative test code values, the performance of the ADC in the whole input range can be comprehensively evaluated, and the pertinence and the effectiveness of the test are improved. Meanwhile, the nonlinearity degree of the ADC can be quantitatively evaluated by analyzing DNL errors, and an important basis is provided for subsequent calibration and optimization.

2. And subtracting the initial measured voltage from the ideal output voltage corresponding to the code value to obtain the actual voltage error under each test code value. This step accurately quantifies the actual error characteristics of the ADC at different input code values by directly comparing the measured voltage to the ideal voltage. By eliminating systematic bias and common mode errors in the measured voltage, the nonlinear error component inherent to the ADC is extracted. After the voltage errors of all the test code values are obtained, the voltage errors corresponding to the two adjacent test code values are further subtracted, so that DNL errors are obtained. The differential calculation method skillfully utilizes the relevance between adjacent code values, and directly obtains the quantization result of DNL errors by comparing the voltage error differences of the adjacent code values. Since the input signal variation corresponding to adjacent code values is minimal, the voltage error difference between them most reflects the non-linearity of the ADC at the code value transition point. The DNL error calculated by the method can accurately characterize the tiny nonlinear error of the ADC during the conversion of adjacent code values.

3. In the process of evaluating the measured ADC according to DNL errors, an intuitive and effective analysis method is adopted. The frequency distribution condition of DNL errors in different cells can be clearly shown by drawing a DNL error distribution histogram of the measured ADC. The DNL error distribution histogram takes the DNL error as an abscissa and the corresponding frequency as an ordinate, and the occurrence probability and distribution rule of the ADC under different nonlinear error levels are revealed through visual graphical representation. By observing the DNL error distribution histogram, the nonlinear error characteristics of the ADC can be directly determined. Ideally, the DNL error should be concentrated around a zero value, exhibiting a morphology resembling a normal distribution. If the DNL error distribution histogram exhibits significant offset, spread, or multiple peaks, it is indicated that there is significant nonlinear error in the ADC and its performance may be affected. By analyzing the frequency distribution of DNL errors in different sizes, the nonlinearity degree of the ADC can be quantitatively evaluated, and whether the ADC meets design indexes and application requirements or not can be judged.

Drawings

Fig. 1 is a schematic structural diagram of a high-precision successive approximation ADC test circuit according to an embodiment of the present application;

FIG. 2 is a schematic flow chart of a high-precision successive approximation type ADC test method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a high-precision successive approximation ADC test circuit provided by the application;

FIG. 4 is a diagram showing a DNL according to the present application;

FIG. 5 is a diagram of a full-code test ramp input waveform

FIG. 6 is a time reference diagram of a full code test ADC according to the present application

FIG. 7 is a diagram showing the test results of a 16-bit successive approximation ADC according to the present application

FIG. 8 is a graph of the test efficiency of a 16-bit successive approximation ADC according to the present application.

Detailed Description

In order that those skilled in the art will better understand the technical solutions in the present specification, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments.

In describing embodiments of the present application, words such as "for example" or "for example" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "such as" or "for example" in embodiments of the application should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "or" for example "is intended to present related concepts in a concrete fashion.

In the description of embodiments of the application, the term "plurality" means two or more. For example, a plurality of systems means two or more systems, and a plurality of screen terminals means two or more screen terminals. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating an indicated technical feature. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

Testing of mixed signal integrated circuits has been an important concern in the industry, where successive approximation analog-to-digital converters (SAR ADCs) have found widespread use in various electronic devices, due to their low power consumption, high speed and high resolution. However, with the continuous progress of technology and the increasing expansion of application fields, the requirements on the accuracy of the ADC are also continuously increased. In practical operation, an ADC often faces the challenge of Differential Nonlinearity (DNL) error, that is, the jump step size between adjacent code values is inconsistent, which results in the conversion accuracy being affected, and becomes one of the key bottlenecks restricting the performance improvement of the ADC.

In order to comprehensively evaluate the differential nonlinear characteristics of the ADC, a testing scheme based on a high-precision Arbitrary Waveform Generator (AWG) and digital channel resources is commonly adopted in the industry at home and abroad. The analog signal matched with the input range of the tested ADC is generated by using the AWG, the analog signal is collected by using the digital channel resource to control the ADC, and the collected data is processed and fitted to obtain a result which can be compared with the input signal, so that the differential linearity ((DIFFERENTIAL LINEARITY, DNL is the core parameter of the ADC electrical parameter test and expressed in figure 4)) parameter of the ADC is analyzed. DNL is used as a core index of ADC electric parameter test, and the definition and test method are definitely specified in national industry standard SJ20961, basic principle of integrated circuit A/D and D/A converter test method.

According to SJ20961 standard, the basic steps of testing DNL are as follows, firstly, finding out the corresponding input level Va when the output code jumps from i-1 to i by adjusting the input level step by step, then, continuously adjusting the input level until the output code jumps from i to i+1, and recording the input level Vb at the moment. It is thus obtained that when the output code is i, its actual code width is Vb-Va. Finally, the DNL value at output code i is calculated according to the formula DNLi = (Vb-Va)/LSB, where LSB represents the ideal code width voltage (LEAST SIGNIFICANT Bit). And repeating the steps to obtain DNL distribution corresponding to all output codes of the ADC. Such a test method is referred to in the industry as a "full-code test method" and reference is made in particular to fig. 5 and 6. However, the above-described conventional testing method based on the high-precision DAC has some limitations that cannot be ignored. Firstly, the cost of the high-precision DAC is high, the linearity and stability of the output signal are difficult to ensure, and extra test errors are easily introduced to influence the accuracy of the test result. Secondly, the method needs to carry out traversal test on the whole input range of the ADC, and has long time consumption and low test efficiency. In addition, as the conversion characteristics of the ADC at different code values are different, simply performing equidistant scanning on the input signal can not accurately capture DNL errors at the key code values, and the reliability of the test result is further affected.

In view of the foregoing background description, those skilled in the art will appreciate that the problems associated with the prior art and the following description will clearly and fully describe the embodiments of the present application with reference to the accompanying drawings, it is evident that the described embodiments are only some, but not all, embodiments of the present application.

On the basis of the background art, referring to fig. 1, fig. 1 is a schematic diagram of a high-precision successive approximation ADC test circuit according to an embodiment of the application, and specifically, the high-precision successive approximation ADC test circuit includes a control bus terminal, a control comparison module, an integrator module, a power module and an input signal conditioning module;

Specifically, referring to fig. 3, a high-precision successive approximation ADC test circuit includes a control bus terminal, a control comparison module, an integrator module, a power module, and an input signal conditioning module. Through the cooperative work of the modules, the testing circuit can effectively test and evaluate the differential nonlinear error of the ADC, and the testing precision and efficiency are improved.

In the test process, the control bus terminal generates an initial digital signal according to a key bit position point which is easy to introduce DNL error, and outputs the initial digital signal to the control comparison module to start the test. The conversion characteristic of the ADC is fully considered in the step, and key code values which are easy to generate DNL errors are selected as test points, so that blind scanning of the whole input range is avoided, the test time is shortened, and the test efficiency is improved.

The control comparison module receives the initial digital signal, generates an adjusting control signal according to the difference between the actual code value and the expected code value, dynamically adjusts the charging and discharging process of the power supply module, and ensures the accuracy and stability of the test signal.

The power module charges or discharges the integrator module according to the initial control signal or the adjusting control signal output by the control comparison module, and stable and reliable power support is provided. The integrator module integrates the input current according to the control signal to obtain an integrated voltage proportional to the integrated value, and outputs the integrated voltage to the input signal conditioning module.

The input signal conditioning module receives the integrated voltage output by the integrator module, generates an analog input signal ADIN corresponding to the integrated voltage, and inputs the analog input signal ADIN to the ADC to be tested for analog-to-digital conversion to obtain an actual digital code value. Meanwhile, the input signal conditioning module also generates a target voltage signal according to the integrated voltage, and the target voltage signal is used as a reference basis for evaluating the ADC performance.

Through the steps, the testing circuit can accurately and efficiently test the differential nonlinear error of the ADC. The initial digital signal generated by the control bus terminal is emphasized to cover the key code value which is easy to introduce DNL error, so that unnecessary test overhead is avoided. The control comparison module realizes accurate control and dynamic adjustment of the test process by generating an initial control signal and an adjustment control signal, and ensures the quality of the test signal. The cooperation of the power supply module and the integrator module provides a stable and reliable hardware basis for generating test signals. The input signal conditioning module provides reliable data support for the evaluation of ADC performance by generating a high quality analog input signal and a target voltage signal.

It should be further noted that, the analog input signal ADIN is an integrated voltage after being conditioned and amplified, and is directly input into the ADC to be tested for analog-to-digital conversion, so as to obtain an actual digital code value. This process is a key step in the test system to actually evaluate the ADC performance. By comparing the difference between the actual output code value and the expected code value, a differential non-linear error (DNL) of the ADC can be derived.

The target voltage signal is used as a reference for evaluating the ADC performance. By comparing the difference between the target voltage and the ADIN signal, the conversion accuracy and linearity of the ADC can be more accurately determined.

The differential amplifier introduced in the input signal conditioning module plays a key role. It performs a 100-fold differential amplification on the ADIN signal so that the test system can detect small voltage variations on the order of 10 uV. The amplification processing greatly improves the sensitivity and the resolution capability of the test, and compared with the traditional full-code test scheme, the test precision is improved by nearly hundred times.

The test results shown in fig. 7 demonstrate the superiority of this test scheme. For a 16-bit ADC, the LSB (least significant bit) is about 76uV, and such small voltage variations are difficult to measure accurately for conventional testing methods. By introducing 100 times of differential amplification, the test system can clearly distinguish the voltage change of 10uV level, so that the differential nonlinear error test of the ADC is more accurate and reliable.

Besides the remarkable improvement of the test precision, the invention also fully utilizes the characteristics of the successive approximation type ADC and further optimizes the test efficiency. Based on the architecture of successive approximation ADC, DNL errors are mainly concentrated at the weight bit-in-place. Thus, by focusing on testing the bit-advance-point, the DNL performance of the ADC can be quickly assessed without having to traverse the entire input range. This targeted test strategy can shorten the test time by approximately 50%, as shown in fig. 8.

On the basis of the above embodiments, as an alternative embodiment, the value of the initial digital signal is related to the reference voltage of the ADC under test, the supply voltage of the DAC, and the input voltage range of the ADC under test.

Specifically, in the high-precision successive approximation type ADC test circuit, the value of the initial digital signal generated at the control bus terminal is closely related to the reference voltage of the ADC under test, the supply voltage of the DAC, and the input voltage range of the ADC under test. Consideration and design of such correlations is critical to ensuring accuracy and applicability of the test signals.

First, the reference voltage of the ADC under test determines its quantization step size and input range. The value of the initial digital signal needs to be matched to the reference voltage to ensure that the generated test signal can cover the entire input range of the ADC and coordinate with its quantization step. By reasonably setting the value of the initial digital signal, the test circuit can generate a test signal corresponding to the input range of the ADC, and the integrity and the effectiveness of the test are ensured. Second, the supply voltage of the DAC determines the range of the amplitude of its output signal. The value of the initial digital signal needs to take into account the supply voltage of the DAC to ensure that the generated test signal is within the output range of the DAC, avoiding signal distortion or clipping. By matching the value of the initial digital signal with the supply voltage of the DAC, the test circuit can generate a test signal with proper amplitude and excellent quality, and reliable input is provided for the evaluation of ADC performance.

In addition, the input voltage range of the ADC under test is also an important basis for determining the initial digital signal value. The voltage range of the test signal needs to be matched with the input range of the ADC, so that the whole input range is covered, and overload of the input of the ADC caused by exceeding the range is avoided. By comprehensively considering the input voltage range of the ADC and correspondingly setting the value of the initial digital signal, the test circuit can generate a test signal which has proper voltage range and is matched with the input of the ADC, thereby ensuring the accuracy and reliability of the test.

In the actual test process, the control bus terminal calculates and generates an optimal value of the initial digital signal according to the parameters and characteristics of the tested ADC. These values are required to meet both the accuracy and applicability requirements of the test signal and to be compatible with both the test efficiency and the resource utilization.

On the basis of the above embodiment, as an optional embodiment, the control comparison module includes a control signal generating unit, a data comparing unit and a logic judging unit, where the control signal generating unit is electrically connected with the data comparing unit and the logic judging unit in sequence;

Specifically, in the high-precision successive approximation type ADC test circuit, the control comparison module plays a vital role. The device comprises a control signal generating unit, a data comparing unit and a logic judging unit, and realizes accurate control and dynamic adjustment of the test process through the cooperative work of the units.

First, the control signal generation unit determines the input digital quantity DB from the digital signal. The step converts the initial digital signal generated by the control bus terminal into the working digital quantity in the control comparison module, and provides a basis for subsequent comparison and judgment. The control signal generating unit realizes signal connection and matching among all modules of the test circuit through processing and converting the input digital signals, and ensures the accuracy and consistency of signal transmission. Next, the control signal generating unit also generates an output digital quantity DA according to the data output from the ADC under test. The process converts the actual output code value of the ADC into a digital quantity form which can be processed by a control comparison module, and provides a basis for subsequent comparison and judgment. The output data of the ADC is obtained and converted in real time, the control signal generating unit realizes dynamic tracking and feedback of the actual conversion result of the ADC, and data support is provided for real-time adjustment and optimization of the test process.

The data comparison unit compares the preset digital quantity B with the input digital quantity DB and the output digital quantity DA respectively to obtain an initial comparison result and an adjustment comparison result. The preset digital quantity B represents an ideal code value expected by the ADC output by the test circuit, and the data comparison unit can evaluate the conversion performance of the ADC in real time by comparing the ideal code value with the actual input digital quantity and the actual output digital quantity so as to judge whether the conversion performance meets the expectation. The initial comparison result reflects whether the setting of the test signal is reasonable or not, and the adjustment comparison result reflects the difference between the actual output and the ideal output of the ADC, so that a basis is provided for subsequent control and adjustment.

And finally, the logic judging unit generates a corresponding control signal to the power supply module according to the initial comparison result or the adjustment comparison result. When the initial comparison result shows that the test signal is reasonably set, the logic judging unit generates a control signal corresponding to the test signal, and instructs the power supply module to charge and discharge the integrator module according to a preset scheme, so that stable output of the test signal is maintained. When the adjustment comparison result shows that the ADC output is different from the expected value, the logic judgment unit generates an adjustment control signal to instruct the power supply module to correspondingly adjust the charging and discharging strategies, and the test signal is dynamically optimized, so that the conversion error is reduced, and the test precision is improved.

The control comparison module realizes accurate control and real-time adjustment of the test process through the cooperative work of the control signal generation unit, the data comparison unit and the logic judgment unit. The digital quantity conversion and processing of the signal generation unit are controlled, and the accuracy and consistency of signal transmission are ensured. The comparison and evaluation of the data comparison unit provides basis for the judgment and optimization of the test process. The control signals of the logic judging unit are generated, so that the effective control of the power supply module and the integrator module is realized, and the quality and stability of the test signals are ensured.

On the basis of the embodiment, as an alternative embodiment, the integrator module comprises an operational amplifier and an integrating capacitor;

In particular, in high-precision successive approximation ADC test circuits, the integrator module plays a key role. The integrated circuit mainly comprises an operational amplifier and an integrating capacitor, and realizes accurate integration of input current and stable output of integrated voltage through cooperation of the two core elements.

The integrating capacitor is connected with the operational amplifier in parallel to form a basic circuit structure of the integrator module. The parallel connection mode fully plays the amplifying function of the operational amplifier and the charge storage function of the integrating capacitor, and ensures the accuracy and stability of the integrating process.

During the test, the control comparison module outputs an initial control signal or a regulating control signal, which is transmitted to an operational amplifier in the integrator module through an electrical connection. The operational amplifier performs accurate integral operation on the input current according to the received control signal. Specifically, when the control signal indicates charging, the operational amplifier converts the input current into electric charge and stores it in the integrating capacitor. As the charging process proceeds, the voltage across the integrating capacitor increases continuously, forming an integrated voltage proportional to the integrated value.

Meanwhile, the high gain characteristic of the operational amplifier and the filtering effect of the integrating capacitor effectively inhibit noise and interference in the integrating process, and ensure the stability and accuracy of the integrated voltage. The capacitance of the integrating capacitor is carefully designed and optimized, so that the requirement of integrating precision is met, and the stability and response speed of the circuit are considered.

When the control signal indicates discharge, the operational amplifier releases the charge stored in the integrating capacitor, so that the integrating voltage is gradually reduced until the preset lower limit value is reached. By controlling the charge and discharge process, the integrator module realizes accurate adjustment and dynamic control of the integrated voltage, and provides stable and reliable input signals for subsequent signal conditioning and ADC conversion.

The output integral voltage of the integrator module is carefully conditioned and then transmitted to the input signal conditioning module. The conditioned analog input signal ADIN has good linearity, noise characteristics and dynamic range, can meet the input requirements of the ADC to be tested, and ensures the accuracy and reliability of the conversion result.

Based on the above embodiments, as an optional embodiment, the parameters of the measured ADC include a reference voltage Vref, a supply voltage VS, and an input voltage range Vrange of the measured ADC, and the preset digital quantity B is determined according to the parameters of the measured ADC, where b≡ (VS/Vrange) ×2ζ≡n, n is the resolution of the measured ADC.

Specifically, the reference voltage Vref of the ADC under test is 2.5V, the supply voltage VS is 3.3V, the input voltage range Vrange is 2V, and the resolution N is 12 bits. According to a calculation formula of the preset digital quantity B, the following steps are obtained:

B ≈ (VS / Vrange) * 2^N= (3.3V / 2V) * 2^12= 1.65 * 4096= 6758.4

for ease of implementation, the preset number quantity B may be rounded to 6758.

In the test process, the control bus terminal firstly selects a key code value which is easy to introduce DNL error as a test code value according to the resolution of the tested ADC and the test requirement. For example, for a 12-bit ADC, 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, and the like may be selected as the test code value.

Then, the control bus terminal generates a corresponding initial digital signal according to the test code value and inputs the initial digital signal to the control comparison module. The control signal generating unit in the control comparison module receives the initial digital signal and converts it into the input digital quantity DB.

Next, the data comparing unit compares the preset digital quantity B (6758) with the input digital quantity DB. If DB is less than 6758, it indicates that the current input voltage has not reached the ideal switching threshold, and the integrator output voltage needs to continue to be increased. The control comparison module outputs an initial control signal to trigger the power supply module to charge the integrator module, so that the output voltage of the integrator module is continuously increased.

When the output voltage of the integrator module passes through the input signal conditioning module, the generated analog input signal ADIN is input to the tested ADC and converted into a digital code value. The control comparison module reads the digital code value output by the ADC and converts the digital code value into an output digital quantity DA.

The data comparison unit compares the preset digital quantity B (6758) with the output digital quantity DA. If DA is equal to or greater than 6758, this indicates that the current output code value has reached or exceeded the expected value, and the integrator output voltage needs to be maintained or reduced. The control comparison module outputs an adjusting control signal to trigger the power supply module to discharge or maintain the integrator module, so that the output voltage of the integrator module is stabilized at a proper level.

In this way, the test circuit can accurately control the input voltage of the tested ADC at the key code value and acquire the actual output code value thereof. And comparing the voltage corresponding to the actual output code value with the ideal output voltage to obtain a voltage error, and calculating the difference between the voltage errors at adjacent code values to obtain the DNL error.

For example, assume that at a test code value of 1024, the actual output code value of the ADC under test is 1023, the corresponding actual conversion voltage is 1.998V, and the ideal output voltage is 2.000V. The voltage error is 1.998V-2.000V = -0.002V. And assuming that when the test code value is 1023, the actual output code value is 1022, the corresponding actual conversion voltage is 1.996V, the ideal output voltage is 1.998V, and the voltage error is 1.996V-1.998 V= -0.002V. The DNL error is (-0.002V) - (-0.002V) =0, indicating that no DNL error occurs at code value 1024.

By selecting more test code values and repeating the test process, DNL error distribution conditions of the tested ADC at different code values can be obtained. Dividing DNL errors into different intervals according to the sizes, counting the occurrence frequency of each interval, drawing a DNL error distribution histogram, and intuitively evaluating the nonlinear error characteristics of the ADC.

On the other hand, the application also provides a testing method of the high-precision successive approximation type ADC testing circuit, referring to fig. 2 specifically, fig. 2 is a flow chart of a testing method of the high-precision successive approximation type ADC testing circuit provided by the embodiment of the application, and the method comprises the following steps:

S101, selecting a group of representative test code values according to the resolution and the test requirement of the ADC to be tested;

Specifically, the resolution of the ADC under test determines the number of bits and the number of quantization levels of its digital output code. For example, an 8-bit ADC has an output code range of 0255 for a total of 256 quantization levels. And the output code range of a 10-bit ADC is 01023, and 1024 quantization levels are used. The higher the resolution, the more the number of output code bits of the ADC, the larger the number of quantization levels, and correspondingly, the more complex the testing and evaluation of its nonlinear errors. Thus, depending on the resolution of the ADC under test, the selection range and number level of test code values can be initially determined.

In addition to resolution considerations, the test code values need to be selected according to specific test requirements. Different applications and performance indexes have different concerns and evaluation criteria for the nonlinear error characteristics of the ADC. For example, in the field of high precision measurement, strict requirements are placed on Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) errors of an ADC, and it is necessary to focus on testing and evaluating the nonlinear error distribution of the ADC over the full range. In the field of high-speed data conversion, dynamic performance indexes of the ADC such as signal-to-noise ratio (SNR) and Total Harmonic Distortion (THD) are more concerned, and test code values capable of reflecting the indexes need to be selected.

In the actual selection of test code values, a hierarchical sampling method is generally adopted, and a certain number of representative code values are uniformly selected from the whole input code range of the ADC. These code values should cover critical conversion points and sensitive intervals of the ADC, such as zero, full scale points, intermediate points, etc., as well as critical code values that are prone to introducing non-linear errors. Meanwhile, in order to comprehensively evaluate the nonlinear characteristics of the ADC, enough sample points are selected in different code value intervals so as to ensure the statistical significance and reliability of the test result.

S102, generating a corresponding initial digital signal according to the test code value, and sequentially inputting the initial digital signal into the high-precision successive approximation type ADC test circuit to obtain an initial measurement voltage;

In the implementation, the corresponding initial digital signal is first generated according to the selected test code value. These initial digital signals are typically in binary coded form, matching the input code format of the ADC under test. For example, for an 8-bit ADC, the initial digital signal with a test pattern value of 0xFF (binary 11111111) is 8 high pulses. The desired initial digital signal sequence may be conveniently generated by a digital signal generator or a programmable logic device.

After the initial digital signal is generated, the initial digital signal is required to be sequentially input into a high-precision successive approximation type ADC test circuit for measurement. The high-precision successive approximation type ADC test circuit is a high-precision digital-to-analog conversion device special for ADC performance test and evaluation, and the core of the high-precision successive approximation type ADC test circuit is a high-resolution Successive Approximation Register (SAR) ADC. Through a successive approximation algorithm, the high-precision successive approximation type ADC test circuit can convert an initial digital signal into a high-precision analog voltage corresponding to the initial digital signal, namely an initial measurement voltage. The accuracy of this measured voltage is typically much higher than the resolution of the ADC under test, which can meet the requirements of DNL error and INL error testing.

In the measuring process, the high-precision successive approximation type ADC test circuit can sample and convert each initial digital signal for a plurality of times, and average and filter the conversion result so as to improve the measuring precision and stability. Meanwhile, in order to eliminate errors and nonlinear effects of the test circuit, self calibration and error compensation are also required for the high-precision successive approximation type ADC test circuit. Through a series of calibration and optimization measures, the accuracy and reliability of the initial measurement voltage can be ensured, and a high-quality data base is provided for subsequent error calculation.

By measuring the initial digital signal using the high-precision successive approximation type ADC test circuit, a high-precision analog voltage value corresponding to the input code value of the ADC to be measured, i.e., an initial measurement voltage, can be obtained. The initial measurement voltage data are complete and accurate, and the actual output characteristics of the measured ADC under different input code values can be truly reflected. Based on the initial measurement voltage, key performance indexes such as DNL error and INL error of the ADC can be conveniently calculated, and nonlinear characteristics of the ADC can be intuitively displayed in the form of an error distribution histogram and the like. The accuracy and reliability of the initial measurement voltage directly determine the accuracy and reliability of the ADC performance evaluation, and are the data base of the whole test scheme.

Some terms in the above are explained below:

1. Successive Approximation Register (SAR) ADC SAR ADC is a common ADC architecture, and analog-to-digital conversion is realized by successive comparison and approximation. The binary search algorithm is used, and the digital equivalent value of the analog input signal is continuously approximated through multiple comparison and adjustment, so that high-precision digital-to-analog conversion is realized.

2. Self-calibration refers to the process of detecting and compensating errors and nonlinearity of the ADC in real time in the working process. Through a built-in self-calibration circuit and algorithm, the ADC can dynamically adjust the quantization level and the comparison threshold value, thereby minimizing conversion errors and improving measurement accuracy.

3. Error compensation, namely, in the digital output result of the ADC, correcting and calibrating the conversion result according to the known error model and calibration data. The error compensation algorithm realized by software or hardware can effectively eliminate the systematic error and nonlinear distortion of the ADC and improve the measurement accuracy and dynamic performance of the ADC.

4. Quantization level-quantization level refers to the minimum amount of analog signal variation that an ADC can resolve within its input range. It is determined by the resolution of the ADC and the reference voltage. The size of the quantization level reflects the sensitivity and resolution capabilities of the ADC. The smaller the quantization level, the higher the resolution of the ADC and the finer the description of the analog signal.

5. The comparison threshold refers to the voltage limit used by the ADC when comparing the analog signal to the digital code value. The ADC outputs a corresponding high level when the voltage of the analog input signal is greater than the comparison threshold, and outputs a corresponding low level when the voltage of the analog input signal is less than the comparison threshold. The accuracy and stability of the comparison threshold directly affect the conversion accuracy and linearity of the ADC.

S103, determining DNL errors according to the initial measurement voltage, and evaluating the tested ADC according to the DNL errors to obtain an evaluation result.

Specifically, after initial measurement voltage data is obtained, the high-precision successive approximation type ADC test method enters a critical error calculation and performance evaluation stage. According to the initial measurement voltage, through a series of calculation and analysis steps, the Differential Nonlinearity (DNL) error of the ADC to be measured can be accurately determined, and the ADC is comprehensively evaluated according to the DNL error to obtain a final evaluation result. The method aims at deeply analyzing the nonlinear characteristics of the ADC, quantitatively evaluating the dynamic performance of the ADC, and providing objective and reliable basis for design optimization and application type selection of the ADC.

First, the DNL error needs to be determined from the initial measurement voltage. The DNL error reflects the degree of nonlinearity of the ADC when adjacent code values are converted, and is an important indicator for evaluating the dynamic performance of the ADC. To calculate the DNL error, the initial measured voltage needs to be compared with the ideal conversion characteristics. The ideal conversion characteristic refers to a linear correspondence between the output code value of the ADC and the input analog signal in an ideal case. By subtracting the ideal output voltage of the corresponding code value from the initial measured voltage, the voltage error at each test code value can be obtained. Then, the voltage errors of the two adjacent test code values are subtracted to obtain corresponding DNL error values. The differential operation method can effectively eliminate the systematic error and offset of the measuring circuit and improve the accuracy of DNL error calculation.

After calculating the DNL errors for all test pattern values, a statistical analysis of these error data is required to fully evaluate the nonlinear characteristics of the ADC. One common analysis method is to draw a DNL error distribution histogram. The DNL error is divided into a plurality of intervals according to the numerical value, and the error times in each interval are counted, so that the performance of the ADC under different nonlinear levels can be intuitively displayed. Ideally, the DNL error should be concentrated around a zero value, exhibiting a morphology resembling a normal distribution. If the DNL error distribution is significantly shifted, stretched or multimodal, it is indicated that there is significant nonlinear distortion of the ADC and its dynamic performance may be affected.

Based on the DNL error distribution histogram, the nonlinear characteristics of the ADC can be further quantitatively evaluated. The nonlinear degree and the dynamic range of the ADC can be comprehensively measured by calculating the statistical parameters such as the mean value, the variance, the maximum value, the minimum value and the like of the DNL error. Meanwhile, the qualification threshold or the rating standard of DNL errors can be set according to specific application requirements and performance indexes, and the ADC can be subjected to grading evaluation and screening. For example, for high precision measurement applications, it may be required that the absolute value of the DNL error does not exceed 0.5 LSB (least significant bit), while for high speed data conversion applications, the DNL error may be allowed to float within ±1 LSB. By quantitatively analyzing and evaluating DNL errors, whether the dynamic performance of the ADC meets the requirements of specific applications can be objectively and accurately judged.

Through the series of error calculation, statistical analysis and performance evaluation steps, the comprehensive evaluation result of the nonlinear characteristics of the tested ADC can be obtained. These evaluation results can reflect not only the dynamic performance level of the ADC, but also the source and influencing factors of its nonlinear distortion. For ADC designers, the evaluation result can guide the ADC designers to optimize circuit design, improve device technology and improve conversion precision and speed. For ADC users, the evaluation result can help the ADC users select proper device models, determine the optimal working conditions and evaluate the performance margin and the reliability of the system.

The above are merely exemplary embodiments of the present disclosure and are not intended to limit the scope of the present disclosure. That is, equivalent changes and modifications are contemplated by the teachings of this disclosure, which fall within the scope of the present disclosure. Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure.

This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a scope and spirit of the disclosure being indicated by the claims.

Claims

1. The high-precision successive approximation type ADC test circuit is characterized by comprising a control bus end, a control comparison module, an integrator module, a power supply module and an input signal conditioning module;

The integrator module is used for integrating the input current according to the initial control signal or the adjustment control signal output by the control comparison module to obtain an integrated value and outputting an integrated voltage proportional to the integrated value;

2. The test circuit of claim 1, wherein the value of the initial digital signal is related to a reference voltage of the ADC under test, a supply voltage of a DAC, and an input voltage range of the ADC under test.

3. The test circuit according to claim 1, wherein the control comparison module comprises a control signal generation unit, a data comparison unit and a logic judgment unit, wherein the control signal generation unit is electrically connected with the data comparison unit and the logic judgment unit in sequence;

4. The test circuit of claim 1, wherein the integrator module comprises an operational amplifier and an integrating capacitor;

5. The test circuit of claim 1, wherein the input signal conditioning module comprises an adder and a differential amplifier;

6. The test circuit of claim 1, wherein the parameters of the ADC under test include a reference voltage Vref, a supply voltage VS, and an input voltage range Vrange of the ADC under test, and wherein the predetermined digital quantity B is determined based on the parameters of the ADC under test, wherein B+ (VS/Vrange) x2≡N, N is the resolution of the ADC under test.

7. A high-precision successive approximation ADC test method applied to the high-precision successive approximation ADC test circuit according to any one of claims 1 to 6, comprising:

8. The test method of claim 7, wherein the test pattern value is a critical transition point that is prone to introducing DNL errors.

9. The method of testing of claim 7, wherein said determining DNL errors from said initial measured voltage comprises:

And subtracting the initial measurement voltage from the ideal output voltage of the corresponding code value to obtain a corresponding voltage error, and subtracting the voltage errors corresponding to the two adjacent test code values to obtain the DNL error.

10. The test method according to claim 7, wherein the evaluating the ADC under test according to the DNL error to obtain an evaluation result comprises:

drawing a DNL error distribution histogram of the measured ADC according to the DNL error, and determining the frequency distribution of the DNL error in different cells according to the DNL error distribution histogram;

and obtaining the evaluation result according to the frequency distribution of the DNL errors among different cells.