CN118566703B - System and method for monitoring metastable state in real time and dynamically correcting metastable state - Google Patents
System and method for monitoring metastable state in real time and dynamically correcting metastable state Download PDFInfo
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Abstract
The invention discloses a metastable state real-time monitoring and dynamic correcting system and a method, which relate to the technical field of chip design, wherein two data ends working in different clock domains are subjected to data interaction at an asynchronous interface, the data ends comprise a source register and a destination register, an edge detection circuit is used for detecting clock phase differences between the source register and the destination register, whether the acquired clock phase differences are in a dangerous range of the metastable state of a circuit of the asynchronous interface or not is monitored in real time, if yes, a data path is started, a data path phase gear is selected, if not, no operation is performed on the circuit of the asynchronous interface in the dangerous range of the metastable state, the data phase adjustment is continued after the data path phase gear is selected, and then the dynamic correction of the circuit is finished finally.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a system and a method for monitoring metastable state in real time and dynamically correcting the metastable state.
Background
The SOC chip has a plurality of asynchronous interfaces, wherein the asynchronous interfaces refer to two modules working at different clock frequencies, the asynchronous interfaces refer to the places where the two modules working at different frequencies perform data interaction, a circuit is easy to generate metastable state phenomenon at the asynchronous interfaces, the data interaction mode of the asynchronous interfaces is performed between registers, the two registers are respectively sourced from the two modules with different working frequencies, a data sending party is called a source register, and a data receiving party is called a destination register.
When the jump of the data end of the destination register at the interface is just in a metastable state window, the circuit can generate metastable state, the metastable state can be spread, the whole system is possibly paralyzed, and aiming at the asynchronous interface, how to monitor the clock phase difference of the source register and the destination register in real time, further, measures for avoiding the jump of the data in the metastable state window are adopted, so that the circuit becomes more stable and reliable, and the problem to be solved is urgent in the current chip design field.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a system and a method for monitoring and dynamically correcting metastable states in real time.
The aim of the invention can be achieved by the following technical scheme: a method for real-time monitoring and dynamic correction of metastability, comprising the steps of:
Step S1: performing data interaction on two data ends working in different clock domains at an asynchronous interface, wherein the data ends comprise a source register and a destination register, and clock phase differences between the source register and the destination register are detected through an edge detection circuit;
Step S2: monitoring whether the acquired clock phase difference is in a dangerous range of metastable state of a circuit of an asynchronous interface in real time, if so, starting a data path, selecting a data path phase gear, and if not, not performing any operation;
step S3: and selecting a data path phase gear for the circuit of the asynchronous interface in the dangerous range of metastable state, and continuing to perform data phase adjustment so as to finish the final dynamic correction of the circuit delay.
Further, the process of data interaction between two data terminals operating in different clock domains at an asynchronous interface includes:
The Clock domains corresponding to the two data ends comprise clock_domain_0 and clock_domain_1, the data end with the Clock domain of clock_domain_0 is used as a data transmitting end for data interaction, and the data end with the Clock domain of clock_domain_1 is used as a data receiving end for data interaction;
the data end serving as a data sending end corresponds to a source register, the data end serving as a data receiving end corresponds to a destination register, the phase of the source register corresponding to a clock is obtained and is recorded as CLK0, the phase of the destination register corresponding to the clock is obtained and is recorded as CLK1, and the interaction position of the two data ends, where data interaction occurs, is an asynchronous interface.
Further, the process of detecting the clock phase difference between the source register and the destination register by the edge detection circuit includes:
The edge detection circuit comprises an edge trigger 0 and an edge trigger 1, wherein the edge trigger 1 is used for detecting a clock corresponding to a destination register, the edge trigger 0 is used for detecting a clock corresponding to a source register, the phase of the clock corresponding to the destination register and the phase of the clock corresponding to the source register are detected through the edge detection circuit, and the clock phase difference between the source register and the destination register is obtained according to the phases CLK0 and CLK 1;
the clock phase difference between the source register and the destination register is recorded as t0, wherein the t0 = CLK 0-CLK 1, the value of t0 comprises a positive value and a negative value, when the clock of the edge trigger 1 corresponding to the destination register is later than the clock of the edge trigger 0 corresponding to the source register, the clock phase difference t0 is taken as the positive value, and when the clock of the edge trigger 0 corresponding to the source register is later than the clock of the edge trigger 1 corresponding to the source register, the clock phase difference t0 is taken as the negative value;
Defining a metastable state area of a corresponding circuit of the asynchronous interface, wherein the metastable state area comprises Tsu and Tu, tsu in the metastable state area indicates that data of a data end are in a window which is stable and unchanged before a clock of a data end corresponding to a target register arrives, D1 before a rising edge of a clock corresponding to CLK1 needs to be unchanged, tu in the metastable state area indicates that data of the data end are in a window which is stable and unchanged after the clock of the data end corresponding to the target register arrives, D1 after the rising edge of the clock corresponding to CLK1 needs to be unchanged, wherein a source register outputs Q0 after the rising edge of the clock CLK0 triggers, and D1 is a waveform of the Q0 reaching the data end of the target register after passing through a data path.
Further, when the edge detection circuit collects clock phase differences between the source register and the destination register, a clock is set to the edge detection circuit, and the clock meets the following requirements: the clock corresponding to the current edge detection circuit is larger than the clock with larger frequency in the source register and the destination register, the clock of the edge detection circuit is set to be twice the clock with larger frequency in the source register and the destination register, after the clock corresponding to the edge detection circuit is set, the edge detection circuit carries out edge sampling on the clocks of the destination register and the source register, the type of the edge sampling comprises rising edge sampling and falling edge sampling, and rising edge sampling and falling edge sampling are carried out on the two clocks at the same time.
Further, the process of monitoring whether the acquired clock phase difference is in a dangerous range of metastable state of the circuit of the asynchronous interface in real time includes:
setting the delay of the whole data path to be Td, and jumping when D1 is in the metastable state area of the clock sampling of the destination register, so that the corresponding circuit at the asynchronous interface is metastable, wherein the formula is as follows: when Td-T0 < Th, or T0-Td+T < Tsu, where T is the period of the destination register, td-T0 is negative, and T0-Td+T can be negative, where Td-T0 < Th and T0-Td+T < Tsu are the dangerous ranges where the clock phase difference is in the metastable state of the asynchronous interface circuit;
When the obtained clock phase difference is monitored in real time and is in the dangerous range of the metastable state of the circuit of the asynchronous interface, the data path of the circuit is started, the phase shift of the data path is selected, and when the obtained clock phase difference is monitored in real time and is not in the dangerous range of the metastable state of the circuit of the asynchronous interface, no operation is carried out.
Further, the process of enabling the data path and selecting the data path phase shift comprises:
Judging whether delay requirements for enabling a data path exist according to Td-T0 < Th or T0-Td+T < Tsu, marking Td-T0 < Th as a judgment formula I, and marking T0-Td+T < Tsu as a judgment formula II;
When the judgment formula I is met, the operation of increasing the Td is performed, the value of the Td is ensured to not meet the judgment formula II while the Td is increased, and when the judgment formula II is met, the operation of reducing the Td is performed, and the value of the Td is ensured to not meet the judgment formula I while the Td is reduced;
and changing Td through the first judgment formula and the second judgment formula, further enabling the data path, and selecting the phase shift of the data path, wherein the selection of the phase shift of the data path is a circuit with n being 1.
Further, for the circuit of the asynchronous interface in the dangerous range of the metastable state, the data phase adjustment is continued after the data path phase gear is selected, and the process of dynamically correcting the circuit delay finally comprises the following steps:
When the circuit of the asynchronous interface is in a dangerous range with metastable state, selecting a phase gear of a corresponding data path of the circuit, dividing the phase gear of the data path into 8 gears, wherein each gear corresponds to 1/4 clock period of a corresponding clock of a destination register, the phase gear of the lowest gear is 1/4 clock period, and the phase gear of the highest gear is 2 clock periods;
The respective periods from the 2 nd phase gear to the 7 th phase gear in the middle are respectively: 1/2, 3/4, 1, 5/4, 3/2 and 7/4 clock cycles corresponding to the destination registers, the lowest gear 1/4 clock cycles being set directly, the highest gear being set based on the maximum difference between the source register and the destination register cycles;
and after the data path selects the corresponding path phase gear, executing data phase adjustment on the asynchronous interface circuit with the metastable state phenomenon through the selected path phase gear, and further completing the final dynamic correction on the circuit delay of the asynchronous interface corresponding circuit.
Further, a system for real-time monitoring and dynamic correction of metastability, the system comprising:
The clock phase difference detection module is used for carrying out data interaction on two data ends working in different clock domains at an asynchronous interface, wherein the data ends comprise a source register and a destination register, and the clock phase difference between the source register and the destination register is detected through the edge detection circuit;
the circuit metastable state monitoring module is used for monitoring whether the acquired clock phase difference is in a dangerous range of metastable state of a circuit of the asynchronous interface in real time, if so, starting a data path, selecting a data path phase gear, and if not, not performing any operation;
And the dynamic correction module is used for continuously carrying out data phase adjustment on the circuit of the asynchronous interface in the dangerous range of metastable state, after selecting the phase gear of the data path, and further completing the final dynamic correction on the circuit delay.
Compared with the prior art, the invention has the beneficial effects that: the data end comprises a source register and a destination register, the edge detection circuit is used for detecting the clock phase difference between the source register and the destination register, and monitoring whether the acquired clock phase difference is in the dangerous range of the metastable state of a circuit of the asynchronous interface or not in real time, and the circuit of the asynchronous interface in the dangerous range of the metastable state is continuously subjected to data phase adjustment after the data path phase gear is selected, so that the dynamic correction of circuit delay is finally completed, the traditional mode of adding circuit delay on a clock is abandoned, the delay is added on the data path, the clock phase difference of the source register and the destination register is monitored in real time, and measures for avoiding jump of data in a metastable state window are timely taken, so that the circuit becomes more stable and reliable.
Drawings
FIG. 1 is a flow chart of the present invention.
Detailed Description
As shown in fig. 1, a method for monitoring and dynamically correcting metastable state in real time comprises the following steps:
Step S1: performing data interaction on two data ends working in different clock domains at an asynchronous interface, wherein the data ends comprise a source register and a destination register, and clock phase differences between the source register and the destination register are detected through an edge detection circuit;
Step S2: monitoring whether the acquired clock phase difference is in a dangerous range of metastable state of a circuit of an asynchronous interface in real time, if so, starting a data path, selecting a data path phase gear, and if not, not performing any operation;
step S3: and selecting a data path phase gear for the circuit of the asynchronous interface in the dangerous range of metastable state, and continuing to perform data phase adjustment so as to finish the final dynamic correction of the circuit delay.
It should be further noted that, in a specific implementation process, a process of performing data interaction at an asynchronous interface by using two data terminals operating in different clock domains includes:
And respectively marking the Clock domains corresponding to the two data ends as clock_domain_0 and clock_domain_1, wherein the data end with the Clock domain of clock_domain_0 is used as a data transmitting end for data interaction, and the data end with the Clock domain of clock_domain_1 is used as a data receiving end for data interaction.
The data end serving as a data sending end corresponds to a source register, the data end serving as a data receiving end corresponds to a destination register, the phase of the source register corresponding to a clock is obtained and is recorded as CLK0, the phase of the destination register corresponding to the clock is obtained and is recorded as CLK1, and the interaction position of the two data ends, where data interaction occurs, is an asynchronous interface.
It should be further noted that, in a specific implementation, the process of detecting the clock phase difference between the source register and the destination register by the edge detection circuit includes:
The edge detection circuit comprises an edge trigger 0 and an edge trigger 1, wherein the edge trigger 1 is used for detecting a clock corresponding to a destination register, the edge trigger 0 is used for detecting a clock corresponding to a source register, the phase of the clock corresponding to the destination register and the phase of the clock corresponding to the source register are detected through the edge detection circuit, and then the clock phase difference between the source register and the destination register is obtained according to the phase of the clock phase difference.
The clock phase difference between the source register and the destination register is recorded as t0, namely t0=clk0-CLK 1, the value of t0 can be positive or negative, when the clock of the edge trigger 1 corresponding to the destination register is later than the clock of the edge trigger 0 corresponding to the source register, the clock phase difference t0 is positive, and when the clock of the edge trigger 0 corresponding to the source register is later than the clock of the edge trigger 1 corresponding to the source register, the clock phase difference t0 is negative.
When the edge detection circuit collects clock phase differences between the source register and the destination register, a clock is set for the edge detection circuit, and the clock meets the following requirements: the clock corresponding to the current edge detection circuit needs to be larger than the clock with larger frequency in the source register and the destination register, the clock of the edge detection circuit is generally set to be twice the clock with larger frequency in the source register and the destination register, after the clock corresponding to the edge detection circuit is set, the edge detection circuit carries out edge sampling on the clock of the destination register and the clock of the source register, the type of the edge sampling comprises rising edge sampling and falling edge sampling, and rising edge sampling and falling edge sampling are carried out on the two clocks at the same time.
Defining a metastable state area of a circuit corresponding to the asynchronous interface when two data ends perform data interaction on the asynchronous interface, wherein the metastable state area comprises Tsu and Tu, the Tsu in the metastable state area represents a window in which data of the data end is stable and unchanged before a clock of the data end corresponding to a target register arrives, namely D1 needs to be kept unchanged before a rising edge of a clock of CLK1, the Tu in the metastable state area represents a window in which the data of the data end is stable and unchanged after the clock of the data end corresponding to the target register arrives, namely D1 needs to be kept unchanged after the rising edge of the clock of CLK1, wherein a source register outputs Q0 after the rising edge of the clock of CLK0 is triggered, and D1 is a waveform of the Q0 reaching the data end of the target register after passing through one data path.
It should be further noted that, in a specific implementation process, the process of monitoring whether the acquired clock phase difference is in a dangerous range of metastable state of the circuit of the asynchronous interface in real time includes:
setting the delay of the whole data path as Td, and when D1 just jumps in the metastable state area of the clock sampling of the destination register, generating metastable state in the circuit corresponding to the asynchronous interface;
The method is characterized in that metastable states can occur by a formula when Td-T0 < Th or T0-Td+T < Tsu, T is the period of a target register, registers of a digital circuit are standard units in a process library, th and Tsu parameter values of the standard register units are related to a manufacturing process, a process factory gives the two values when the digital circuit is used, the two combined regions are metastable state regions of the registers, td-T0 can be negative numbers, T0-Td+T can be negative numbers, and the metastable states can occur, wherein Td-T0 < Th and T0-Td+T < Tsu are the dangerous ranges of the metastable states of circuits with clock phase differences in asynchronous interfaces;
When the obtained clock phase difference is monitored in real time and is in the dangerous range of the metastable state of the circuit of the asynchronous interface, the data path of the circuit is started, the phase shift of the data path is selected, and when the obtained clock phase difference is monitored in real time and is not in the dangerous range of the metastable state of the circuit of the asynchronous interface, no operation is carried out.
It should be further noted that, in a specific implementation, the process of enabling the data path and selecting the phase shift of the data path includes:
According to the phase of the two clocks, whether the delay requirement of enabling the data path exists or not is judged according to the formula Td-T0 < Th (judgment formula I) or T0-Td+T < Tsu (judgment formula II), and the clock of the destination register is 100M, namely T is 10ns, the delay Td of the data path is 7ns, and the phase difference of the two clocks is 8ns.
In the above equation, only the phase difference between two registers is a variable, the phase difference needs to be captured by detection, other values are known, and it is known through calculation that when the first judgment equation is satisfied, a metastable state is generated, the delay of Td needs to be increased, but when Td is increased, the second judgment equation is not necessarily satisfied, so that the range of Td increase is between [1ns,11ns-100ps ], the transmission efficiency of integrated circuit data is generally selected, the minimum value is added with a margin of 20%, but the minimum scalable scale is 1/4 clock period, and therefore, the delay gear to be increased is selected to be 10/4 and 2.5ns.
It is also possible that t0 is negative, when t0 is-3 ns, it will be apparent that decision equation two will be triggered, it will be apparent that Td at this time needs to be subtracted, and if metastable correction has been triggered before, it will be necessary to directly subtract the added delay to see if the circuit is satisfied, otherwise it will be necessary to add a greater delay to avoid being sampled at the current clock cycle, and it will be necessary to de-sample at the next clock sampling edge.
The data path phase gear selection is an n-selection 1 circuit, selects a proper path according to the phase difference result, and also comprises values of a plurality of readable registers, a current gear inquiry register, a plurality of state registers such as a metastable state trigger mark register and the like, wherein the state registers can be directly observed through an upper computer.
It should be further noted that, in a specific implementation process, for a circuit of an asynchronous interface in a dangerous range where metastable states occur, after selecting a data path phase shift, continuing to perform data phase adjustment, so as to complete a process of dynamically correcting a circuit delay finally, including:
when the circuit of the asynchronous interface is in a dangerous range of metastable state, the phase shift of the circuit corresponding to the data path is selected, the phase shift of the data path is divided into 8 shifts, each shift phase shift corresponds to 1/4 clock period of the corresponding clock of the destination register, wherein the phase shift of the lowest shift is 1/4 period, and the phase shift of the highest shift is 2 period.
The respective periods from the 2 nd phase gear to the 7 th phase gear in the middle are respectively: 1/2, 3/4, 1, 5/4, 3/2 and 7/4 of the destination registers are directly set to realize the 1/4 cycles of the lowest gear, and the highest gear is set based on the maximum difference between the cycles of the source register and the destination register, which should be noted that, in general, the frequency of the destination register is twice as high as that of the source register, and the highest gear of the delay is one cycle of the source register, namely, the clock cycles of the two destination registers.
And after the data path selects the corresponding path phase gear, executing data phase adjustment on the asynchronous interface circuit with the metastable state phenomenon through the selected path phase gear, and further completing the final dynamic correction on the circuit delay of the asynchronous interface corresponding circuit.
The invention also provides a system for monitoring and dynamically correcting the metastable state in real time, which comprises:
And the clock phase difference detection module is used for carrying out data interaction on two data ends working in different clock domains at an asynchronous interface, wherein the data ends comprise a source register and a destination register, and the clock phase difference between the source register and the destination register is detected through the edge detection circuit.
The circuit metastable state monitoring module is used for monitoring whether the acquired clock phase difference is in a dangerous range of metastable state of a circuit of the asynchronous interface in real time, if so, enabling a data path, selecting a data path phase gear, and if not, not performing any operation.
And the dynamic correction module is used for selecting the phase shift of the data path for the circuit of the asynchronous interface in the metastable dangerous range, and then continuing to carry out data phase adjustment so as to finish the final circuit delay.
The above embodiments are only for illustrating the technical method of the present invention and not for limiting the same, and it should be understood by those skilled in the art that the technical method of the present invention may be modified or substituted without departing from the spirit and scope of the technical method of the present invention.
Claims (4)
1. A method for real-time monitoring and dynamic correction of metastable state, comprising the steps of:
Step S1: performing data interaction on two data ends working in different clock domains at an asynchronous interface, wherein the data ends comprise a source register and a destination register, and clock phase differences between the source register and the destination register are detected through an edge detection circuit;
Step S2: monitoring whether the acquired clock phase difference is in a dangerous range of metastable state of a circuit of an asynchronous interface in real time, if so, starting a data path, selecting a data path phase gear, and if not, not performing any operation;
Step S3: for the circuit of the asynchronous interface in the dangerous range of the metastable state, the data phase adjustment is continued after the data path phase gear is selected, and then the dynamic correction of the circuit delay is finished;
The process of data interaction at an asynchronous interface between two data terminals operating in different clock domains comprises:
The Clock domains corresponding to the two data ends comprise clock_domain_0 and clock_domain_1, the data end with the Clock domain of clock_domain_0 is used as a data transmitting end for data interaction, and the data end with the Clock domain of clock_domain_1 is used as a data receiving end for data interaction;
The method comprises the steps that a data end serving as a data sending end corresponds to a source register, a data end serving as a data receiving end corresponds to a destination register, a phase of the source register under a corresponding clock is obtained, the phase is recorded as CLK0, the phase of the destination register under the corresponding clock is obtained, the phase is recorded as CLK1, and an interaction position of the two data ends, where data interaction occurs, is an asynchronous interface;
The process of detecting the clock phase difference between the source register and the destination register by the edge detection circuit includes:
The edge detection circuit comprises an edge trigger 0 and an edge trigger 1, wherein the edge trigger 1 is used for detecting a clock corresponding to a destination register, the edge trigger 0 is used for detecting a clock corresponding to a source register, the phase of the clock corresponding to the destination register and the phase of the clock corresponding to the source register are detected through the edge detection circuit, and the clock phase difference between the source register and the destination register is obtained according to the phases CLK0 and CLK 1;
the clock phase difference between the source register and the destination register is recorded as t0, wherein the t0 = CLK 0-CLK 1, the value of t0 comprises a positive value and a negative value, when the clock of the edge trigger 1 corresponding to the destination register is later than the clock of the edge trigger 0 corresponding to the source register, the clock phase difference t0 is taken as the positive value, and when the clock of the edge trigger 0 corresponding to the source register is later than the clock of the edge trigger 1 corresponding to the source register, the clock phase difference t0 is taken as the negative value;
Defining a metastable state area of a circuit corresponding to an asynchronous interface, wherein the metastable state area comprises Tsu and Th, tsu in the metastable state area indicates that data of a data end are in a window which is stable and unchanged before a clock of a data end corresponding to a target register arrives, D1 before a rising edge of a clock corresponding to CLK1 needs to be unchanged, th in the metastable state area indicates that the data of the data end are in a window which is stable and unchanged after the clock of the data end corresponding to the target register arrives, D1 after the rising edge of the clock corresponding to CLK1 needs to be unchanged, wherein a source register outputs Q0 after the rising edge of the clock CLK0 triggers, and D1 is a waveform of the Q0 reaching the data end of the target register after passing through a data path;
when the edge detection circuit collects clock phase differences between the source register and the destination register, a clock is arranged on the edge detection circuit, and the clock meets the following requirements: the clock corresponding to the current edge detection circuit is larger than the clock with larger frequency in the source register and the destination register, the clock of the edge detection circuit is set to be twice the clock with larger frequency in the source register and the destination register, after the clock corresponding to the edge detection circuit is set, the edge detection circuit carries out edge sampling on the clocks of the destination register and the source register, the type of the edge sampling comprises rising edge sampling and falling edge sampling, and rising edge sampling and falling edge sampling are carried out on the two clocks at the same time;
The process of monitoring whether the acquired clock phase difference is in a dangerous range of metastable state of a circuit of an asynchronous interface in real time comprises the following steps:
setting the delay of the whole data path to be Td, and jumping when D1 is in the metastable state area of the clock sampling of the destination register, so that the corresponding circuit at the asynchronous interface is metastable, wherein the formula is as follows: when Td-T0 < Th, or T0-Td+T < Tsu, wherein T is the period of the destination register, td-T0 is negative, and T0-Td+T is negative, where Td-T0 < Th and T0-Td+T < Tsu are the dangerous ranges of the clock phase difference in the metastable state of the asynchronous interface circuit;
When the obtained clock phase difference is monitored in real time and is in the dangerous range of the metastable state of the circuit of the asynchronous interface, the data path of the circuit is started, the phase shift of the data path is selected, and when the obtained clock phase difference is monitored in real time and is not in the dangerous range of the metastable state of the circuit of the asynchronous interface, no operation is carried out.
2. The method of claim 1, wherein enabling the data path and selecting the data path phase range comprises:
Judging whether delay requirements for enabling a data path exist according to Td-T0 < Th or T0-Td+T < Tsu, marking Td-T0 < Th as a judgment formula I, and marking T0-Td+T < Tsu as a judgment formula II;
When the judgment formula I is met, the operation of increasing the Td is performed, the value of the Td is ensured to not meet the judgment formula II while the Td is increased, and when the judgment formula II is met, the operation of reducing the Td is performed, and the value of the Td is ensured to not meet the judgment formula I while the Td is reduced;
and changing Td through the first judgment formula and the second judgment formula, further enabling the data path, and selecting the phase shift of the data path, wherein the selection of the phase shift of the data path is a circuit with n being 1.
3. The method of claim 2, wherein for the circuit of the asynchronous interface in the dangerous range of occurrence of metastable state, the data phase adjustment is continued after the data path phase gear is selected, and the process of dynamically correcting the delay of the circuit finally comprises the following steps:
When the circuit of the asynchronous interface is in a dangerous range with metastable state, selecting a phase gear of a corresponding data path of the circuit, dividing the phase gear of the data path into 8 gears, wherein each gear corresponds to 1/4 clock period of a corresponding clock of a destination register, the phase gear of the lowest gear is 1/4 clock period, and the phase gear of the highest gear is 2 clock periods;
The respective periods from the 2 nd phase gear to the 7 th phase gear in the middle are respectively: 1/2, 3/4, 1, 5/4, 3/2 and 7/4 clock cycles corresponding to the destination registers, the lowest gear 1/4 clock cycles being set directly, the highest gear being set based on the maximum difference between the source register and the destination register cycles;
and after the data path selects the corresponding path phase gear, executing data phase adjustment on the asynchronous interface circuit with the metastable state phenomenon through the selected path phase gear, and further completing the final dynamic correction on the circuit delay of the asynchronous interface corresponding circuit.
4. A system for real-time monitoring and dynamic correction of metastable states for implementing a method for real-time monitoring and dynamic correction of metastable states according to any one of claims 1 to 3, characterized in that it comprises:
The clock phase difference detection module is used for carrying out data interaction on two data ends working in different clock domains at an asynchronous interface, wherein the data ends comprise a source register and a destination register, and the clock phase difference between the source register and the destination register is detected through the edge detection circuit;
the circuit metastable state monitoring module is used for monitoring whether the acquired clock phase difference is in a dangerous range of metastable state of a circuit of the asynchronous interface in real time, if so, starting a data path, selecting a data path phase gear, and if not, not performing any operation;
And the dynamic correction module is used for continuously carrying out data phase adjustment on the circuit of the asynchronous interface in the dangerous range of metastable state, after selecting the phase gear of the data path, and further completing the final dynamic correction on the circuit delay.
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| CN104535918B (en) * | 2014-12-22 | 2017-03-15 | 中国民航大学 | A kind of cross clock domain lock unit internal constant test circuit and method |
| CN107220204B (en) * | 2016-03-21 | 2020-05-08 | 华为技术有限公司 | A data reading circuit |
| CN106201950B (en) * | 2016-07-08 | 2023-04-11 | 中南大学 | Method for SOC asynchronous clock domain signal interface |
| CN109116316B (en) * | 2018-09-10 | 2023-03-24 | 西安电子工程研究所 | Method for closed-loop detection of metastable state and correction |
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