CN118471979B - Metal oxide field effect power transistor based on BCD integration and process - Google Patents

Abstract

The invention relates to a metal oxide field effect power transistor based on BCD integration and a process thereof. The transistor comprises a substrate, wherein a deep groove isolation is arranged in the substrate to isolate the substrate into a high-voltage area and a low-voltage area, and the two sides of the low-voltage area are provided with the deep groove isolation; the substrate comprises a first metal lead-out layer, an N+ substrate layer and an N-epitaxial layer which are sequentially stacked from bottom to top along the vertical direction; the high-voltage region is internally provided with at least an SGT-NMOS main body, and the low-voltage region is internally provided with at least a PNP bipolar transistor main body and a low-voltage CMOS device main body; the first metal lead-out layer is also arranged on the back of the whole transistor in an extending way; the SGT-NMOS main body, the PNP bipolar transistor main body and the low-voltage CMOS device main body are all built in an N-epitaxial layer or on the N-epitaxial layer, and respectively form the SGT-NMOS, the PNP bipolar transistor and the low-voltage CMOS device with the substrate. Through the structural design of the high-voltage area and the low-voltage area, the SGT-NMOS, the PNP bipolar transistor and the low-voltage CMOS device are integrated, and the integration of the power management module and the driving power device is realized.

Description

A metal oxide field effect power transistor based on BCD integration and process

Technical Field

The invention relates to a metal oxide field effect power transistor, in particular to a metal oxide field effect power transistor based on BCD integration and a process.

Background Art

Currently in the field of power management circuits, whether it is AC/DC power management IC, LED driver IC, or high-voltage gate driver IC, all of them use power management modules and drive power devices to jointly realize functional requirements.

The power management module is manufactured using a low-voltage CMOS process, and the maximum operating voltage does not exceed 12V, while the power driver device is manufactured using a high-voltage process. For example, in AC/DC power management ICs and LED driver circuits, 700V DMOS tubes are widely used for power tubes. The voltage of the power driver tubes in DC-DC circuits belongs to the low-voltage DMOS category, generally in the range of 30-120V.

There are currently two integration methods: VDMOS and LDMOS. Regardless of whether it is a high-voltage DMOS device or a medium- and low-voltage DMOS device, if an integrated process is chosen, LDMOS devices are currently almost all used because LDMOS devices are easy to integrate in CMOS processes. However, LDMOS devices are arranged laterally, have a large area, low power density, and low integration.

The difference between VDMOS devices and LDMOS devices is that the drain of the VDMOS tube is directly led out from the back of the chip, the purpose of which is to reduce the on-resistance of the power tube. The current mainstream CMOS process uses a P-sub substrate, and the back needs to be connected to the common terminal (GND), which cannot directly realize VDMOS integration. When packaging the final product, a double wafer stage is required to place the power DMOS device and the low-voltage CMOS control circuit respectively. When the module using the sealing method is working, the power output tube is the device that generates the most concentrated heat, and the temperature detection circuit often uses a low-voltage CMOS process, which belongs to the power management category. Therefore, the temperature detection sensitivity is actually greatly discounted, and it often cannot play an over-temperature protection role in actual use. Therefore, the power management circuit developed using the sealing method often inevitably has a high probability of explosion and burning in actual use. At the same time, the double chip sealing technology increases the chip production cost in actual production.

In summary, since VDMOS uses vertical stacking and the back side needs to be connected to the highest potential, and the P substrate needs to be connected to GND, it cannot be integrated and has poor heat dissipation performance; LDMOS uses lateral integration, which has a large area, low power density, and low integration.

Summary of the invention

In order to solve the problems in the background technology, the present invention provides an integrated high-voltage buried gate trench metal oxide field effect power transistor and process. Through the structural design of the high-voltage region and the low-voltage region, the SGT-NMOS body, the PNP bipolar transistor body and the low-voltage CMOS device body are all constructed in the N-epitaxial layer or on the N-epitaxial layer, and the N-epitaxial layer of the low-voltage region has a first deep P-type well region as the common ground terminal of the low-voltage region, and the PNP bipolar transistor and the low-voltage CMOS device share the first deep P-type well region, integrating the high-voltage device with the low-voltage device to realize the integration of the power management module and the driving power device, with high integration and high power density; the integration of the high-voltage region and the low-voltage region enables the temperature detection circuit to accurately detect the temperature of the high and low voltage regions of the power transistor; the first metal lead-out layer is also extended to the back of the entire transistor to greatly improve the heat dissipation performance of the device.

The present application provides the following scheme: a metal oxide field effect power transistor based on BCD integration, comprising a substrate, wherein deep trench isolation is provided in the substrate to isolate the substrate into a high voltage region and a low voltage region, and deep trench isolation is provided on both sides of the low voltage region; the substrate comprises a first metal lead-out layer, an N+ substrate layer, and an N- epitaxial layer stacked in sequence from bottom to top along a vertical direction; the high voltage region has at least an SGT-NMOS body, and the low voltage region has at least a PNP bipolar transistor body and a low voltage CMOS device body;

The first metal lead-out layer is also extended to the back of the entire transistor; the SGT-NMOS body, the PNP bipolar transistor body and the low-voltage CMOS device body are all constructed in or on the N-epitaxial layer, and respectively form the SGT-NMOS, the PNP bipolar transistor and the low-voltage CMOS device with the substrate;

The N-epitaxial layer of the low-voltage region has a first deep P-type well region as a common ground terminal of the low-voltage region, and the PNP bipolar transistor and the low-voltage CMOS device share the first deep P-type well region;

The low voltage area also has a first P+ area, which is arranged between the PNP bipolar transistor and the low voltage CMOS device and is located in the first deep P-type well area. The PNP bipolar transistor is isolated from the first P+ area by a shallow trench, and the low voltage CMOS device is isolated from the first P+ area by a shallow trench. The first P+ area is used for grounding.

In the present application, the structures of the SGT-NMOS body, the PNP bipolar transistor body, and the low-voltage CMOS device body are all structures of ordinary SGT-NMOS, PNP bipolar transistor, and CMOS devices, which are common knowledge in the art.

Furthermore, the high voltage region also has SGT-PMOS, and the devices in the high voltage region are SGT-PMOS and SGT-NMOS in the horizontal direction, and the SGT-PMOS and the SGT-NMOS are isolated by a deep trench.

Furthermore, the low voltage region also has an NPN bipolar transistor, and the devices in the low voltage region are NPN bipolar transistor, PNP bipolar transistor and low voltage CMOS device in the horizontal direction, and the NPN bipolar transistor shares the first deep P-type well region with the PNP bipolar transistor and the low voltage CMOS device.

Further, the SGT-NMOS includes a first metal lead-out layer, an N+ substrate layer, and an N-epitaxial layer arranged in sequence from bottom to top, a deep groove is provided in the N-epitaxial layer, and the deep groove has an SGT-NMOS field plate polycrystalline layer and an SGT-NMOS control gate polycrystalline layer; a P-type body region, a first N+ region, and a second P+ region are symmetrically provided on both sides of the deep groove, the first N+ region and the second P+ region are adjacent and both are arranged on the P-type body region, and the first N+ region is close to the deep groove; a second metal lead-out layer is provided on the first N+ region and the second P+ region, and a source of the SGT-NMOS is formed by leading out through the second metal lead-out layer;

The PNP bipolar transistor comprises a first metal lead-out layer, an N+ substrate layer and an N-epitaxial layer arranged in sequence from bottom to top, a deep P-type well region as a common ground terminal of a low-voltage region is provided in the N-epitaxial layer, a first N-type well region and a third P+ region as a collector region of the PNP bipolar transistor are provided in the deep P-type well region, and the first N-type well region and the third P+ region are isolated by a shallow trench; the first N-type well region has a second N+ region as a first base region of the PNP bipolar transistor, a fourth P+ region as an emitter region of the PNP bipolar transistor and a third N+ region as a second base region of the PNP bipolar transistor, which are arranged in sequence in the first N-type well region; the third P+ region is led out through a third metal lead-out layer, the second N+ region is led out through a fourth metal lead-out layer, the fourth P+ region is led out through a fifth metal lead-out layer, and the third N+ region is led out through a sixth metal lead-out layer, to form a first collector, a first base, a first emitter and a second base of the PNP bipolar transistor respectively;

The low-voltage PMOS device comprises a first metal lead-out layer, an N+ substrate layer, and an N-epitaxial layer which are sequentially arranged from bottom to top; a deep P-type well region as a common ground end of a low-voltage region is provided in the N-epitaxial layer; a second N-type well region is provided in the deep P-type well region; a fourth N+ region, a fifth P+ region, and a sixth P+ region are sequentially arranged in the second N-type well region; the fourth N+ region and the fifth P+ region are led out through a seventh metal lead-out layer; the sixth P+ region is led out through an eighth metal lead-out layer; a first gate oxide layer is provided on the second N-type well region between the fifth P+ region and the sixth P+ region; a PMOS control gate polycrystalline layer is provided on the first gate oxide layer; two PLDD regions are provided on both sides under the first gate oxide layer; the two PLDD regions are connected to the fifth P+ region and the sixth P+ region, respectively;

The low-voltage NMOS device comprises a first metal lead-out layer, an N+ substrate layer, and an N-epitaxial layer which are sequentially arranged from bottom to top; a deep P-type well region as a common ground end of a low-voltage region is provided in the N-epitaxial layer; a third N-type well region is provided in the deep P-type well region; a P-type well region is provided in the third N-type well region; a fifth N+ region, a sixth N+ region, and a seventh P+ region are sequentially arranged in the P-type well region; the fifth N+ region is led out through a ninth metal lead-out layer; the sixth N+ region and the seventh P+ region are led out through a tenth metal lead-out layer; a second gate oxide layer is provided on the fifth N+ region of the fourth N+ region; and an NMOS control gate polycrystalline layer is provided on the second gate oxide layer; two NLDD regions are provided on both sides under the second gate oxide layer; the two NLDD regions are respectively connected to the fifth N+ region and the sixth N+ region; a seventh N+ region is also provided in the third N-type well region; the seventh N+ region is isolated from the P-type well region through a shallow trench; and the seventh N+ region is led out through an eleventh metal lead-out layer.

In the present application, N+, N, and N- respectively represent the concentration of N-type doping, and P+ and P respectively represent the concentration of P-type doping, which are commonly used expressions in the art.

Furthermore, the SGT-PMOS includes a first metal lead-out layer, an N+ substrate layer, and an N-epitaxial layer which are sequentially arranged from bottom to top, the N-epitaxial layer has a second deep P-type well region, the second deep P-type well region has a deep trench, the deep trench has an SGT-PMOS field plate polycrystalline layer and an SGT-PMOS control gate polycrystalline layer; an N-type body region, an eighth N+ region, and an eighth P+ region are symmetrically arranged on both sides of the deep trench, the eighth N+ region and the eighth P+ region are adjacent and are both arranged on the N-type body region, and the eighth P+ region is close to the deep trench; a twelfth metal lead-out layer is provided on the eighth N+ region and the eighth P+ region, and the source of the SGT-PMOS is formed by leading out through the twelfth metal lead-out layer.

Furthermore, the second deep P-type well region of the SGT-PMOS also has a P-type enrichment region.

Further, the NPN bipolar transistor includes a first metal lead-out layer, an N+ substrate layer and an N-epitaxial layer which are arranged in sequence from bottom to top; a deep P-type well region as a common ground terminal of a low-voltage region is provided in the N-epitaxial layer; a fourth N-type well region and a ninth N+ region as a collector region of the NPN bipolar transistor are provided in the deep P-type well region; the fourth N-type well region has a ninth P+ region as a third base region of the NPN bipolar transistor, a tenth N+ region as an emitter region of the NPN bipolar transistor and a tenth P+ region as a fourth base region of the NPN bipolar transistor which are arranged in sequence; the ninth N+ region is led out through a thirteenth metal lead-out layer, the ninth P+ region is led out through a fourteenth metal lead-out layer, the tenth N+ region is led out through a fifteenth metal lead-out layer, and the tenth P+ region is led out through a sixteenth metal lead-out layer, to form a second collector, a third base, a second emitter and a fourth base of the NPN bipolar transistor respectively.

A process for preparing a metal oxide field effect power transistor based on BCD integration comprises the following steps:

(1) Growing an N- epitaxial layer on an N+ substrate;

(2) Setting a pattern mask on the N-epitaxial layer and performing ion implantation to produce a deep P-type well region;

(3) Setting a pattern mask, and forming a first N-type well region, a second N-type well region, and a third N-type well region in the deep P-type well region by ion implantation;

(4) Setting a pattern mask, and forming a P-type body region and a first P-type well region in the third N-type well region and the N-type epitaxial layer by ion implantation;

(5) Using a pattern mask, the deep trench of the SGT-NMOS, the deep trench between the high-voltage region and the low-voltage region, and the deep trench on the other side of the low-voltage region are produced;

(6) Thermally oxidize the deep trench, then deposit polysilicon, and selectively etch the polysilicon to produce the SGT-NMOS field plate polycrystalline layer and the field plate polycrystalline layers in other deep trenches;

(7) After thermal oxidation, polysilicon is deposited and selectively dry-etched to produce the SGT-NMOS control gate polycrystalline layer and the control gate polycrystalline layer in other deep trenches;

(8) through thermal oxidation, selective photomask, and etching methods, shallow trench isolation between the first N-type well region and the third P+ region, shallow trench isolation between the PNP bipolar transistor and the first P+ region, shallow trench isolation between the low-voltage CMOS device and the first P+ region, shallow trench isolation between the low-voltage PMOS device and the low-voltage NMOS device, and shallow trench isolation between the seventh N+ region and the P-type well region are manufactured;

(9) Producing a first gate oxide layer and a second gate oxide layer by a low temperature oxidation method;

(10) Depositing polysilicon, and using pattern masking and etching to produce a PMOS control gate polycrystalline layer and an NMOS control gate polycrystalline layer respectively;

(11) Pre-oxidizing the PMOS control gate polycrystalline layer and the NMOS control gate polycrystalline layer to produce an oxide layer;

(12) Forming NLDD and PLDD regions through LDD implantation;

(13) By using different material growth and etching techniques, self-aligned injection sidewall regions of low voltage PMOS devices and low voltage NMOS devices are manufactured; the different material growth and etching techniques are determined according to the materials used and are common knowledge in the art.

(14) Using a pattern mask, a first N+ region, a second N+ region, a third N+ region, a fourth N+ region, a fifth N+ region, a sixth N+ region, and a seventh N+ region are produced; and then using a pattern mask, a first P+ region, a second P+ region, a third P+ region, a fourth P+ region, a fifth P+ region, a sixth P+ region, and a seventh P+ region are produced;

(15) Produce a dielectric insulating layer, and produce a lead hole layer by pattern masking and etching;

(16) Fabricating a first metal lead layer, a second metal lead layer, a third metal lead layer, a fourth metal lead layer, a fifth metal lead layer, a sixth metal lead layer, a seventh metal lead layer, an eighth metal lead layer, a ninth metal lead layer, a tenth metal lead layer, and an eleventh metal lead layer.

Furthermore, the thickness of the N-epitaxial layer in step (1) is 4-10 um.

Furthermore, the doping concentration of the N-epitaxial layer in step (1) is 1e14 cm ^-3 ~1e16 cm ^-3 .

Furthermore, the ion implantation in step (2) uses BF2 or B11.

Furthermore, the ion implantation in step (3) uses phosphorus or As.

Furthermore, the ion implantation in step (4) uses BF2 or B11.

Furthermore, the deep groove described in step (5) is produced by dry etching with a depth of 2-5 um.

The beneficial effects of this application are:

(1) Through the structural design of the high-voltage region and the low-voltage region, the SGT-NMOS body, the PNP bipolar transistor body and the low-voltage CMOS device body are all constructed in or on the N-epitaxial layer, and the N-epitaxial layer of the low-voltage region has a first deep P-type well region as a common ground terminal of the low-voltage region, and the PNP bipolar transistor and the low-voltage CMOS device share the first deep P-type well region, so that the high-voltage device and the low-voltage device are integrated to realize the integration of the power management module and the driving power device, with high integration and high power density;

(2) The integration of high-voltage and low-voltage regions enables the temperature detection circuit to accurately detect the temperature of the high-voltage and low-voltage regions of the power transistor;

(3) The first metal lead-out layer is extended to the back of the entire transistor, which greatly improves the heat dissipation performance of the device;

(4) The structural design of the integrated high-voltage region and the low-voltage region makes the manufacturing process of the metal oxide field effect power transistor simple and fast.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a schematic structural diagram of the present invention;

FIG2 is a schematic diagram of the structure of Embodiment 1 of the present invention;

FIG3 is a schematic diagram of step 1 of process step 1 of the present invention;

FIG4 is a schematic diagram of step 2 of process step 1 of the present invention;

FIG5 is a schematic diagram of step 3 of process step 1 of the present invention;

FIG6 is a schematic diagram of step 4 of process step 1 of the present invention;

FIG7 is a schematic diagram of step 5 of process step 1 of the present invention;

FIG8 is a schematic diagram of step 6 of process step 1 of the present invention;

FIG9 is a schematic diagram of step 7 of process step 1 of the present invention;

FIG10 is a schematic diagram of step 8 of process step 1 of the present invention;

FIG11 is a schematic diagram of step 9 of process step 1 of the present invention;

FIG12 is a schematic diagram of step 10 of process step 1 of the present invention;

FIG13 is a schematic diagram of step 11 of process step 1 of the present invention;

FIG14 is a schematic diagram of step 12 of process step 1 of the present invention;

FIG15 is a schematic diagram of step 13 of process step 1 of the present invention;

FIG16 is a schematic diagram of step 14 of process step 1 of the present invention;

FIG17 is a schematic diagram of the structure of Embodiment 2 of the present invention;

FIG18 is a schematic diagram of the structure of Embodiment 3 of the present invention;

Among them, high voltage region A, low voltage region B, first metal lead layer a, N+ substrate layer b, N- epitaxial layer c, first deep P-type well region d, SGT-NMOS 1, deep trench 1-1, P-type body region 1-2, second P+ region 1-3, first N+ region 1-4, second metal lead layer 1-5, SGT-NMOS field plate polycrystalline layer 1-1-1, SGT-NMOS control gate polycrystalline layer 1-1-2, PNP bipolar transistor 2, first N-type well region 2-1, third P+ region 2-2, second N+ region 2-3, fourth P+ region 2-4, third N+ region 2-5, CMOS device 3, low voltage PMOS device 31, second N-type well region 311, fourth N+ region 312, first Fifth P+ region 313, PMOS control gate polycrystalline layer 314, first gate oxide layer 315, PLDD region 316, sixth P+ region 317, low voltage NMOS device 32, third N-type well region 321, first P-type well region 322, fifth N+ region 323, NLDD region 324, second gate oxide layer 325, NMOS control gate polycrystalline layer 326, sixth N+ region 327, seventh P+ region 328, seventh N+ region 329, deep trench 4, first P+ region 5, shallow trench 6, P-type enrichment region 7, SGT-PMOS 8, deep trench 8-1, N-type body region 8-2, eighth N+ region 8-3, eighth P+ region 8-4, twelfth metal lead-out layer 8-5, second deep P-type well region 8-6, SGT-NMOS field plate polycrystalline layer 8-1-1, SGT-PMOS control gate polycrystalline layer 8-1-2, NPN bipolar transistor 9, fourth N-type well region 9-1, second P-type well region 9-2, ninth P+ region 9-3, tenth N+ region 9-4, tenth P+ region 9-5, ninth N+ region 9-6.

DETAILED DESCRIPTION

Through the structural design of the high-voltage area and the low-voltage area, the SGT-NMOS body, the PNP bipolar transistor body and the low-voltage CMOS device body are all constructed in the N-epitaxial layer or on the N-epitaxial layer, and the N-epitaxial layer of the low-voltage area has a first deep P-type well area as the common ground end of the low-voltage area. The PNP bipolar transistor and the low-voltage CMOS device share the first deep P-type well area, integrating the high-voltage device with the low-voltage device to realize the integration of the power management module and the driving power device. The integration is high and the power density is high; the integration of the high-voltage area and the low-voltage area enables the temperature detection circuit to accurately detect the temperature of the high and low voltage areas of the power transistor; the first metal lead-out layer is also extended to the back of the entire transistor to greatly improve the heat dissipation performance of the device.

Furthermore, the solution of the present application is neither based on VDMOS nor LDMOS integration. Through the integrated structural design of the high-voltage region and the low-voltage region of the present application, the manufacturing process of the metal oxide field effect power transistor is simple and fast.

In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the specific implementation mode, structure, characteristics and effects of the present invention are described in detail below in combination with the accompanying drawings and preferred embodiments.

Example 1

As shown in FIG1 , a metal oxide field effect power transistor based on BCD integration includes a substrate, a deep trench isolation 4 is provided in the substrate to isolate the substrate into a high voltage region A and a low voltage region B, and both sides of the low voltage region B have deep trench isolation 4; the substrate includes a first metal lead-out layer a, an N+ substrate layer b, and an N- epitaxial layer c stacked in sequence from bottom to top along a vertical direction; the high voltage region A has an SGT-NMOS body, and the low voltage region B has a PNP bipolar transistor body and a low voltage CMOS device body;

The first metal lead-out layer a is also extended to the back of the entire transistor; the SGT-NMOS body, the PNP bipolar transistor body and the low-voltage CMOS device body are all constructed in or on the N-epitaxial layer c, and respectively form the SGT-NMOS 1, the PNP bipolar transistor 2 and the low-voltage CMOS device 3 with the substrate;

The N-epitaxial layer c of the low voltage region B has a first deep P-type well region d as a common ground terminal of the low voltage region B, and the PNP bipolar transistor 2 and the low voltage CMOS device 3 share the first deep P-type well region d;

The low voltage region B also has a first P+ region 5, which is arranged between the PNP bipolar transistor 2 and the low voltage CMOS device 3 and is located in the first deep P-type well region d. The PNP bipolar transistor 2 is isolated from the first P+ region 5 by a shallow trench, and the low voltage CMOS device 3 is isolated from the first P+ region 5 by a shallow trench. The first P+ region 5 is used for grounding.

The low voltage CMOS device 3 includes a low voltage PMOS device 31 and a low voltage NMOS device 32 . The low voltage PMOS device 31 and the low voltage NMOS device 32 are isolated from each other by a shallow trench.

The SGT-NMOS 1 includes a first metal lead-out layer a, an N+ substrate layer b, and an N-epitaxial layer c which are sequentially arranged from bottom to top, a deep trench 1-1 is provided in the N-epitaxial layer c, and a SGT-NMOS field plate polycrystalline layer 1-1-1 and a SGT-NMOS control gate polycrystalline layer 1-1-2 are provided in the deep trench 1-1; a P-type body region 1-2, a first N+ region 1-4, and a second P+ region 1-3 are symmetrically arranged on both sides of the deep trench 1-1, the first N+ region 1-4 and the second P+ region 1-3 are adjacent to each other and are both arranged on the P-type body region 1-2, and the first N+ region 1-4 is close to the deep trench 1-1; a second metal lead-out layer 1-5 is provided on the first N+ region 1-4 and the second P+ region 1-3, and a source of the SGT-NMOS 1 is formed by leading out the second metal 1-5 lead-out layer;

The PNP bipolar transistor 2 includes a first metal lead-out layer a, an N+ substrate layer b and an N-epitaxial layer c arranged in sequence from bottom to top, a deep P-type well region d serving as a common ground terminal of the low-voltage region B is provided in the N-epitaxial layer c, a first N-type well region 2-1 and a third P+ region 2-2 serving as a collector region of the PNP bipolar transistor 2 are provided in the deep P-type well region d, the first N-type well region 2-1 and the third P+ region 2-2 are isolated by a shallow trench; the first N-type well region 2-1 has a third P+ region 2-2 arranged in sequence as a first base region of the PNP bipolar transistor 2. a second N+ region 2-3, a fourth P+ region 2-4 as an emitter region of a PNP bipolar transistor, and a third N+ region 2-5 as a second base region of the PNP bipolar transistor 2; the third P+ region 2-2 is led out through a third metal lead-out layer, the second N+ region 2-3 is led out through a fourth metal lead-out layer, the fourth P+ region 2-4 is led out through a fifth metal lead-out layer, and the third N+ region 2-5 is led out through a sixth metal lead-out layer, to form a first collector, a first base, a first emitter, and a second base of the PNP bipolar transistor 2, respectively;

The low voltage PMOS device 31 comprises a first metal lead-out layer a, an N+ substrate layer b, and an N-epitaxial layer c arranged in sequence from bottom to top, wherein the N-epitaxial layer c has a deep P-type well region d as a common ground terminal of the low voltage region B, the deep P-type well region d has a second N-type well region 311, and the second N-type well region 311 has a fourth N+ region 312, a fifth P+ region 313, and a sixth P+ region 317 arranged in sequence, the fourth N+ region 312 and the fifth P+ region 313 are connected by the first The seventh metal lead-out layer leads out, and the sixth P+ region 317 is led out through the eighth metal lead-out layer. A first gate oxide layer 315 is provided on the second N-type well region 311 between the fifth P+ region 313 and the sixth P+ region 317, and a PMOS control gate polycrystalline layer 314 is provided on the first gate oxide layer 315; two PLDD regions 316 are provided on both sides under the first gate oxide layer 315, and the two PLDD regions 316 are connected to the fifth P+ region 313 and the sixth P+ region 317 respectively;

The low voltage NMOS device 32 comprises a first metal lead-out layer a, an N+ substrate layer b, and an N-epitaxial layer c, which are arranged in sequence from bottom to top. The N-epitaxial layer c has a deep P-type well region d as a common ground terminal of the low voltage region B, a third N-type well region 321 in the deep P-type well region d, a P-type well region 322 in the third N-type well region 321, a fifth N+ region 323, a sixth N+ region 327, and a seventh P+ region 328 arranged in sequence in the P-type well region 322, the fifth N+ region 323 is led out through a ninth metal lead-out layer, the sixth N+ region 327 and the seventh P+ region 328 are led out through a tenth metal lead-out layer, and the sixth N+ region 327 and the seventh P+ region 328 are connected to the P-type well region 322. The lead-out layer leads out, and a second gate oxide layer 325 is provided on the P-type well region 322 between the fifth N+ region 323 and the sixth N+ region 327, and an NMOS control gate polycrystalline layer 326 is provided on the second gate oxide layer 325; two NLDD regions 324 are provided on both sides under the second gate oxide layer 325, and the two NLDD regions 324 are respectively connected to the fifth N+ region 323 and the sixth N+ region 327; a seventh N+ region 329 is also provided in the third N-type well region 321, and the seventh N+ region 329 is isolated from the P-type well region 322 by a shallow trench, and the seventh N+ region 329 is led out through the eleventh metal lead-out layer.

As shown in FIG2 , without changing the transistor structure of the present embodiment, the functions of the third P+ region 2-2 and the first P+ region 5 can be interchanged through different connection methods during use, thereby changing the structural division of the PNP bipolar transistor 2.

A process for preparing a metal oxide field effect power transistor based on BCD integration comprises the following steps:

(1) As shown in FIG. 3 , an N-epitaxial layer c is grown on an N+ substrate b, the thickness of the N-epitaxial layer is 4 um, and in some embodiments, 10 um may also be used, and the doping concentration of the N-epitaxial layer is 1e14 cm ^-3 , and in some embodiments, 1e16 cm ^-3 may also be used, which is a common technical means in the art;

(2) As shown in FIG. 4 , a pattern mask is set on the N-epitaxial layer c, and ion implantation is performed to produce a deep P-type well region d. The ion implantation uses BF2, and in some embodiments, B11 can also be used, which is a common technical means in the art;

(3) As shown in FIG. 5 , a pattern mask is provided, and a first N-type well region 2-1, a second N-type well region 311, and a third N-type well region 312 are produced in the deep P-type well region d by ion implantation. Phosphorus is used for ion implantation, and As may also be used in some embodiments, which is a common technical means in the art;

(4) As shown in FIG. 6 , a pattern mask is provided, and a P-type body region 1-2 and a first P-type well region 322 are formed in the third N-type well region 312 and the N-type epitaxial layer c by ion implantation. The ion implantation is performed by using BF2, and in some embodiments, B11 may also be used, which is a common technical means in the art;

(5) As shown in FIG. 7 , a deep trench 1-1 of the SGT-NMOS 1, a deep trench 4 between the high voltage region A and the low voltage region B, and a deep trench 4 on the other side of the low voltage region are manufactured by pattern mask. The deep trenches 1-1 and 4 are manufactured by dry etching with a depth of 2 μm. In some embodiments, 5 μm can also be used, which is a common technical means in the art.

(6) As shown in FIG8 , the deep trenches 1 - 1 and 4 are thermally oxidized, and then polysilicon is deposited and selectively etched to produce the SGT-NMOS field plate polycrystalline layer 1 - 1 - 1 and the field plate polycrystalline layers in other deep trenches;

(7) As shown in FIG9 , after thermal oxidation, polysilicon is deposited and selectively dry-etched to produce the SGT-NMOS control gate polycrystalline layer 1-1-2 and the control gate polycrystalline layer in other deep trenches;

(8) As shown in FIG. 10 , shallow trench isolation between the first N-type well region 2-1 and the third P+ region 2-2, shallow trench isolation between the PNP bipolar transistor 2 and the first P+ region 5, shallow trench isolation between the low-voltage CMOS device 3 and the first P+ region 5, shallow trench isolation between the low-voltage PMOS device 31 and the low-voltage NMOS device 32, and shallow trench isolation between the seventh N+ region 329 and the P-type well region 322 are fabricated by thermal oxidation, selective masking, and etching methods;

(9) As shown in FIG. 11 , a first gate oxide layer 315 and a second gate oxide layer 325 are manufactured by a low temperature oxidation method;

(10) As shown in FIG. 12 , polysilicon is deposited, and a PMOS control gate polycrystalline layer 314 and an NMOS control gate polycrystalline layer 326 are respectively produced by pattern masking and etching;

(11) As shown in FIG. 13 , the PMOS control gate polycrystalline layer 314 and the NMOS control gate polycrystalline layer 326 are pre-oxidized to form an oxide layer;

(12) As shown in FIG. 14 , an NLDD region 324 and a PLDD region 316 are formed by LDD implantation;

(13) As shown in FIG. 15 , the self-aligned implanted sidewall regions of the low voltage PMOS device and the low voltage NMOS device are fabricated by using growth and etching techniques of different materials;

(14) As shown in FIG. 16 , a first N+ region 1-4, a second N+ region 2-3, a third N+ region 2-5, a fourth N+ region 312, a fifth N+ region 323, a sixth N+ region 327, and a seventh N+ region 329 are produced by pattern masking; then, a first P+ region 5, a second P+ region 1-3, a third P+ region 2-2, a fourth P+ region 2-4, a fifth P+ region 313, a sixth P+ region 317, and a seventh P+ region 328 are produced by pattern masking;

(15) Produce a dielectric insulating layer, and produce a lead hole layer by pattern masking and etching;

(16) Fabricate a first metal lead layer a, a second metal lead layer 1-5, a third metal lead layer, a fourth metal lead layer, a fifth metal lead layer, a sixth metal lead layer, a seventh metal lead layer, an eighth metal lead layer, a ninth metal lead layer, a tenth metal lead layer, and an eleventh metal lead layer to fabricate a metal oxide field effect power transistor based on BCD integration as shown in FIG. 1 .

Example 2

Based on the first embodiment, the present embodiment adds a SGT-PMOS 8 in the high voltage region A and adds an NPN bipolar transistor 9 in the low voltage region B.

Specifically, as shown in FIG17 , a metal oxide field effect power transistor based on BCD integration includes a substrate, a deep trench isolation 4 is provided in the substrate to isolate the substrate into a high voltage region A and a low voltage region B, and both sides of the low voltage region B have deep trench isolation 4; the substrate includes a first metal lead-out layer a, an N+ substrate layer b, and an N- epitaxial layer c stacked in sequence from bottom to top along the vertical direction; the high voltage region A has an SGT-NMOS body, and the low voltage region B has a PNP bipolar transistor body and a low voltage CMOS device body;

The first metal lead-out layer a is also extended to the back of the entire transistor; the SGT-NMOS body, the PNP bipolar transistor body and the low-voltage CMOS device body are all constructed in or on the N-epitaxial layer c, and respectively form the SGT-NMOS 1, the PNP bipolar transistor 2 and the low-voltage CMOS device 3 with the substrate;

The N-epitaxial layer c of the low voltage region B has a first deep P-type well region d as a common ground terminal of the low voltage region B, and the PNP bipolar transistor 2 and the low voltage CMOS device 3 share the first deep P-type well region d;

The low voltage region B also has a first P+ region 5, which is arranged between the PNP bipolar transistor 2 and the low voltage CMOS device 3 and is located in the first deep P-type well region d. The PNP bipolar transistor 2 is isolated from the first P+ region 5 by a shallow trench, and the low voltage CMOS device 3 is isolated from the first P+ region 5 by a shallow trench. The first P+ region 5 is used for grounding.

The low voltage CMOS device 3 includes a low voltage PMOS device 31 and a low voltage NMOS device 32 . The low voltage PMOS device 31 and the low voltage NMOS device 32 are isolated from each other by a shallow trench.

The high voltage region A also has a SGT-PMOS 8. The devices in the high voltage region A are SGT-PMOS 1 and SGT-NMOS 8 in the horizontal direction. The SGT-PMOS 1 and SGT-NMOS 8 are isolated from each other by a deep trench.

The low voltage region B also has an NPN bipolar transistor 9. The devices in the low voltage region B are the NPN bipolar transistor 9, the PNP bipolar transistor 2 and the low voltage CMOS device 3 in the horizontal direction. The NPN bipolar transistor 9 shares the first deep P-type well region d with the PNP bipolar transistor 2 and the low voltage CMOS device 3.

The SGT-NMOS 1 includes a first metal lead-out layer a, an N+ substrate layer b, and an N-epitaxial layer c which are sequentially arranged from bottom to top, a deep trench 1-1 is provided in the N-epitaxial layer c, and a SGT-NMOS field plate polycrystalline layer 1-1-1 and a SGT-NMOS control gate polycrystalline layer 1-1-2 are provided in the deep trench 1-1; a P-type body region 1-2, a first N+ region 1-4, and a second P+ region 1-3 are symmetrically arranged on both sides of the deep trench 1-1, the first N+ region 1-4 and the second P+ region 1-3 are adjacent to each other and are both arranged on the P-type body region 1-2, and the first N+ region 1-4 is close to the deep trench 1-1; a second metal lead-out layer 1-5 is provided on the first N+ region 1-4 and the second P+ region 1-3, and a source of the SGT-NMOS 1 is formed by leading out the second metal 1-5 lead-out layer;

The PNP bipolar transistor 2 includes a first metal lead-out layer a, an N+ substrate layer b and an N-epitaxial layer c arranged in sequence from bottom to top, a deep P-type well region d serving as a common ground terminal of the low-voltage region B is provided in the N-epitaxial layer c, a first N-type well region 2-1 and a third P+ region 2-2 serving as a collector region of the PNP bipolar transistor 2 are provided in the deep P-type well region d, the first N-type well region 2-1 and the third P+ region 2-2 are isolated by a shallow trench; the first N-type well region 2-1 has a third P+ region 2-2 arranged in sequence as a first base region of the PNP bipolar transistor 2. a second N+ region 2-3, a fourth P+ region 2-4 as an emitter region of a PNP bipolar transistor, and a third N+ region 2-5 as a second base region of the PNP bipolar transistor 2; the third P+ region 2-2 is led out through a third metal lead-out layer, the second N+ region 2-3 is led out through a fourth metal lead-out layer, the fourth P+ region 2-4 is led out through a fifth metal lead-out layer, and the third N+ region 2-5 is led out through a sixth metal lead-out layer, to form a first collector, a first base, a first emitter, and a second base of the PNP bipolar transistor 2, respectively;

The low voltage PMOS device 31 comprises a first metal lead-out layer a, an N+ substrate layer b, and an N-epitaxial layer c arranged in sequence from bottom to top, wherein the N-epitaxial layer c has a deep P-type well region d as a common ground terminal of the low voltage region B, the deep P-type well region d has a second N-type well region 311, and the second N-type well region 311 has a fourth N+ region 312, a fifth P+ region 313, and a sixth P+ region 317 arranged in sequence, the fourth N+ region 312 and the fifth P+ region 313 are connected by the first The seventh metal lead-out layer leads out, and the sixth P+ region 317 is led out through the eighth metal lead-out layer. A first gate oxide layer 315 is provided on the second N-type well region 311 between the fifth P+ region 313 and the sixth P+ region 317, and a PMOS control gate polycrystalline layer 314 is provided on the first gate oxide layer 315; two PLDD regions 316 are provided on both sides under the first gate oxide layer 315, and the two PLDD regions 316 are connected to the fifth P+ region 313 and the sixth P+ region 317 respectively;

The low voltage NMOS device 32 comprises a first metal lead-out layer a, an N+ substrate layer b, and an N-epitaxial layer c, which are arranged in sequence from bottom to top. The N-epitaxial layer c has a deep P-type well region d as a common ground terminal of the low voltage region B, a third N-type well region 321 in the deep P-type well region d, a P-type well region 322 in the third N-type well region 321, a fifth N+ region 323, a sixth N+ region 327, and a seventh P+ region 328 arranged in sequence in the P-type well region 322, the fifth N+ region 323 is led out through a ninth metal lead-out layer, the sixth N+ region 327 and the seventh P+ region 328 are led out through a tenth metal lead-out layer, and the sixth N+ region 327 and the seventh P+ region 328 are connected to the P-type well region 322. The lead-out layer leads out, and a second gate oxide layer 325 is provided on the P-type well region 322 between the fifth N+ region 323 and the sixth N+ region 327, and an NMOS control gate polycrystalline layer 326 is provided on the second gate oxide layer 325; two NLDD regions 324 are provided on both sides under the second gate oxide layer 325, and the two NLDD regions 324 are respectively connected to the fifth N+ region 323 and the sixth N+ region 327; a seventh N+ region 329 is also provided in the third N-type well region 321, and the seventh N+ region 329 is isolated from the P-type well region 322 by a shallow trench, and the seventh N+ region 329 is led out through the eleventh metal lead-out layer.

The SGT-PMOS 8 includes a first metal lead-out layer a, an N+ substrate layer b, and an N-epitaxial layer c which are arranged in sequence from bottom to top. The N-epitaxial layer c has a second deep P-type well region 8-6, and a deep trench 8-1 is provided in the second deep P-type well region 8-6. The deep trench 8-1 has an SGT-PMOS field plate polycrystalline layer 8-1-1 and an SGT-PMOS control gate polycrystalline layer 8-1-2. The N-type body region 8-2, the eighth N+ region 8-3, and the eighth P+ region 8-4 are symmetrically arranged on both sides of the deep trench 8-1. The eighth N+ region 8-3 and the eighth P+ region 8-4 are adjacent and are both arranged on the N-type body region 8-2, and the eighth P+ region 8-4 is close to the deep trench. The eighth N+ region 8-3 and the eighth P+ region 8-4 have a twelfth metal lead-out layer 8-5, and the source of the SGT-PMOS 8 is formed by leading out through the twelfth metal lead-out layer 8-5. The SGT-PMOS 8 further has a P-type enrichment region 7 in the second deep P-type well region 8 - 6 .

The NPN bipolar transistor 9 includes a first metal lead-out layer a, an N+ substrate layer b and an N-epitaxial layer c arranged in sequence from bottom to top, a deep P-type well region d serving as a common ground terminal of the low voltage region B in the N-epitaxial layer c, a fourth N-type well region 9-1 in the deep P-type well region d, a second P-type well region 9-2 and a ninth N+ region 9-6 serving as a collector region of the NPN bipolar transistor 9 in the fourth N-type well region 9-1, a ninth P+ region 9-6 serving as a third base region of the NPN bipolar transistor 9 arranged in sequence in the second P-type well region 9-2 Domain 9-3, the tenth N+ region 9-4 as the emitter region of the NPN type bipolar transistor 9 and the tenth P+ region 9-5 as the fourth base region of the NPN type bipolar transistor 9; the ninth N+ region 9-6 is led out through the thirteenth metal lead-out layer, the ninth P+ region 9-3 is led out through the fourteenth metal lead-out layer, the tenth N+ region 9-4 is led out through the fifteenth metal lead-out layer, and the tenth P+ region 9-5 is led out through the sixteenth metal lead-out layer, to form the second collector, third base, second emitter and fourth base of the NPN type bipolar transistor 9 respectively.

Example 3

As shown in FIG18 , this embodiment is basically the same as the embodiment 2, except that the structures of the field plate polycrystalline layer and the control gate polycrystalline layer in the deep trench are changed. Taking the deep trench 8-1 of SGT-PMOS 8 as an example, the SGT-NMOS field plate polycrystalline layer 8-1-1 of the deep trench 8-1 is arranged along the length direction of the deep trench, and there are two SGT-PMOS control gate polycrystalline layers 8-1-2, which are symmetrically arranged on both sides of the SGT-PMOS field plate polycrystalline layer 8-1-1. The SGT-NMOS field plate polycrystalline layer 1-1-1 and the SGT-NMOS control gate polycrystalline layer 1-1-2 in the deep trench 1-1 of SGT-NMOS 1 also have the same structure. The arrangement of the field plate polycrystalline layer and the control gate polycrystalline layer is a common technical means in this field.

In the present application, the isolation between the high-voltage area and the low-voltage area is achieved by silicon dioxide + polycrystalline, which has a high dielectric constant and a good isolation effect.

The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims (14)

1. The metal oxide field effect power transistor based on BCD integration is characterized by comprising a substrate, wherein deep trench isolation is arranged in the substrate to isolate the substrate into a high-voltage region and a low-voltage region, and the two sides of the low-voltage region are provided with the deep trench isolation; the substrate comprises a first metal lead-out layer, an N+ substrate layer and an N-epitaxial layer which are sequentially stacked from bottom to top along the vertical direction; the high-voltage region is internally provided with at least an SGT-NMOS main body, and the low-voltage region is internally provided with at least a PNP bipolar transistor main body and a low-voltage CMOS device main body;

The first metal lead-out layer is also arranged on the back of the whole transistor in an extending way; the SGT-NMOS main body, the PNP bipolar transistor main body and the low-voltage CMOS device main body are all built in an N-epitaxial layer or on the N-epitaxial layer and respectively form an SGT-NMOS, a PNP bipolar transistor and a low-voltage CMOS device with a substrate;

The N-epitaxial layer of the low-voltage region is internally provided with a first deep P-type well region serving as a common ground end of the low-voltage region, and the PNP-type bipolar transistor and the low-voltage CMOS device share the first deep P-type well region;

The low-voltage region is also provided with a first P+ region, the first P+ region is arranged between the PNP type bipolar transistor and the low-voltage CMOS device and is positioned in the first deep P type well region, the PNP type bipolar transistor is isolated from the first P+ region through a shallow groove, the low-voltage CMOS device is isolated from the first P+ region through a shallow groove, and the first P+ region is used for grounding.

2. The BCD-integrated metal oxide field effect power transistor of claim 1, wherein the high voltage region further comprises an SGT-PMOS, the devices in the high voltage region are sequentially an SGT-PMOS and an SGT-NMOS in a horizontal direction, and the SGT-PMOS and the SGT-NMOS are isolated by a deep trench.

3. The BCD integration-based metal oxide field effect power transistor of claim 1, wherein the low voltage region further comprises an NPN bipolar transistor, a PNP bipolar transistor and a low voltage CMOS device, the NPN bipolar transistor, the PNP bipolar transistor and the low voltage CMOS device sharing the first deep P-well region, the NPN bipolar transistor and the low voltage CMOS device being arranged in the low voltage region in the order of the NPN bipolar transistor, the PNP bipolar transistor and the low voltage CMOS device.

4. The metal oxide field effect power transistor based on BCD integration of claim 1, wherein the SGT-NMOS comprises a first metal extraction layer, an n+ substrate layer, an N-epitaxial layer, and a deep trench having an SGT-NMOS field plate poly layer and an SGT-NMOS control gate poly layer therein, disposed in sequence from bottom to top; the deep groove is provided with a P-type body region, a first N+ region and a second P+ region which are symmetrically arranged at two sides of the deep groove, the first N+ region and the second P+ region are adjacent and are arranged on the P-type body region, and the first N+ region is close to the deep groove; the first N+ region and the second P+ region are provided with a second metal extraction layer, and the source electrode of the SGT-NMOS is extracted through the second metal extraction layer;

the PNP bipolar transistor comprises a first metal lead-out layer, an N+ substrate layer and an N-epitaxial layer which are sequentially arranged from bottom to top, wherein a deep P-type well region serving as a common ground end of a low-voltage region is arranged in the N-epitaxial layer, a first N-type well region and a third P+ region serving as a collector region of the PNP bipolar transistor are arranged in the deep P-type well region, and the first N-type well region and the third P+ region are isolated through shallow grooves; the first N-type well region is internally provided with a second N+ region serving as a first base region of the PNP type bipolar transistor, a fourth P+ region serving as an emitter region of the PNP type bipolar transistor and a third N+ region serving as a second base region of the PNP type bipolar transistor which are sequentially arranged; the third P+ region is led out through a third metal leading-out layer, the second N+ region is led out through a fourth metal leading-out layer, the fourth P+ region is led out through a fifth metal leading-out layer, and the third N+ region is led out through a sixth metal leading-out layer to respectively form a first collector, a first base, a first emitter and a second base of the PNP bipolar transistor;

the low-voltage CMOS device comprises a low-voltage PMOS device and a low-voltage NMOS device, wherein the low-voltage PMOS device and the low-voltage NMOS device are isolated through a shallow groove;

The low-voltage PMOS device comprises a first metal lead-out layer, an N+ substrate layer and an N-epitaxial layer which are sequentially arranged from bottom to top, wherein a deep P-type well region serving as a common ground end of a low-voltage region is arranged in the N-epitaxial layer, a second N-type well region is arranged in the deep P-type well region, a fourth N+ region, a fifth P+ region and a sixth P+ region which are sequentially arranged in the second N-type well region are arranged, the fourth N+ region and the fifth P+ region are led out through a seventh metal lead-out layer, the sixth P+ region is led out through an eighth metal lead-out layer, a first gate oxide layer is arranged on the second N-type well region between the fifth P+ region and the sixth P+ region, and a PMOS control gate layer is arranged on the first gate oxide layer; two PLDD regions are arranged on two sides below the first gate oxide layer and are respectively connected with a fifth P+ region and a sixth P+ region;

The low-voltage NMOS device comprises a first metal lead-out layer, an N+ substrate layer and an N-epitaxial layer which are sequentially arranged from bottom to top, wherein a deep P-type well region serving as a common ground end of a low-voltage region is arranged in the N-epitaxial layer, a third N-type well region is arranged in the deep P-type well region, a first P-type well region is arranged in the third N-type well region, a fifth N+ region, a sixth N+ region and a seventh P+ region are sequentially arranged in the first P-type well region, the fifth N+ region is led out through a ninth metal lead-out layer, the sixth N+ region and the seventh P+ region are led out through a tenth metal lead-out layer, a second gate oxide layer is arranged on the fifth N+ region of the fourth N+ region, and an NMOS control gate polycrystalline layer is arranged on the second gate oxide layer; two NLDD regions are arranged on two sides below the second gate oxide layer and are respectively connected with a fifth N+ region and a sixth N+ region; the third N-type well region is also provided with a seventh N+ region, the seventh N+ region is isolated from the P-type well region through a shallow groove, and the seventh N+ region is led out through an eleventh metal leading-out layer.

5. The metal oxide field effect power transistor based on BCD integration of claim 2, wherein the SGT-PMOS comprises a first metal extraction layer, an n+ substrate layer, an N-epitaxial layer, a second deep P-well region in the N-epitaxial layer, a deep trench in the second deep P-well region, an SGT-PMOS field plate polycrystalline layer and an SGT-PMOS control gate polycrystalline layer in the deep trench, which are sequentially arranged from bottom to top; the deep groove is provided with an N-type body region, an eighth N+ region and an eighth P+ region which are symmetrically arranged at two sides of the deep groove, the eighth N+ region and the eighth P+ region are adjacent and are arranged on the N-type body region, and the eighth P+ region is close to the deep groove; and a twelfth metal extraction layer is arranged on the eighth N+ region and the eighth P+ region, and the source electrode of the SGT-PMOS is formed through extraction of the twelfth metal extraction layer.

6. The BCD-integrated metal-oxide-field-effect-power transistor of claim 5, wherein said SGT-PMOS second deep P-well region further comprises a P-type enhancement region.

7. The BCD integration-based metal oxide field effect power transistor according to claim 3, wherein the NPN bipolar transistor comprises a first metal lead-out layer, an n+ substrate layer and an N-epitaxial layer sequentially arranged from bottom to top, a deep P-type well region serving as a common ground of a low voltage region is formed in the N-epitaxial layer, a fourth N-type well region is formed in the deep P-type well region, a second P-type well region and a ninth n+ region serving as a collector region of the NPN bipolar transistor are formed in the fourth N-type well region, and a ninth p+ region serving as a third base region of the NPN bipolar transistor, a tenth n+ region serving as an emitter region of the NPN bipolar transistor and a tenth p+ region serving as a fourth base region of the NPN bipolar transistor are sequentially arranged in the second P-type well region; the ninth N+ region is led out through a thirteenth metal leading-out layer, the ninth P+ region is led out through a fourteenth metal leading-out layer, the tenth N+ region is led out through a fifteenth metal leading-out layer, and the tenth P+ region is led out through a sixteenth metal leading-out layer to respectively form a second collector, a third base, a second emitter and a fourth base of the NPN bipolar transistor.

8. A process for preparing a BCD integrated metal oxide field effect power transistor in accordance with claim 4, comprising the steps of:

(1) Growing an N-epitaxial layer on the N+ type substrate;

(2) A pattern photomask is arranged on the N-epitaxial layer, and a deep P-type well region is manufactured by ion implantation;

(3) A pattern photomask is arranged, and a first N-type well region, a second N-type well region and a third N-type well region are manufactured in the deep P-type well region through ion implantation;

(4) Setting a pattern photomask, and manufacturing a P-type body region and a first P-type well region in the third N-type well region and the N-type epitaxial layer through ion implantation;

(5) Manufacturing a deep groove of the SGT-NMOS, a deep groove between a high-voltage area and a low-voltage area and a deep groove at the other side of the low-voltage area through a pattern photomask;

(6) Performing thermal oxidation on the deep groove, then depositing polycrystalline silicon, and selectively etching the polycrystalline silicon to manufacture an SGT-NMOS field plate polycrystalline layer and field plate polycrystalline layers in other deep grooves;

(7) After thermal oxidation, depositing polycrystalline silicon, and carrying out selective dry etching on the polycrystalline silicon to manufacture an SGT-NMOS control gate polycrystalline layer and other control gate polycrystalline layers in the deep grooves;

(8) Manufacturing shallow trench isolation between a first N-type well region and a third P+ region, shallow trench isolation between a PNP bipolar transistor and the first P+ region, shallow trench isolation between a low-voltage CMOS device and the first P+ region, shallow trench isolation between a low-voltage PMOS device and a low-voltage NMOS device, and shallow trench isolation between a seventh N+ region and a P-type well region by thermal oxidation, a selective photomask and an etching method;

(9) Manufacturing a first gate oxide layer and a second gate oxide layer by a low-temperature oxidation method;

(10) Depositing polysilicon, and respectively manufacturing a PMOS control gate polycrystalline layer and an NMOS control gate polycrystalline layer through a pattern photomask and etching;

(11) Pre-oxidizing the PMOS control gate polycrystalline layer and the NMOS control gate polycrystalline layer to manufacture an oxide layer;

(12) Forming an NLDD region and a PLDD region through LDD implantation;

(13) The self-aligned injection side wall regions of the low-voltage PMOS device and the low-voltage NMOS device are manufactured through the growth and etching technology of different materials;

(14) Manufacturing a first N+ region, a second N+ region, a third N+ region, a fourth N+ region, a fifth N+ region, a sixth N+ region and a seventh N+ region through a graph photomask; then, a first P+ region, a second P+ region, a third P+ region, a fourth P+ region, a fifth P+ region, a sixth P+ region and a seventh P+ region are manufactured through a graphic photomask;

(15) Manufacturing a dielectric insulating layer, and manufacturing a lead hole layer through a pattern photomask and etching;

(16) And manufacturing a first metal lead-out layer, a second metal lead-out layer, a third metal lead-out layer, a fourth metal lead-out layer, a fifth metal lead-out layer, a sixth metal lead-out layer, a seventh metal lead-out layer, an eighth metal lead-out layer, a ninth metal lead-out layer, a tenth metal lead-out layer and an eleventh metal lead-out layer.

9. The process of claim 8, wherein the N-epi layer of step (1) has a thickness of 4-10 um.

10. The process of claim 8, wherein the N-epitaxial layer doping concentration of step (1) is 1e14cm ^-3~1e16 cm^-3.

11. The process of claim 8, wherein the ion implantation of step (2) is performed using BF2 or B11.

12. The process of claim 8, wherein the ion implantation in step (3) is performed using phosphorus or As.

13. The process of claim 8, wherein the ion implantation of step (4) is performed using BF2 or B11.

14. The process of claim 8, wherein the deep trench in step (5) is formed by dry etching to a depth of 2-5 um.