CN115497877B - Method for manufacturing semiconductor integrated device - Google Patents
Method for manufacturing semiconductor integrated deviceInfo
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- CN115497877B CN115497877B CN202211316324.7A CN202211316324A CN115497877B CN 115497877 B CN115497877 B CN 115497877B CN 202211316324 A CN202211316324 A CN 202211316324A CN 115497877 B CN115497877 B CN 115497877B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0181—Manufacturing their gate insulating layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明提供了一种半导体集成器件的制造方法方法，应用于半导体技术领域。具体的，其通过在去除了低压器件区的厚氧形成该区域的MOS器件的栅氧的过程中，同时在SGT器件中的表面形成一层薄氧层，从而弥补在刻蚀形成SGT器件的栅极多晶硅时，由于刻蚀过程中的误差导致的SGT器件的栅氧的损伤，进而避免了SGT器件发生漏电的问题，即，提高了器件的性能。并且，本发明提供了一种可以在同一块芯片同步生产SGT分离器件和BCD功率IC器件的方法，进而避免了现有技术中需要分步分别形成所述器件之后，再将二者键合连接，而导致的二者之间的寄生Rs和Rc比较大的问题，同时也提高了SGT器件和BCD器件的性能匹配度。
The present invention provides a method for manufacturing a semiconductor integrated device, which is applied to the field of semiconductor technology. Specifically, by removing the thick oxygen in the low-voltage device region to form the gate oxide of the MOS device in that region, a thin oxygen layer is simultaneously formed on the surface of the SGT device, thereby compensating for damage to the gate oxide of the SGT device caused by errors in the etching process when etching the gate polysilicon of the SGT device, thereby avoiding the problem of leakage in the SGT device, that is, improving the performance of the device. In addition, the present invention provides a method for simultaneously producing SGT separation devices and BCD power IC devices on the same chip, thereby avoiding the problem of large parasitic Rs and Rc between the two devices caused by the need to form the devices separately in steps and then bond them together in the prior art, and also improving the performance matching between the SGT device and the BCD device.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor integrated device.
Background
Power integrated ICs are widely used in power management, motor driving, automotive electronics, industrial control, and other fields. BCD refers to a process technology of integrating Bipolar, CMOS, DMOS and other high-voltage power devices, various resistors, capacitors and diodes into one chip, and has the characteristics of low cost, easiness in packaging and design, simplicity in peripheral chips and the like, and is rapidly developed into a mainstream technology in the field of power ICs. Bipolar transistors in BCD technology have high analog precision mainly used in analog circuits, CMOS has high integration mainly used in logic circuits, and DMOS has high power (high voltage) characteristics commonly used as switching.
In the prior art, a high-voltage device and a low-voltage device are often integrated in a BCD device, for example, the high-voltage device may be an LDMOS device, a high-voltage JFET device, etc., and the low-voltage device may be a low-voltage MOS device, etc. The split gate or shielded gate MOSFET is an improved UMOS device, and has faster switching speed and lower switching loss compared with UMOS. The structure according to poly is divided into up-down (UD SGT) and left-right (LR SGT). The SGT device utilizes a charge balance principle to reduce on-resistance by properly increasing the doping concentration of an epitaxial layer, and utilizes a shielding gate to reduce Cgd/Ciss and improve Dv/dt capacity.
Currently, the SGT separation device and PowerIC (power IC) BCD devices on the market are commonly manufactured separately and then packaged together to form a module. Therefore, in the high-end application field, the module formed by the method has the following problems that 1, the SGT separation device and the Power IC device of the BCD are connected through bonding wire, so that parasitic Rs and Rc are relatively large, and 2, the SGT separation device and the PowerIC device of the BCD are produced in an asynchronous manner, so that the performance matching degree of the SGT separation device and the BCD is not high.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor integrated device, which is a novel manufacturing method for integrating an SGT device and a BCD device into a same chip, and can solve the problem that the reliability of the gate oxide of the SGT device is low because the gate oxide of the SGT device is over-etched in the process of etching and forming gate polysilicon.
In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor integrated device, which specifically includes at least the following steps:
Providing a semiconductor substrate, wherein the semiconductor substrate comprises an SGT device region, a low-voltage device region and a high-voltage device region which are sequentially arranged side by side, the low-voltage device region comprises a PMOS region and an NMOS region, the high-voltage device region comprises an NLDMOS region and a PLDMOS region, a plurality of groove isolation structures for isolating each device structure in the SGT device region, the low-voltage device region and the high-voltage device region are formed on the semiconductor substrate, and the top surface of each groove isolation structure is higher than the top surface of the semiconductor substrate;
Forming a gate trench, a voltage-resistant groove, a first oxide layer, source polycrystalline silicon, an isolation layer, a second oxide layer and gate polycrystalline silicon which are filled in the gate trench in the semiconductor substrate corresponding to the SGT device region, wherein the source polycrystalline silicon also fills the voltage-resistant groove, the gate polycrystalline silicon covers the surface of the isolation layer and at least fills the rest of the gate trench, the source polycrystalline silicon in the voltage-resistant groove and the surfaces of the semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region are also covered, and the second oxide layer also extends to cover the surfaces of the semiconductor substrate between adjacent trench isolation structures;
Etching the gate polysilicon back until the gate polysilicon remained in the pressure-resistant groove and the gate groove is flush with the surface of the second oxide layer remained after the etching back;
And forming a third oxide layer on the surface of the semiconductor substrate, wherein the third oxide layer covers the surface of the rest second oxide layer and extends to cover the surface of the semiconductor substrate corresponding to the space between two adjacent groove isolation structures in the low-voltage device region.
Further, during the process of etching back the gate polysilicon, the second oxide layer with partial thickness is also etched back, thereby causing loss of the gate oxide layer of the SGT device.
Further, after forming the gate trench and the voltage-resistant trench, the manufacturing method may further include:
Performing a first ion implantation process on the semiconductor substrate corresponding to the PMOS region, the NMOS region, the NLDMOS region and the PLDMOS region to form at least three P-type deep wells in the low-voltage device region and the high-voltage device region;
and performing a second ion implantation process on the semiconductor substrate corresponding to the P-type deep well to form a plurality of high-voltage N wells in the high-voltage device region and a plurality of low-voltage N wells in the low-voltage device region.
Further, the step of forming the first oxide layer, the source polysilicon, the isolation layer, the second oxide layer and the gate polysilicon in the gate trench may include:
Forming a first oxide layer on the inner walls of the pressure-resistant groove and the gate groove, and filling source polycrystalline silicon in the pressure-resistant groove and the gate groove after the first oxide layer is formed so that the top surface of the filled source polycrystalline silicon is flush with the upper surface of the semiconductor substrate;
masking the surface of the semiconductor substrate corresponding to the pressure-resistant groove, etching back the source polycrystalline silicon and the first oxide layer in the grid groove to form a shielding grid and a thick oxide layer of the SGT device structure in the grid groove, forming an isolation layer on the top surfaces of the source polycrystalline silicon and the first oxide layer after etching back, and covering the surface of the isolation layer and the second oxide layer on the inner wall of the residual grid groove, wherein the second oxide layer also extends to cover the surface of the rest exposed semiconductor substrate.
Further, the remaining exposed semiconductor substrate surface covered by the second oxide layer extension may include a surface of the semiconductor substrate corresponding between two adjacent trench isolation structures in the low voltage device region.
Further, after etching back the gate polysilicon and before forming the third oxide layer, the manufacturing method may further include:
forming a photoresist layer which shields the semiconductor substrate corresponding to the SGT device region and the high-voltage device region, exposing the semiconductor substrate corresponding to the low-voltage device region, and etching to remove a second oxide layer formed in the low-voltage device region by taking the photoresist layer as a mask;
A third oxide layer is formed on the surface of the semiconductor substrate exposed between two adjacent trench isolation structures in the low voltage device region from which the second oxide layer is removed.
Further, the process of forming the third oxide layer may include a thermal oxidation process.
Further, the step of forming the trench isolation structure may include:
and forming a plurality of shallow trenches in the semiconductor substrate, and filling the shallow trenches to form the trench isolation structure for isolating the SGT device region, the low-voltage device region, the high-voltage device region and each MOS tube contained in the low-voltage device region and the high-voltage device region.
Further, after forming the third oxide layer, the manufacturing method may further include:
and forming a gate material layer, wherein the gate material layer covers the whole surface of the semiconductor substrate, and etching the gate material layer to form corresponding gate structures in the low-voltage device region and the high-voltage device region.
Further, the materials of the isolation layer, the first oxide layer, the second oxide layer, and the third oxide layer may include silicon dioxide.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
In the manufacturing method of the semiconductor integrated device, a thin oxygen layer is formed on the surface of the SGT device in the process of removing thick oxygen in a low-voltage device region to form gate oxygen of the MOS device in the region, so that the damage of the gate oxygen of the SGT device caused by errors in the etching process when the gate polysilicon of the SGT device is formed by etching is compensated, and the problem of leakage of the SGT device is avoided, namely the performance of the device is improved.
In addition, the invention provides a method for synchronously producing the SGT separation device and the BCD power IC device on the same chip, thereby avoiding the problem of larger parasitic Rs and Rc between the SGT separation device and the BCD power IC device caused by bonding the SGT separation device and the BCD power IC device after the SGT separation device and the BCD power IC device are respectively formed step by step in the prior art.
Drawings
Fig. 1 is a flow chart illustrating a method of manufacturing a semiconductor integrated device according to an embodiment of the present invention;
fig. 2a to fig. 2d are schematic structural diagrams of a method for manufacturing a semiconductor integrated device according to an embodiment of the present invention in a manufacturing process.
Wherein, the reference numerals are as follows:
A 100-semiconductor substrate, a 110-epitaxial layer;
an A-SGT device region;
A C-low voltage device region, a 101-trench isolation structure;
DPW-P type deep well, LVNW-low voltage N well;
HVNW-high voltage N-well, 102-gate trench;
103-a pressure-resistant groove, 120-a first oxide layer;
130-source polysilicon, 140-isolation layer;
150-second oxide layer, 160-grid polysilicon;
170 photoresist layer and 180 third oxide layer.
Detailed Description
As described in the background art, a high-voltage device and a low-voltage device are often integrated in the BCD device, for example, the high-voltage device may be an LDMOS device, a high-voltage JFET device, etc., and the low-voltage device may be a low-voltage MOS device, etc. The split gate or shielded gate MOSFET is an improved UMOS device, and has faster switching speed and lower switching loss compared with UMOS. The structure according to poly is divided into up-down (UD SGT) and left-right (LR SGT). The SGT device utilizes a charge balance principle to reduce on-resistance by properly increasing the doping concentration of an epitaxial layer, and utilizes a shielding gate to reduce Cgd/Ciss and improve Dv/dt capacity.
Currently, the SGT separation device and BCD device of Power IC (Power IC) on the market are commonly produced separately and then packaged together to form a module. Therefore, in the high-end application field, the module formed by the method has the following problems that 1, the SGT separation device and the Power IC device of the BCD are connected through bonding wire, so that parasitic Rs and Rc are relatively large, and 2, the SGT separation device and the PowerIC device of the BCD are produced in an asynchronous manner, so that the performance matching degree of the SGT separation device and the BCD is not high.
Therefore, the invention provides a manufacturing method of a semiconductor integrated device, which is used for providing a novel manufacturing method for integrating an SGT device and a BCD device into a same chip, and simultaneously solving the problem of low reliability of gate oxide of the device caused by over-etching of gate oxide of the SGT device in the process of forming gate polysilicon by etching the SGT device.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor integrated device according to an embodiment of the present invention, where the method for manufacturing a semiconductor integrated device may include the following steps:
Step S100, providing a semiconductor substrate, wherein the semiconductor substrate comprises an SGT device area, a low-voltage device area and a high-voltage device area which are sequentially arranged side by side, the low-voltage device area comprises a PMOS area and an NMOS area, the high-voltage device area comprises an NLDMOS area and a PLDMOS area, a plurality of groove isolation structures for isolating each device structure in the SGT device area, the low-voltage device area and the high-voltage device area are formed on the semiconductor substrate, and the top surface of each groove isolation structure is higher than the top surface of the semiconductor substrate;
Step S200, forming a gate trench, a voltage-resistant trench, a first oxide layer, a source polysilicon, an isolation layer, a second oxide layer and a gate polysilicon filled in the gate trench in the semiconductor substrate corresponding to the SGT device region, wherein the source polysilicon further fills the voltage-resistant trench, the gate polysilicon covers the surface of the isolation layer and at least fills the remaining gate trench, and further extends to cover the source polysilicon in the voltage-resistant trench and the surface of the semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region, and the second oxide layer further extends to cover the surface of the semiconductor substrate between adjacent trench isolation structures;
Step S300, etching back the gate polysilicon until the gate polysilicon remained in the pressure-resistant groove and the gate groove is flush with the surface of the second oxide layer remained after the etching back;
And step 400, forming a third oxide layer on the surface of the semiconductor substrate, wherein the third oxide layer covers the surface of the rest second oxide layer and extends to cover the surface of the semiconductor substrate corresponding to the space between two adjacent trench isolation structures in the low-voltage device region.
That is, in the method for manufacturing a semiconductor integrated device according to the present invention, a thin oxygen layer is formed on the surface of the SGT device during the process of removing the thick oxygen in the low voltage device region to form the gate oxide of the MOS device in the region, so as to compensate for the damage of the gate oxide of the SGT device caused by the error in the etching process when the gate polysilicon of the SGT device is formed by etching, thereby avoiding the problem of leakage of the SGT device, that is, improving the performance of the device. In addition, the invention provides a method for synchronously producing the SGT separation device and the BCD power IC device on the same chip, thereby avoiding the problem of larger parasitic Rs and Rc between the SGT separation device and the BCD power IC device caused by bonding the SGT separation device and the BCD power IC device after the SGT separation device and the BCD power IC device are respectively formed step by step in the prior art.
The method for manufacturing the semiconductor integrated device according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than as described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.
As used in the specification and in the claims, the terms "a," "an," "the," and/or "the" are not specific to a singular, but may include a plurality, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus. In describing embodiments of the present application in detail, the cross-sectional view of the device structure is not partially exaggerated to a general scale for convenience of explanation, and the schematic drawings are only examples and should not limit the scope of the present application herein. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Fig. 2a to fig. 2d are schematic structural diagrams of a method for manufacturing a semiconductor integrated device according to an embodiment of the present invention during a manufacturing process.
In step S100, referring specifically to fig. 2a, a semiconductor substrate 100 is provided, where the semiconductor substrate includes an SGT device region a, a low voltage device region C, and a high voltage device region B, which are sequentially arranged side by side, where the low voltage device region C may include one or more PMOS regions and NMOS regions, i.e., the low voltage device region C is a device region including a plurality of CMOS transistors, and an operating voltage of the CMOS transistors in the device region may be 5V, and the high voltage device region B may include one or more NLDMOS regions and a PLDMOS region, i.e., the high voltage device region B is a device region including a plurality of LDMOS transistors. Further, a plurality of trench isolation structures 101 for isolating each device structure in the SGT device region a, the low voltage device region C, and the high voltage device region B may be formed on the semiconductor substrate 100, and a top surface of the trench isolation structures 101 is higher than a top surface of the semiconductor substrate.
In this embodiment, a semiconductor substrate, such as the semiconductor substrate 100 shown in fig. 2a, is first provided, where the semiconductor substrate 100 may be any suitable substrate known in the art, for example, at least one of silicon (Si), germanium (Ge), germanium silicon (SiGe), carbon Silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, a multilayer structure including these semiconductors, or the like, or may be a double-sided polished silicon wafer (Double Side Polished Wafers, DSP), a ceramic substrate such as alumina, quartz, or glass substrate, or the like. The semiconductor substrate 100 in this embodiment is, for example, a silicon wafer.
Thereafter, an N-type doped epitaxial layer (Nepi) 110 may be formed on the surface of the N-type doped silicon substrate 100 using a combination of an epitaxial process and a doping process with respect to the N-type doped silicon substrate 100. Further, after the N-type doped epitaxial layer (Nepi) 110 is formed, the semiconductor substrate 100 may be subjected to multi-step ion implantation to form a plurality of P-type deep wells and N-type wells in the N-type doped epitaxial layer (Nepi), and the specific forming steps may be referred to as follows:
Step S101, performing a first ion implantation process on the semiconductor substrate 100 corresponding to the PMOS region, the NMOS region, the NLDMOS region, and the PLDMOS region, so as to form at least three P-type deep wells DPW in the low-voltage device region C and the high-voltage device region B;
In step S102, a second ion implantation process is performed on the semiconductor substrate 100 corresponding to the P-type deep well DPW, so as to form a plurality of high-voltage N-wells HVNW in the high-voltage device region B and a plurality of low-voltage N-wells LVNW in the low-voltage device region C.
In this embodiment, as can be seen from the above steps S101 and S102, the MOS transistors in the high-voltage device region B and the low-voltage device region C are distinguished by being formed in different N-type wells, which is the prior art, and the present invention will not be described in detail.
Further, after the N-well LVNW is formed in the step S102, a plurality of shallow trenches may be formed in the semiconductor substrate 100 by using an etching process, and then each of the shallow trenches is filled with silicon dioxide, so as to form the trench isolation structure 101 for isolating the MOS transistors included in the SGT device region a, the low-voltage device region C, the high-voltage device region B, and the low-voltage device region C and the high-voltage device region B.
In step S200, as shown in fig. 2a, a gate trench 102, a voltage-resistant trench 103, and a first oxide layer 120, a source polysilicon 130, an isolation layer 140, a second oxide layer 150, and a gate polysilicon 160 filled in the gate trench 102 are formed in the semiconductor substrate 100 corresponding to the SGT device region a. The source polysilicon 130 further fills the voltage-resistant trench 103, the gate polysilicon 160 covers the surface of the isolation layer 140 and at least fills the remaining gate trench 102, and further extends to cover the surface of the semiconductor substrate 100 corresponding to the source polysilicon 130 and the low-voltage device region C and the high-voltage device region B in the voltage-resistant trench 103, and the second oxide layer 150 further extends to cover the surface of the semiconductor substrate 100 between the adjacent trench isolation structures 101.
In this embodiment, a hard mask layer (not shown) may be formed on the surface of the semiconductor substrate 100 before the step S102, where the hard mask layer covers the entire surface of the semiconductor substrate 100 corresponding to the low-voltage device region B and the high-voltage device region C, and exposes a plurality of places in the SGT device region a, and further, with the hard mask layer as a mask, a plurality of gate trenches 102 and a voltage-resistant trench 103 may be formed in the SGT device region a, where the gate trenches 102 are used to form SGT devices with upper and lower structures in the SGT device region a, and the voltage-resistant trench 103 is used to form a voltage-resistant device serving as a field-stop region in the SGT device region a to improve the voltage-resistant performance of the SGT devices. And the hard mask layer can be an ONO laminated structure composed of silicon dioxide, silicon nitride or oxide-nitride-oxide. Illustratively, in an embodiment of the present invention, the hard mask layer may be an ONO stack structure.
Further, after forming a plurality of gate trenches 102 and a voltage-resistant trench 103 in the SGT device region a, a thick oxide layer 120 with a certain thickness may be formed on the bottom and the sidewall of the gate trench 102 and the voltage-resistant trench 103 by using a deposition process, then the gate trench 102 and the voltage-resistant trench 103 are filled with source polysilicon 130, so that the top surfaces of the filled gate trench 102 and the voltage-resistant trench 103 are flush with the top surface of the semiconductor substrate 100, then a photoresist layer (not shown) shielding the surface of the semiconductor substrate 100 corresponding to the voltage-resistant trench 103, the low-voltage device region C, and the high-voltage device region B is formed, and then the first oxide layer 120 and the source polysilicon 130 formed in the region corresponding to the gate trench 102 of the SGT device region a that is not shielded (exposed) by using an etching process are etched back, so as to form a first oxide layer 120 and a source polysilicon 130 with the surface in the partial height of the bottom of the gate process 102, then the first oxide layer 120 and the source polysilicon 130 are flush with the top surface of the semiconductor substrate 100, and then the surface of the second oxide layer 140 is formed to cover the surface of the semiconductor substrate 100 in the gate trench 101 and the surface of the second oxide layer (the gate trench) is formed to be flush with the surface of the second oxide layer 140. Thereafter, a gate polysilicon 160 is formed overlying the surface of the isolation layer 140 and filling at least the remaining gate trench 102, and also extending overlying the source polysilicon 130 in the voltage-resistant trench 103 and the surface of the semiconductor substrate 100 corresponding to the low-voltage device region B and the high-voltage device region C, as shown in fig. 2 a. The gate polysilicon 160 may be polished to a partial thickness by a CMP process after the deposition process.
It should be noted that, in the embodiment of the present invention, all identifiers that identify the same film layer are identified by the same identifier no matter how they are changed, which is to clearly identify each film layer and effectively distinguish each film layer from other film layers, but in other embodiments, different states of the same identifier, for example, 120', 120″ may also be used to identify states of the same film layer after different semiconductor process flows, which is not particularly limited to this embodiment.
In step S300, referring specifically to fig. 2b, the gate polysilicon 160 is etched back until the remaining gate polysilicon 160 in the voltage-resistant trench 103 and the gate trench 102 is flush with the surface of the second oxide layer 150 remaining after the etching back.
In this embodiment, the present inventors found that during the process of etching back the gate polysilicon 160, a part of the thickness of the second oxide layer 150 is also etched back, so that the gate oxide layer (i.e. the second oxide layer 150) of the SGT device is damaged, as shown in the portion D circled in fig. 2 b. Therefore, this will cause the problem of leakage and low performance for the SGT device formed by integration, based on which the present inventors propose a method of forming the gate oxide of the MOS device in the low-voltage device region C (i.e., the second oxide layer 150 covering the region) by removing the thick oxygen in the region (i.e., the third oxide layer 180 formed in the subsequent step) while forming a thin oxygen layer on the surface of the SGT device, so as to compensate for the damage of the gate oxide of the SGT device caused by the error in the etching process when the gate polysilicon of the SGT device is formed, thereby avoiding the problem of leakage of the SGT device, i.e., improving the performance of the device.
In addition, as can be seen from the above steps, in the embodiment of the present invention, a method for synchronously producing an SGT separation device and a BCD power IC device on the same chip is provided, so that the problem in the prior art that parasitic Rs and Rc between the two devices are relatively large due to bonding connection after the devices are required to be formed step by step respectively is avoided, and performance matching degree of the SGT device and the BCD device is provided.
In step S400, referring specifically to fig. 2C and 2d, a third oxide layer 180 is formed on the surface of the semiconductor substrate 100, and the third oxide layer 180 covers the surface of the remaining second oxide layer 150 and extends to cover the surface of the semiconductor substrate 100 corresponding to between two adjacent trench isolation structures 101 in the low-voltage device region C.
In this embodiment, as shown in fig. 2C, a photoresist layer 170 may be formed on the structure formed in the step S300, where the photoresist layer 170 exposes the semiconductor substrate 100 corresponding to the low-voltage device region C, and then an etching and removing process of the second oxide layer 150 is performed on the region, for example, a dry etching process, a wet etching process, or a mixed process of the two processes, and then the photoresist layer 170 is removed, and a third oxide layer 180 is formed. Specifically, the process can be described by the following steps:
Step S401, specifically as shown in fig. 2C, of forming a photoresist layer 170 for shielding the semiconductor substrate 100 corresponding to the SGT device region a and the high voltage device region B, exposing the semiconductor substrate 100 corresponding to the low voltage device region C, and etching to remove the second oxide layer 150 formed in the low voltage device region C by using the photoresist layer 170 as a mask;
In step S402, a third oxide layer 180 is formed on the surface of the semiconductor substrate 100 exposed between two adjacent trench isolation structures 101 in the low-voltage device region C from which the second oxide layer 150 is removed. Wherein the photoresist layer 170 is removed first, the process of forming the third oxide layer 180 may include a thermal oxidation process. In other embodiments, a deposition process is also possible. Because the third oxide layer 180 formed in the present invention not only covers the surface of the semiconductor substrate 100 between two adjacent trench isolation structures 101 in the low-voltage device region C, but also serves as gate oxide of a MOS transistor device formed subsequently in the region, and simultaneously covers the third oxide layer 180 in the SGT device region a in the process of this step, thereby compensating for the damage of gate oxide of the SGT device caused by errors in the etching process when the gate polysilicon 160 of the SGT device is formed by etching, and further avoiding the problem of leakage of the SGT device, that is, improving the performance of the device, and achieving the purpose of the present invention.
Further, in an embodiment of the present invention, after forming the third oxide layer 180, the manufacturing method may further include the steps of:
In step S403, a gate material layer (not shown) is formed, and the gate material layer (not shown) is covered on the entire surface of the semiconductor substrate 100, and is etched to form corresponding gate structures in the low-voltage device region C and the high-voltage device region B.
In the embodiment of the present invention, the forming process in this step is the prior art, so this will not be specifically described in the present invention. Illustratively, in an embodiment of the present invention, the materials of the isolation layer, the first oxide layer, the second oxide layer, and the third oxide layer may all include silicon dioxide.
In summary, in the method for manufacturing a semiconductor integrated device provided by the present invention, a thin oxygen layer is formed on the surface of the SGT device during the process of removing the thick oxygen in the low-voltage device region to form the gate oxide of the MOS device in the region, so as to compensate the damage of the gate oxide of the SGT device caused by the error in the etching process when the gate polysilicon of the SGT device is formed by etching, thereby avoiding the problem of leakage of the SGT device, that is, improving the performance of the device. In addition, the invention provides a method for synchronously producing the SGT separation device and the BCD power IC device on the same chip, thereby avoiding the problem of larger parasitic Rs and Rc between the SGT separation device and the BCD power IC device caused by bonding the SGT separation device and the BCD power IC device after the SGT separation device and the BCD power IC device are respectively formed step by step in the prior art.
It should be noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.
It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary. Furthermore, implementation of the methods and/or apparatus in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.
Claims (10)
1. A method of manufacturing a semiconductor integrated device, comprising at least the steps of:
Providing a semiconductor substrate, wherein the semiconductor substrate comprises an SGT device region, a low-voltage device region and a high-voltage device region which are sequentially arranged side by side, the low-voltage device region comprises a PMOS region and an NMOS region, the high-voltage device region comprises an NLDMOS region and a PLDMOS region, a plurality of groove isolation structures for isolating each device structure in the SGT device region, the low-voltage device region and the high-voltage device region are formed on the semiconductor substrate, and the top surface of each groove isolation structure is higher than the top surface of the semiconductor substrate;
Forming a gate trench, a voltage-resistant groove, a first oxide layer, source polycrystalline silicon, an isolation layer, a second oxide layer and gate polycrystalline silicon which are filled in the gate trench in the semiconductor substrate corresponding to the SGT device region, wherein the source polycrystalline silicon also fills the voltage-resistant groove, the gate polycrystalline silicon covers the surface of the isolation layer and at least fills the rest of the gate trench, the source polycrystalline silicon in the voltage-resistant groove and the surfaces of the semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region are also covered, and the second oxide layer also extends to cover the surfaces of the semiconductor substrate between adjacent trench isolation structures;
Etching the gate polysilicon back until the gate polysilicon remained in the pressure-resistant groove and the gate groove is flush with the surface of the second oxide layer remained after the etching back;
removing the first oxide layer located in the low-voltage device region;
And forming a third oxide layer on the surface of the semiconductor substrate, wherein the third oxide layer covers the surface of the rest second oxide layer and extends to cover the surface of the semiconductor substrate corresponding to the space between two adjacent groove isolation structures in the low-voltage device region.
2. The method of manufacturing a semiconductor integrated device as recited in claim 1, wherein during the etching back of the gate polysilicon, a portion of the second oxide layer is etched back simultaneously, thereby causing loss of the gate oxide layer of the SGT device.
3. The method for manufacturing a semiconductor integrated device according to claim 1, wherein after forming the gate trench, the withstand voltage trench, the manufacturing method further comprises:
Performing a first ion implantation process on the semiconductor substrate corresponding to the PMOS region, the NMOS region, the NLDMOS region and the PLDMOS region to form at least three P-type deep wells in the low-voltage device region and the high-voltage device region;
and performing a second ion implantation process on the semiconductor substrate corresponding to the P-type deep well to form a plurality of high-voltage N wells in the high-voltage device region and a plurality of low-voltage N wells in the low-voltage device region.
4. The method for manufacturing a semiconductor integrated device according to claim 3, wherein the step of forming the first oxide layer, the source polysilicon, the spacer layer, the second oxide layer, and the gate polysilicon in the gate trench comprises:
Forming a first oxide layer on the inner walls of the pressure-resistant groove and the gate groove, and filling source polycrystalline silicon in the pressure-resistant groove and the gate groove after the first oxide layer is formed so that the top surface of the filled source polycrystalline silicon is flush with the upper surface of the semiconductor substrate;
Masking the surface of the semiconductor substrate corresponding to the pressure-resistant groove, and etching back the source polycrystalline silicon and the first oxide layer in the grid groove to form a shielding grid and a thick oxide layer of the SGT device area in the grid groove, then forming an isolation layer on the top surfaces of the source polycrystalline silicon and the first oxide layer after etching back, and covering the surface of the isolation layer and the second oxide layer on the inner wall of the residual grid groove, wherein the second oxide layer also extends to cover the surface of the rest of exposed semiconductor substrate.
5. The method of manufacturing a semiconductor integrated device according to claim 4, wherein the remaining exposed semiconductor substrate surface covered by the second oxide layer extension includes a surface of the semiconductor substrate corresponding between two adjacent trench isolation structures in the low voltage device region.
6. The method for manufacturing a semiconductor integrated device according to claim 5, wherein after etching back the gate polysilicon and before forming the third oxide layer, the method further comprises:
forming a photoresist layer which shields the semiconductor substrate corresponding to the SGT device region and the high-voltage device region, exposing the semiconductor substrate corresponding to the low-voltage device region, and etching to remove a second oxide layer formed in the low-voltage device region by taking the photoresist layer as a mask;
A third oxide layer is formed on the surface of the semiconductor substrate exposed between two adjacent trench isolation structures in the low voltage device region from which the second oxide layer is removed.
7. The method for manufacturing a semiconductor integrated device according to claim 6, wherein the process of forming the third oxide layer includes a thermal oxidation process.
8. The method of manufacturing a semiconductor integrated device according to claim 1, wherein the step of forming the trench isolation structure comprises:
and forming a plurality of shallow trenches in the semiconductor substrate, and filling the shallow trenches to form the trench isolation structure for isolating the SGT device region, the low-voltage device region, the high-voltage device region and each MOS tube contained in the low-voltage device region and the high-voltage device region.
9. The method for manufacturing a semiconductor integrated device according to claim 1, wherein after the third oxide layer is formed, the method further comprises:
and forming a gate material layer, wherein the gate material layer covers the whole surface of the semiconductor substrate, and etching the gate material layer to form corresponding gate structures in the low-voltage device region and the high-voltage device region.
10. The method for manufacturing a semiconductor integrated device according to claim 1, wherein materials of the isolation layer, the first oxide layer, the second oxide layer, and the third oxide layer include silicon dioxide.
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| CN118471979B (en) * | 2024-07-10 | 2024-09-10 | 杭州致善微电子科技有限公司 | Metal oxide field effect power transistor based on BCD integration and process |
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| CN102097327A (en) * | 2009-12-02 | 2011-06-15 | 万国半导体股份有限公司 | Dual channel trench LDMOS transistors and BCD process with deep trench isolation |
| CN115064445A (en) * | 2022-08-11 | 2022-09-16 | 广州粤芯半导体技术有限公司 | Preparation method of semiconductor structure and transistor with shielded gate trench structure |
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| CN102097327A (en) * | 2009-12-02 | 2011-06-15 | 万国半导体股份有限公司 | Dual channel trench LDMOS transistors and BCD process with deep trench isolation |
| CN115064445A (en) * | 2022-08-11 | 2022-09-16 | 广州粤芯半导体技术有限公司 | Preparation method of semiconductor structure and transistor with shielded gate trench structure |
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