CN118197393B - Chip and starting method and device thereof - Google Patents
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Abstract
The invention discloses a chip and a starting method and a device thereof, wherein the chip comprises a processor and a starting control module which are mutually connected, the processor is correspondingly provided with an SRAM module, and the starting method of the chip comprises the following steps: downloading the test program to the SRAM module when the processor receives the reset signal, releasing the reset signal after the downloading is completed, and starting the processor; receiving a starting mode selection instruction through a starting control module, so that the processor reads an initial value of a main stack pointer and a starting address of a test program according to the starting mode selection instruction; and when the reading is finished, the processor is controlled to execute the test program stored in the SRAM module, so that the processor can be controlled to execute the program in the SRAM module, and further, the test time can be saved and the test cost can be reduced.
Description
Technical Field
The present invention relates to the field of chip design and test technologies, and in particular, to a method for starting a chip, a device for starting a chip, and a chip.
Background
In mass production testing of integrated circuits, a test program is generally downloaded to an on-chip SRAM (Static Random-Access Memory) or a nonvolatile Memory cell Flash, and the test is performed by a CPU (Central Processing Unit) core, however, downloading the test program to the nonvolatile Memory cell Flash results in a long test time, and programming and erasing operations are required for the nonvolatile Memory cell Flash.
For the microcontroller chip based on ARM company, after the microcontroller chip is powered on or reset, the CPU core first reads out the address of the main stack pointer and the entry function address (reset vector, i.e. the starting position of program execution) from the interrupt vector table, and the interrupt vector table is stored at the address 32' h00000000 of the nonvolatile Memory unit Flash or ROM (Read-Only Memory) Memory unit, so that the code can Only be executed from the nonvolatile Memory unit Flash or ROM Memory unit, if the code is executed from the SRAM, the CPU needs to be additionally configured, and thus the test time and the test cost can be increased.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, a first objective of the present invention is to provide a method for starting a chip, which can control a processor to execute a program in an SRAM module by reading an initial value of a main stack pointer and a start address of a test program according to a start mode selection instruction, so as to save test time and reduce test cost.
A second object of the present invention is to provide a chip starting device.
A third object of the present invention is to propose a chip.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a method for starting a chip, where the chip includes a processor and a start control module that are connected to each other, the processor is correspondingly provided with an SRAM module, and the method includes: downloading a test program into the SRAM module when the processor receives a reset signal, and releasing the reset signal and starting the processor after the test program is downloaded; receiving a starting mode selection instruction through the starting control module, so that the processor reads an initial value of a main stack pointer and a starting address of a test program according to the starting mode selection instruction; and when the processor reads the initial value of the main stack pointer and the starting address of the test program, controlling the processor to execute the test program stored in the SRAM module.
According to the starting method of the chip, the initial value of the main stack pointer and the starting address of the test program are read by the processor according to the starting mode selection instruction, so that the processor can be controlled to execute the program in the SRAM module, the test time can be saved, and the test cost can be reduced.
In addition, the method for starting the chip according to the above embodiment of the present invention may further include the following additional technical features:
According to one embodiment of the present invention, the start control module includes a first channel selector and a finger fetch counter, and the receiving, by the start control module, a start mode selection instruction, so that the processor reads an initial value of a main stack pointer and a start address of a test program according to the start mode selection instruction, includes: when the instruction fetch counter receives the starting mode selection instruction, acquiring a mark signal sent by the processor through the instruction fetch counter, so that the instruction fetch counter sends counting state information to the first channel selector according to the mark signal, wherein the first channel selector sends a corresponding selection signal to the processor according to the counting state information after receiving the counting state information, and the selection signal comprises address information corresponding to an initial value of the main stack pointer and address information corresponding to a starting address of the test program.
According to one embodiment of the present invention, the count state information includes first count state information and second count state information, and the first channel selector sends a corresponding selection signal to the processor according to the count state information, including: when the count state information is the first count state information, the first channel selector sends address information corresponding to an initial value of the main stack pointer to the processor; and when the counting state information is the second counting state information, the first channel selector sends address information corresponding to the starting address of the test program to the processor.
According to one embodiment of the invention, the start control module further comprises a second channel selector, and the second channel selector is respectively connected with the finger fetch counter and the processor.
According to one embodiment of the present invention, the finger counter further sends the count state information to the second channel selector according to the flag signal, so that the second channel selector outputs transmission state information to the processor according to the count state information.
According to one embodiment of the present invention, the second channel selector outputs transmission state information to the processor according to the count state information, including: and when the counting state information is the first counting state information or the second counting state information, the second channel selector outputs transmission completion information to the processor.
According to one embodiment of the present invention, the finger counter further performs a zero clearing process after transmitting a preset count state information to the first channel selector.
According to one embodiment of the invention, the processor is Cortex-M4.
According to one embodiment of the present invention, the start control module includes a third channel selector, and the receiving, by the start control module, a start mode selection instruction, so that the processor reads an initial value of a main stack pointer and a start address of a test program according to the start mode selection instruction, includes: when the third channel selector receives the starting mode selection instruction, the first address information and the second address information of the SRAM module are sent to the processor, so that the processor reads the initial value of the main stack pointer according to the first address information of the SRAM and reads the starting address of the test program according to the second address information of the SRAM.
According to one embodiment of the invention, the processor is Cortex-M0.
According to one embodiment of the invention, the method further comprises: and downloading the test program into the SRAM module through JTAG protocol.
In order to achieve the above object, an embodiment of a second aspect of the present invention provides a device for starting a chip, where the chip includes a processor and a start control module that are connected to each other, the processor is correspondingly provided with an SRAM module, and the device includes: the control module is used for downloading a test program into the SRAM module when the processor receives a reset signal, releasing the reset signal and starting the processor after the test program is downloaded; the receiving module is used for receiving a starting mode selection instruction through the starting control module so that the processor reads an initial value of a main stack pointer and a starting address of a test program according to the starting mode selection instruction; and the control module is further used for controlling the processor to execute the test program stored in the SRAM module when the processor reads the initial value of the main stack pointer and the initial address of the test program.
According to the starting device of the chip, the initial value of the main stack pointer and the starting address of the test program are read by the processor according to the starting mode selection instruction, so that the processor can be controlled to execute the program in the SRAM module, the test time can be saved, and the test cost can be reduced.
In order to achieve the above object, an embodiment of a third aspect of the present invention provides a chip, which is activated by the activation device of the chip of the above embodiment when the chip is in a test mode.
According to the chip provided by the embodiment of the invention, the starting device of the chip provided by the embodiment of the invention is adopted, and the initial value of the main stack pointer and the initial address of the test program are read by the processor according to the starting mode selection instruction, so that the processor can be controlled to execute the program in the SRAM module, the test time can be saved, and the test cost can be reduced.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic diagram of a chip structure according to one embodiment of the invention;
FIG. 2 is a schematic diagram of a chip according to another embodiment of the invention;
FIG. 3 is a flow chart of a method for starting a chip according to an embodiment of the invention;
FIG. 4 is a block diagram of an activation device of a chip according to an embodiment of the present invention;
Fig. 5 is a block diagram of a chip according to an embodiment of the invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
The method for starting the chip, the device for starting the chip, and the chip according to the embodiments of the present invention are described below with reference to the accompanying drawings.
Before describing the method and apparatus for starting the chip of the present invention, a corresponding description will be given of the chip of the present invention, and as shown in fig. 1 and 2, the chip 1000 includes a processor 10 and a start control module 20 that are connected to each other, where the processor 10 is correspondingly provided with an SRAM module.
As shown in fig. 1, when the processor 10 is Cortex-M4, the start control module 20 includes a first channel selector 21, a second channel selector 22, and a finger counter 23, where the second channel selector 22 is connected to the finger counter 23 and the processor 10, respectively.
As shown in fig. 2, when the processor 10 is Cortex-M0, the start control module 20 includes a third channel selector 24.
Fig. 3 is a flowchart of a method for starting a chip according to an embodiment of the invention.
Specifically, in some embodiments of the present invention, as shown in fig. 3, a chip includes a processor and a start control module that are connected to each other, where the processor is correspondingly provided with an SRAM module, and the method for starting the chip includes:
s101, when the processor receives the reset signal, downloading the test program into the SRAM module, and releasing the reset signal and starting the processor after the test program is downloaded.
Specifically, in this embodiment, when the processor receives the reset signal, the processor resets and downloads the test program to the SRAM module through the JTAG (Joint Test Action Group, joint test action organization) protocol, and it should be noted that the reset signal is a low level signal at this time. And releasing the reset signal after the test program is downloaded, and changing the reset signal from a low level signal to a high level signal at the moment, and controlling the processor to start through the high level signal.
S102, receiving a starting mode selection instruction through a starting control module, so that the processor reads the initial value of the main stack pointer and the starting address of the test program according to the starting mode selection instruction.
Specifically, in this embodiment, when the processor is Cortex-M4, the start control module includes a first channel selector and an instruction fetch counter, and when the instruction fetch counter receives a start mode selection instruction, the instruction fetch counter obtains a flag signal sent by the processor, so that the instruction fetch counter sends count state information to the first channel selector according to the flag signal, where the first channel selector sends a corresponding selection signal to the processor according to the count state information after receiving the count state information, where the selection signal includes address information corresponding to an initial value of a main stack pointer and address information corresponding to a start address of a test program.
When the processor is Cortex-M0, the starting control module comprises a third channel selector, and when the third channel selector receives a starting mode selection instruction, the first address information and the second address information of the SRAM module are sent to the processor, so that the processor reads an initial value of a main stack pointer according to the first address information of the SRAM and reads a starting address of a test program according to the second address information of the SRAM.
S103, when the processor reads the initial value of the main stack pointer and the initial address of the test program, the processor is controlled to execute the test program stored in the SRAM module.
Specifically, in this embodiment, when the processor is Cortex-M4, as shown in fig. 1, after the first channel selector 21 sends the information 32' h2001fff0 corresponding to the first count state information 2' b01 as a selection signal to the processor 10, the first channel selector 21 sends the address information 32' h2001fff0 corresponding to the initial value of the main stack pointer to the processor 10, and after the first channel selector 21 sends the information 32' h20000001 corresponding to the second count state information 2' b10 as a selection signal to the processor 10, the first channel selector 21 sends the address information 32' h20000001 corresponding to the start address of the test program to the processor 10, and then directs the processor 10 to execute the test program stored in the SRAM module with the 32' h2000_0001 as the start address of the test program.
When the processor 10 is Cortex-M0, as shown in fig. 2, when the third channel selector 24 receives the Boot mode selection instruction boot_from_ram as a high level signal, the third channel selector 24 transmits the interrupt vector table address 24'h1fffc0 in the test mode corresponding to the high level signal to the processor 10, wherein the interrupt vector table address 24' h1fffc0 includes the first address information 32'h1fffc000 and the second address information 32' h1fffc004 of the SRAM module. After receiving the first address information 32'h1fffc000 and the second address information 32' h1fffc004 of the SRAM module, the processor 10 may begin to take a finger from the first address information 32'h1fffc000, thereby reading the initial value 32' h20003ff0 of the main stack pointer, and then begin to take a finger from the second address information 32'h1fffc004, thereby reading the start address 32' h1fffc101 of the test program. The 32' h1fffc101 is used as the start address of the test program to control the processor 10 to execute the test program stored in the SRAM module.
Further, in some embodiments of the present invention, the start control module includes a first channel selector and a finger counter, and receives a start mode selection instruction through the start control module, so that the processor reads an initial value of a main stack pointer and a start address of a test program according to the start mode selection instruction, including: when the instruction fetch counter receives a starting mode selection instruction, the instruction fetch counter acquires a sign signal sent by the processor, so that the instruction fetch counter sends counting state information to the first channel selector according to the sign signal, wherein the first channel selector sends a corresponding selection signal to the processor according to the counting state information after receiving the counting state information, and the selection signal comprises address information corresponding to an initial value of a main stack pointer and address information corresponding to a starting address of a test program.
Specifically, in this embodiment, as shown in fig. 1, the counting state information includes a first counting state information 2'b0 and a second counting state information 2' b10, when the processor 10 is Cortex-M4, the start control module 20 includes a first channel selector 21, a second channel selector 22 and a finger taking counter 23, wherein the second channel selector 22 is respectively connected to the finger taking counter 23 and the processor 10, when the finger taking counter 23 receives a start mode selection command boot_from_ram as a high level signal, the processor 10 starts to start to enter a test mode, the processor 10 sends a flag signal HTRANSC to the finger taking counter 23, the finger taking counter 23 starts to count after receiving a flag signal HTRANSC, when the finger taking counter 23 counts once according to the flag signal HTRANSC, the finger taking counter 23 sends the first counting state information 2'b01 to the first channel selector 21, and when the finger taking counter 23 counts twice, the finger taking counter 23 sends the second counting state information 2' b10 to the first channel selector 21.
The first channel selector 21 sends address information 32'h2001fff0 corresponding to the initial value of the main stack pointer to the processor 10 after receiving the first count state information 2' b01, and the first channel selector 21 sends address information 32'h20000001 corresponding to the start address of the test program to the processor 10 after receiving the second count state information 2' b 10.
Further, in some embodiments of the present invention, the count state information includes first count state information and second count state information, and the first channel selector sends a corresponding selection signal to the processor according to the count state information, including: when the counting state information is first counting state information, the first channel selector sends address information corresponding to an initial value of the main stack pointer to the processor; when the counting state information is the second counting state information, the first channel selector sends address information corresponding to the starting address of the test program to the processor.
Specifically, in this embodiment, as shown in fig. 1, when the count state information is the first count state information 2'b01, the first channel selector 21 sends address information 32' h2001fff0 corresponding to the initial value of the main stack pointer to the processor 10 through the system read instruction bus HRDATAC [31:0 ]; when the count status information is the second count status information 2'b10, the first channel selector 21 sends the address information 32' h20000001 corresponding to the start address of the test program to the processor 10 through the system read command bus HRDATAC [31:0 ].
Further, in some embodiments of the present invention, the start control module further includes a second channel selector, where the second channel selector is connected to the finger fetch counter and the processor, and the finger fetch counter further sends count state information to the second channel selector according to the flag signal, so that the second channel selector outputs transmission state information to the processor according to the count state information.
Specifically, in this embodiment, as shown in fig. 1, the start control module 20 further includes a second channel selector 22, where the second channel selector 22 is respectively connected to the finger taking counter 23 and the processor 10, when the finger taking counter 23 counts once according to the flag signal HTRANSC, the finger taking counter 23 sends the first count state information 2'b01 to the second channel selector 22, and when the finger taking counter 23 counts twice, the finger taking counter 23 sends the second count state information 2' b10 to the second channel selector 22.
When the count state information is the first count state information 2'b01 or the second count state information 2' b10, the second channel selector 22 outputs the fixed value 1'b1 as the transmission completion information HREADYC and outputs 1' b1 as the transmission completion information HREADYC to the processor 10. The fixed value 1' b1 is a high level signal, and the address information corresponding to the initial value of the main stack pointer and the address information corresponding to the starting address of the test program are marked through the high level signal.
Further, in some embodiments of the present invention, the finger counter also performs a zero clearing process after sending a preset number of count status information to the first channel selector.
Specifically, in this embodiment, the finger counter further performs the zero clearing process after sending two pieces of count state information to the first channel selector, where the two pieces of count state information include the first count state information 2' b01 and the second count state information 2' b10, and after the finger counter is reset to perform the zero clearing process, the count state information of the finger counter is the third count state information 2' b00.
Further, in some embodiments of the present invention, the start control module includes a third channel selector, and the start control module receives a start mode selection instruction, so that the processor reads an initial value of the main stack pointer and a start address of the test program according to the start mode selection instruction, including: when the third channel selector receives a starting mode selection instruction, the first address information and the second address information of the SRAM module are sent to the processor, so that the processor reads an initial value of a main stack pointer according to the first address information of the SRAM and reads a starting address of a test program according to the second address information of the SRAM.
Specifically, in this embodiment, as shown in fig. 2, when the processor 10 is Cortex-M0, the start control module 20 includes the third channel selector 24, and when the third channel selector 24 receives the start mode selection command boot_from_ram as a high level signal, the processor 10 starts to start entering the test mode, the third channel selector 24 sends the interrupt vector table address 24'h1fffc0 to the processor 10 in the test mode corresponding to the high level signal, and it is noted that by setting the interrupt vector table address signal vtor _31to8[23:0] to 24' h1fffc0, the third channel selector 24 sends the interrupt vector table address signal vtor _31to8[23:0] to the processor 10. Wherein the interrupt vector table address 24' h1fffc0 includes first address information 32' h1fffc000 and second address information 32' h1fffc004 of the SRAM module.
After receiving the first address information 32'h1fffc000 and the second address information 32' h1fffc004 of the SRAM module, the processor 10 may begin to take a finger from the first address information 32'h1fffc000, thereby reading the initial value 32' h20003ff0 of the main stack pointer, and then begin to take a finger from the second address information 32'h1fffc004, thereby reading the start address 32' h1fffc101 of the test program.
Further, in some embodiments of the invention, the method further comprises: the test program is downloaded into the SRAM module via the JTAG protocol.
Specifically, in this embodiment, when the processor receives the reset signal, the test program is downloaded to the SRAM module through the JTAG protocol, and in addition, the method of downloading the test program to the SRAM module is not specifically limited, for example, the test program may also be downloaded to the SRAM module through a serial interface or a parallel bus interface.
To summarize, as shown in fig. 1, when the processor 10 is Cortex-M4 and the chip is in the test module, the processor 10 receives the reset signal HRESETn, where the reset signal HRESETn is a low level signal, and downloads the test program to the SRAM module through the JTAG protocol, and releases the reset signal HRESETn after the test program is downloaded, where the reset signal HRESETn is changed From the low level signal to a high level signal, so as to control the processor 10 to start, and controls the instruction fetch counter to start through the start mode selection instruction boot_from_ram, where the start mode selection instruction boot_from_ram is a high level signal, and is stored in the system control register or the test control register.
After the processor 10 is started, the processor 10 sends a flag signal HTRANSC to the finger counter 23, the finger counter 23 starts counting after receiving the flag signal HTRANSC, and when the finger counter 23 counts once according to the flag signal HTRANSC, the finger counter 23 sends the first count state information 2'b01 to the first channel selector 21, so that the first channel selector 21 sends address information 32' h2001fff0 corresponding to the initial value of the main stack pointer to the processor 10.
When the fetch counter 23 counts twice, the fetch counter 23 sends the second count status information 2'b10 to the first channel selector 21, so that the first pass selector 21 sends the address information 32' h20000001 corresponding to the start address of the test program to the processor 10.
The processor 10 may read the initial value 32' h2001fff0 of the main stack pointer according to the address information 32' h2001fff0 corresponding to the initial value of the main stack pointer, and read the start address 32' h20000001 of the test program according to the address information 32' h20000001 corresponding to the start address of the test program, so that after the processor 10 reads the initial value 32' h2001fff0 of the main stack pointer and the start address 32' h20000001 of the test program, the processor 10 may be controlled to execute the test program stored in the SRAM module, that is, take the address 32' h20000001 as the start address to perform the instruction fetching.
In addition, when the chip is in the user function mode, HRDATAC _from_bus [31:0] in fig. 1 is a system read command Bus in the user function mode, and HREADYC _from_bus is a system Bus transmission completion signal in the user function mode.
As shown in fig. 2, when the processor 10 is Cortex-M0 and the chip is in the test module, the processor 10 receives the reset signal HRESETn, where the reset signal HRESETn is a low level signal, and downloads the test program to the SRAM module through the JTAG protocol, and releases the reset signal HRESETn after the test program is downloaded, where the reset signal HRESETn is changed From the low level signal to a high level signal, and further controls the processor 10 to start, where the start mode selection command boot_from_ram is a high level signal and is input to the third channel selector 24, and the third channel selector 24 sends the interrupt vector table address 24'h1fffc0 corresponding to the high level signal to the processor 10 in the test mode, where the interrupt vector table address 24' h1fffc0 includes the first address information 32'h1fffc000 and the second address information 32' h1fffc004 of the SRAM module.
After receiving the first address information 32' h1fffc000 and the second address information 32' h1fffc004 of the SRAM module, the processor 10 may begin to fetch from the first address information 32' h1fffc000, thereby reading the initial value 32' h20003ff0 of the main stack pointer, then begin to fetch from the second address information 32' h1fffc004, thereby reading the initial address 32' h1fffc101 of the test program, and further after the processor 10 reads the initial value 32' h20003ff0 of the main stack pointer and the initial address 32' h1fffc101 of the test program, the processor 10 may be controlled to execute the test program stored in the SRAM module, that is, fetch with the address 32' h1fffc101 as the initial address.
In addition, nvm _ vtor _31to8_i [23:0] in FIG. 2 is the interrupt vector table address in user function mode when the chip is in user function mode.
In summary, according to the method for starting the chip of the embodiment of the present invention, the processor reads the initial value of the main stack pointer and the start address of the test program according to the start mode selection instruction, so as to control the processor to execute the program in the SRAM module, thereby saving the test time and reducing the test cost.
Fig. 4 is a block diagram of a chip start-up device according to an embodiment of the present invention.
Specifically, the chip includes a processor and a start control module that are connected to each other, and the processor is correspondingly provided with an SRAM module, as shown in fig. 4, and the start device 100 of the chip includes a control module 10 and a receiving module 20.
The control module 10 is configured to download the test program to the SRAM module when the processor receives the reset signal, and release the reset signal and start the processor after the test program is downloaded; the receiving module 20 is configured to receive a start mode selection instruction through the start control module, so that the processor reads an initial value of the main stack pointer and a start address of the test program according to the start mode selection instruction; the control module 10 is further configured to control the processor to execute the test program stored in the SRAM module when the processor reads the initial value of the main stack pointer and the start address of the test program.
In some embodiments of the present invention, the start control module includes a first channel selector and a finger counter, and the receiving module 20 is specifically configured to, when the finger counter receives a start mode selection instruction, obtain, by the finger counter, a flag signal sent by the processor, so that the finger counter sends count state information to the first channel selector according to the flag signal, where after receiving the count state information, the first channel selector sends, to the processor, a corresponding selection signal according to the count state information, where the selection signal includes address information corresponding to an initial value of a main stack pointer and address information corresponding to a start address of a test program.
In some embodiments of the present invention, the count state information includes first count state information and second count state information, and the receiving module 20 is specifically configured to send, when the count state information is the first count state information, address information corresponding to an initial value of the main stack pointer to the processor by the first channel selector; when the counting state information is the second counting state information, the first channel selector sends address information corresponding to the starting address of the test program to the processor.
In some embodiments of the invention, the start control module further comprises a second channel selector, the second channel selector being respectively connected to the finger counter and the processor.
In some embodiments of the invention, the finger counter further transmits count state information to the second channel selector based on the flag signal, such that the second channel selector outputs transmission state information to the processor based on the count state information.
In some embodiments of the invention, the second channel selector outputs the transmission state information to the processor based on the count state information, comprising: when the count state information is the first count state information or the second count state information, the second channel selector outputs transmission completion information to the processor.
In some embodiments of the present invention, the finger counter also performs a zero clearing process after sending a preset number of count state information to the first channel selector.
In some embodiments of the invention, the processor is Cortex-M4.
In some embodiments of the present invention, the start control module includes a third channel selector, and the receiving module 20 is specifically configured to send the first address information and the second address information of the SRAM module to the processor when the third channel selector receives the start mode selection instruction, so that the processor reads an initial value of the main stack pointer according to the first address information of the SRAM and reads a start address of the test program according to the second address information of the SRAM.
In some embodiments of the invention, the processor is Cortex-M0.
In some embodiments of the present invention, the test program is downloaded into the SRAM module via the JTAG protocol.
It should be noted that, for other specific embodiments of the chip starting device according to the embodiments of the present invention, reference may be made to the foregoing specific embodiments of the chip starting method according to the embodiments of the present invention, and in order to reduce redundancy, details are not repeated here.
In summary, according to the starting device of the chip of the embodiment of the invention, the processor reads the initial value of the main stack pointer and the starting address of the test program according to the starting mode selection instruction, so that the processor can be controlled to execute the program in the SRAM module, thereby saving the test time and reducing the test cost.
Fig. 5 is a block diagram of a chip according to an embodiment of the invention.
As shown in fig. 5, when the chip 1000 is in the test mode, the activation is performed by the activation device 100 of the chip of the above-described embodiment.
According to the chip provided by the embodiment of the invention, the starting device of the chip provided by the embodiment of the invention is adopted, and the initial value of the main stack pointer and the initial address of the test program are read by the processor according to the starting mode selection instruction, so that the processor can be controlled to execute the program in the SRAM module, the test time can be saved, and the test cost can be reduced.
In addition, other structures and functions of the chip according to the embodiments of the present invention are known to those skilled in the art, and are not described herein for redundancy reduction.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (13)
1. The method for starting the chip is characterized in that the chip comprises a processor and a starting control module which are connected with each other, wherein the processor is correspondingly provided with an SRAM module, and the method comprises the following steps:
downloading a test program into the SRAM module when the processor receives a reset signal, releasing the reset signal after the test program is downloaded, converting the reset signal from a low-level signal to a high-level signal, and starting the processor through the high-level signal;
receiving a starting mode selection instruction through the starting control module, so that the processor reads an initial value of a main stack pointer and a starting address of a test program according to the starting mode selection instruction;
and when the processor reads the initial value of the main stack pointer and the starting address of the test program, controlling the processor to execute the test program stored in the SRAM module.
2. The method according to claim 1, wherein the start control module includes a first channel selector and an instruction fetch counter, and the receiving, by the start control module, a start mode selection instruction, so that the processor reads an initial value of a main stack pointer and a start address of a test program according to the start mode selection instruction, including:
When the instruction fetch counter receives the starting mode selection instruction, acquiring a mark signal sent by the processor through the instruction fetch counter, so that the instruction fetch counter sends counting state information to the first channel selector according to the mark signal, wherein the first channel selector sends a corresponding selection signal to the processor according to the counting state information after receiving the counting state information, and the selection signal comprises address information corresponding to an initial value of the main stack pointer and address information corresponding to a starting address of the test program.
3. The method of claim 2, wherein the count state information includes first count state information and second count state information, and the first channel selector sends a corresponding selection signal to the processor according to the count state information, including:
When the count state information is the first count state information, the first channel selector sends address information corresponding to an initial value of the main stack pointer to the processor;
And when the counting state information is the second counting state information, the first channel selector sends address information corresponding to the starting address of the test program to the processor.
4. The method of claim 3, wherein the start control module further comprises a second channel selector, the second channel selector being respectively connected to the finger counter and the processor.
5. The method according to claim 4, wherein the finger counter further transmits the count state information to the second channel selector according to the flag signal, so that the second channel selector outputs transmission state information to the processor according to the count state information.
6. The method of starting up a chip according to claim 5, wherein the second channel selector outputs transmission state information to the processor according to the count state information, comprising:
And when the counting state information is the first counting state information or the second counting state information, the second channel selector outputs transmission completion information to the processor.
7. The method according to claim 2, wherein the finger counter further performs a zero clearing process after transmitting a preset count state information to the first channel selector.
8. The method of starting up a chip according to any one of claims 2-7, wherein the processor is Cortex-M4.
9. The method according to claim 1, wherein the start control module includes a third channel selector, and the receiving, by the start control module, a start mode selection instruction, so that the processor reads an initial value of a main stack pointer and a start address of a test program according to the start mode selection instruction, includes:
When the third channel selector receives the starting mode selection instruction, the first address information and the second address information of the SRAM module are sent to the processor, so that the processor reads the initial value of the main stack pointer according to the first address information of the SRAM and reads the starting address of the test program according to the second address information of the SRAM.
10. The method of claim 9, wherein the processor is Cortex-M0.
11. The method for starting up a chip according to claim 1, further comprising:
And downloading the test program into the SRAM module through JTAG protocol.
12. A starting device of a chip, wherein the chip comprises a processor and a starting control module which are connected with each other, the processor is correspondingly provided with an SRAM module, and the device comprises:
The control module is used for downloading a test program into the SRAM module when the processor receives a reset signal, releasing the reset signal after the test program is downloaded, converting the reset signal from a low-level signal to a high-level signal, and starting the processor through the high-level signal;
The receiving module is used for receiving a starting mode selection instruction through the starting control module so that the processor reads an initial value of a main stack pointer and a starting address of a test program according to the starting mode selection instruction;
And the control module is further used for controlling the processor to execute the test program stored in the SRAM module when the processor reads the initial value of the main stack pointer and the initial address of the test program.
13. A chip, characterized in that it is activated by the activation means of the chip according to claim 12 when said chip is in a test mode.
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| JP2009289336A (en) * | 2008-05-29 | 2009-12-10 | Nec Electronics Corp | Semiconductor integrated circuit and test method thereof |
| CN116643801A (en) * | 2023-07-26 | 2023-08-25 | 常州楠菲微电子有限公司 | Method for repairing address space of chip safe start and chip |
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| TWI497511B (en) * | 2012-11-08 | 2015-08-21 | Ind Tech Res Inst | Chip with embedded non-volatile memory and testing method therefor |
| CN105700901B (en) * | 2014-11-28 | 2020-05-08 | 华为技术有限公司 | A startup method, device and computer system |
| CN109801665B (en) * | 2018-12-14 | 2021-05-11 | 深圳市紫光同创电子有限公司 | SRAM self-test system, structure and method, storage medium |
| CN115480827A (en) * | 2022-09-13 | 2022-12-16 | 重庆长安汽车股份有限公司 | MCU chip starting method |
| CN116237276A (en) * | 2023-02-21 | 2023-06-09 | 杭州长川科技股份有限公司 | Chip testing method, system, device and electronic equipment |
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| JP2009289336A (en) * | 2008-05-29 | 2009-12-10 | Nec Electronics Corp | Semiconductor integrated circuit and test method thereof |
| CN116643801A (en) * | 2023-07-26 | 2023-08-25 | 常州楠菲微电子有限公司 | Method for repairing address space of chip safe start and chip |
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