JP2008158991A - NAND flash memory control system - Google Patents

Abstract

A NAND-type flash memory controller is compatible with various NAND-type flash memories, and a control board can be used in a long life cycle without degrading functions and specifications.
A system power supply is turned on to activate a main CPU and to activate a NAND flash memory controller. When the NAND flash memory controller 12 is activated, the NAND ID 20 is read from the NAND flash memory 13 to set individual specifications necessary for memory access, and the configuration data 21 is read to speed the memory access (access time). ) Is set. Then, the user data 22 of the NAND flash memory 13 is copied to the DRAM, and the main CPU executes the main program.
[Selection] Figure 2

Description

  The present invention relates to a control system for a NAND flash memory, and more particularly to a control system for a NAND flash memory that controls a NAND flash memory storing program data using a NAND flash memory controller.

  Conventionally, when executing program data stored in a memory in a machine such as a copying machine, a facsimile machine, or a printer, it is essential that the memory be randomly accessible. Therefore, a NOR flash is used as a nonvolatile memory for storing a program. It was common to use memory.

  Recently, however, the program capacity has been enlarged due to an increase in applications in each device, and the number of NAND flash memories with low unit cost per unit bit and high writing speed is increasing for storing programs.

  However, in adopting the NAND flash memory, functions such as management of defective blocks, conversion of logical physical addresses, and uniformization of blocks (wear leveling) are required. Thus, although these functions can be performed using host-side software, a general-purpose NAND flash memory controller equipped with the above functions is used to reduce the load of software driver processing.

  The NAND flash memory has a device ID indicating the memory specification, and the connected NAND flash memory controller reads the device ID to set the device according to the NAND flash memory specification. Is going.

JP 2003-308525 A JP 2003-330743 A

  Such NAND flash memory can achieve high capacity and high speed by process shrink that reduces the chip size, but the specifications of the NAND flash memory controller that controls this can be used so that the latest NAND flash memory can be used There is a demand for scalable support.

  However, the device ID used in the NAND flash memory is slightly different depending on the manufacturer, and the size is limited (for example, 4 bytes), so there is a problem that the specifications such as the extended function cannot be read. . Therefore, if the specifications of the device ID are expanded with the evolution of the NAND flash memory, undefined information may be required when developing the NAND flash memory controller.

  In addition, the variation factors of NAND flash memory include capacity, block size, page size, access speed, or bus width. In setting these, external terminals of the NAND flash memory controller or other If a redundant specification that can be set from a nonvolatile device (for example, EEPROM) is used, there is a problem that the cost of the NAND flash memory controller is increased.

  Furthermore, by changing the firmware in the NAND flash memory controller from the mask ROM to the flash ROM, it becomes possible to expand the function without changing the hardware. There was a problem of increasing costs.

  In addition, general-purpose NAND type memory modules (SD card, USB memory) have a short life cycle, and can be handled by reviewing the NAND type control IC for each product. However, when NAND flash memory is incorporated into copiers, multifunction devices, etc., the life cycle of the device is long, and the use of NAND flash memory with the latest capacity and speed in later models due to the common use of controllers. However, if the specifications of the NAND flash memory controller are not compatible at that time, the evaluation and quality assurance must be repeated by changing the NAND flash memory, which is inconvenient. there were.

  The present invention has been made in view of the above, and enables a NAND flash memory controller to support a wide range of NAND flash memories and uses a control board in a long life cycle without degrading functions and specifications. An object of the present invention is to provide a control system for a NAND flash memory that can be used.

  In order to solve the above-described problems and achieve the object, the present invention is a NAND flash memory control system that controls a NAND flash memory storing program data using a NAND flash memory controller. The NAND flash memory controller reads the setting data stored in a specific area of the NAND flash memory, and changes the operation specification according to the NAND flash memory.

  Further, according to a preferred aspect of the present invention, when program data is written from an external medium to the NAND flash memory, it is desirable to write setting data stored in the external medium to the specific area.

  According to a preferred aspect of the present invention, the apparatus further comprises a writing jig storing setting data of the NAND flash memory, the writing jig is connected to an interface of the NAND flash memory, and the specific area is accessed. It is desirable to write setting data.

  According to a preferred aspect of the present invention, when the program data stored in the NAND flash memory includes setting data, the NAND flash memory controller sets the setting data in the program data after the system is booted. Is preferably copied and written into a specific area of the NAND flash memory.

  According to a preferred aspect of the present invention, after the NAND flash memory controller copies and writes setting data to a specific area of the NAND flash memory, the NAND flash memory controller is reset and rebooted. Therefore, it is desirable to reflect the setting value of the setting data.

  According to a preferred aspect of the present invention, it is desirable to provide a flag for the setting data and to determine whether to copy the setting data based on the flag.

  According to a preferred aspect of the present invention, it is desirable to provide version information in the setting data and determine whether to update the setting data based on the version information.

  According to the present invention, a NAND flash memory for storing program data and a NAND flash memory controller are provided, and the NAND flash memory controller reads the setting data stored in a specific area of the NAND flash memory, thereby The setting is changed according to the operation specification of the NAND flash memory. In this way, by storing the setting data of each NAND flash memory in its own specific area, there is no restriction due to the capacity and data format like the conventional device ID, and the connected NAND flash memory controller There is an effect that setting data of a specific area in the NAND flash memory can be read, and settings can be easily changed to operation specifications corresponding to various NAND flash memories.

  According to the present invention, when program data is written to the NAND flash memory using an external medium, the setting data stored in the external medium is written to a specific area. As described above, when program data is written to the NAND flash memory using an external medium after commercialization, the setting data stored in the external medium is written to a specific area, and the NAND flash memory controller stores the setting data from here. By reading, there is an effect that the setting can be easily changed to the operation specification suitable for the NAND flash memory.

  In addition, according to the present invention, the writing jig storing the setting data of the NAND flash memory is provided, and the writing jig is used to connect to the interface of the NAND flash memory after commercialization. Is stored in a specific area of the NAND flash memory. As described above, the NAND flash memory controller can easily change the setting to the operation specification suitable for the NAND flash memory by reading the setting data written in the specific area of the NAND flash memory. Play.

  Further, according to the present invention, when the setting data is included in the program data stored in the NAND flash memory, the NAND flash memory controller includes the program data in the NAND flash memory after the system is booted (started up). The setting data is copied and written to a specific area. As described above, the NAND flash memory controller has an effect that the setting data stored in the program data can be written to the specific area at the normal startup of the system.

  Further, according to the present invention, after the NAND flash memory controller copies and writes the setting data to the specific area of the NAND flash memory, the NAND flash memory controller is reset and rebooted (restarted). Reflect the setting value of the setting data. As described above, when reflecting the setting value of the setting data, the setting data is set by resetting only the NAND flash memory controller and rebooting instead of turning on / off the entire system and booting. There is an effect that the reflection of the value can be performed efficiently.

  In addition, according to the present invention, the setting data is provided with a flag for determining whether to copy the setting data and write it to a specific area of the NAND flash memory, and the NAND flash memory controller checks the status of the setting data flag. Thus, it is determined to write the setting data to the specific area. As described above, since the flag is used to determine whether to write the setting data to the specific area, there is an effect that it is possible to eliminate the useless processing that has been performed to write the setting data at each normal startup.

  Also, according to the present invention, version information is provided in the setting data, and the NAND flash memory controller determines whether or not to update the setting data based on the version information of the setting data. As described above, since the update of the setting data is performed using the version information, there is an effect that it is possible to eliminate the useless processing that has been performed to write the setting data at each normal startup until now.

  Embodiments of a NAND flash memory control system according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

(First embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration of a control board of the copying machine according to the present embodiment. The control board shown in FIG. 1 includes a CPU 10, a DRAM 11, a NAND flash memory controller 12, a NAND flash memory 13, a NOR flash memory 14, an SD card 15, an HDD 16, and the like.

  The CPU 10 is a control unit that controls the entire copying machine. The DRAM 11 is a memory used for copying program data stored in the NAND flash memory 13 or the like and executing programs on the DRAM. The NAND flash memory controller 12 and the NAND flash memory 13 are main parts constituting the control system of the present invention, and are connected via a NAND interface (I / F). The NOR flash memory 14 stores a startup program for the CPU 10, and the CPU 10 is started by the program of the NOR flash memory 14 when the system is turned on. The SD card 15 is a detachable external medium that stores configuration data as program data and setting data. The HDD 16 is a large-capacity nonvolatile memory that is connected to the CPU 10 via the ATA and can store various data.

  FIG. 2 is a detailed configuration diagram of the NAND flash memory controller and the NAND flash memory of FIG. As shown in FIG. 2, the NAND flash memory controller 12 is connected to the NAND flash memory 13 via a NAND interface, and controls the NAND flash memory 13. The NAND flash memory controller 12 includes a CPU 121, a ROM 122, a RAM 123, a NAND controller module 124, a USB interface 125, a GPIO (General Purpose Input / Output) 126 as a general-purpose input / output port, and the like. Further, the NAND flash memory 13 stores a block that stores NAND ID 20 as a device ID, a block that stores configuration data (Config Data) 21 such as setting data as an extended device ID, and user data 22 such as program data. It has a block to do.

  FIG. 3 is a diagram for explaining the configuration of the NAND ID of the NAND flash memory of FIG. As shown in the upper table of FIG. 3, the NAND ID 20 includes a manufacturer code, a device code, a page size, a block size, a bus width, a speed (access time), and the like. These NAND IDs are stored in 4 bytes as shown in the lower table of FIG.

  FIG. 4 is a diagram for explaining the configuration of configuration data of the NAND flash memory of FIG. The configuration data 21 is written in a specific area of the NAND flash memory 13 determined by the NAND flash memory controller 12. The upper table of FIG. 4 shows that the read (Read) timing and write (Write) data are written in the configuration data 21, and the lower table of FIG. 4 shows the timing specifications for each NAND flash memory and the timing specifications. The relationship with the set value for is shown. FIG. 5 is a configuration diagram of dedicated commands necessary for writing configuration data from the NAND flash memory controller to a specific area of the NAND flash memory. When the configuration data is written using the dedicated command shown in FIG. 5, it cannot be accessed from a normal formatted memory space.

  FIG. 12 is a flowchart for explaining the operation of the NAND flash memory control system according to the first embodiment, and FIG. 13 is a flowchart showing a subroutine of step S101 in FIG. As shown in FIG. 12, when the system power is turned on, the CPU 10 of FIG. 1 performs a boot process from the NOR flash memory 14 (step S100), and the NAND flash memory controller of the present invention. 12 is started (step S101).

  In the start-up process in the NAND flash memory controller 12, as shown in FIG. 13, when the NAND flash memory controller 12 reads the NAND ID 20 from the NAND flash memory 13, individual specifications (for example, page size) required for memory access are obtained. , Block size, bus width, access time) can be set (step S1010).

  Subsequently, as shown in FIG. 13, the NAND flash memory controller 12 reads the configuration data 21 from the NAND flash memory 13 to set the speed (access time) at the time of memory access (step S1011).

  For example, when the access time of the NAND flash memory 13 is 20 ns and the information cannot be obtained from the NAND ID 20, or even if the information is obtained, the firmware of the NAND flash memory controller 12 adds the additional information of 20 ns. If the specification is not recognized, 0x3B in the lower table of FIG. 4 is set in Byte 1 of the configuration data, so that the operating frequency can be switched to the maximum speed of 30 MHz corresponding to the access time.

  In subsequent step S102, the user data 22 of the NAND flash memory 13 is copied to the DRAM 11 of FIG. Then, the program counter is jumped to the address on the DRAM 11 and the CPU 10 executes the main program (step S103). Then, the process ends when the system power is turned off (step S104).

  As described above, according to the first embodiment of the present invention, the NAND flash memory controller 12 reads the configuration data 21 as the setting data stored in the specific area of the NAND flash memory 13 to perform various operations. The operation specification can be changed according to the NAND flash memory 13.

(Second Embodiment)
In the second embodiment, when writing program data to the NAND flash memory 13 using an SD card as an external medium in which program data and setting data (configuration data) are stored, the setting data is also stored in a specific area. It is characterized in that it is written.

  FIG. 6 is a schematic configuration diagram according to the second embodiment in which data is written to a NAND flash memory using an SD card. As shown in FIG. 6, program data 23 and configuration data 21 are stored in the SD card 15. When the system power is turned on with the SD card 15 inserted into the control board via the SD interface (I / F) shown in FIG. 1, the CPU 10 and the NAND flash memory controller 12 are activated and the SD card 15 is activated. Data in the card 15 (program data 23 and configuration data 21) is copied to the DRAM 11. The program data 23 in the DRAM 11 is copied to the NAND flash memory 13 and the configuration data 21 in the DRAM 11 is written to a specific area of the NAND flash memory 13 using a dedicated command. Hereinafter, the operation will be described with reference to FIG.

  FIG. 14 is a flowchart for explaining the operation of the control system of the NAND flash memory according to the second embodiment. When the system power is turned on with the SD card 15 inserted in the control board, the CPU 10 starts up from the NOR flash memory 14 as shown in FIG. 14 (step S200), and the NAND flash memory controller. 12 is performed (step S201).

  Here, the presence / absence of the program data 23 in the SD card 15 is determined (step S202). If the program data 23 is present, the data (program data 23 and configuration data 21) in the SD card 15 is copied to the DRAM 11 (step S202). S203).

  Then, the program data 23 in the DRAM 11 is copied by DMA transfer to the user data 22 area of the NAND flash memory 13 (step S204).

  Next, the configuration data 21 in the DRAM 11 is written to a specific area for the configuration data 21 in the NAND flash memory 13 using a dedicated command (step S205), and the process is terminated by power-off (step S206).

  In step S202, if there is no program data 23 in the SD card 15, normal activation and initialization are performed (step S207), and the program data 23, which is the user data 22 of the NAND flash memory 13, is DMA transferred. To copy to the DRAM 11 (step S208).

  Then, the CPU 10 jumps the program counter to the address on the DRAM 11 and executes the program (step S209).

  Thus, according to the second embodiment of the present invention, program data and configuration data 21 of the external SD card 15 can be written into the NAND flash memory 13 after commercialization. Thereby, the NAND flash memory controller 12 can change the setting to the operation specification corresponding to the NAND flash memory 13 by reading the configuration data 21 of the NAND flash memory 13 at the time of startup.

(Third embodiment)
The third embodiment is characterized in that a configuration data writing jig 30 storing setting data (configuration data 21) is further provided.

  FIG. 7 is a schematic configuration diagram according to the third embodiment in which configuration data is written to a specific area of the NAND flash memory using a configuration data writing jig. Using the fixture of the control board, the configuration data writing jig 21 is connected to the NAND I / F, and the configuration data 21 of the configuration data writing jig 21 is directly transferred to a specific area of the NAND flash memory 13 (area of the configuration data 21). Can write.

  As described above, according to the third embodiment of the present invention, the desired configuration data 21 can be written to a specific area of the NAND flash memory 13 by using the configuration data writing jig 21 at the time of commercialization. . Thereby, the NAND flash memory controller 12 can change the setting to the operation specification corresponding to the NAND flash memory 13 by reading the configuration data 21 of the NAND flash memory 13 at the time of startup.

(Fourth embodiment)
The fourth embodiment is characterized in that setting data (configuration data 24) is included in a part of program data written to the NAND flash memory 13.

  FIG. 8 is a schematic configuration diagram according to the fourth embodiment when program data including configuration data is written to the NAND flash memory. As shown in FIG. 8, it is possible to write program data 23 including configuration data 24 into the NAND flash memory 13 using a ROM writer 40, an SD card 15, or the like.

  FIG. 15 is a flowchart for explaining the operation of the fourth to sixth embodiments. In the fourth embodiment, when the system power is turned on, as shown in FIG. 15, the CPU 10 performs a boot process from the NOR flash memory 14 (step S <b> 300) and starts the NAND flash memory controller 12. Processing is performed (step S301).

  Here, when the SD card 15 for upgrading is inserted in the control board, it is determined whether or not there is program data in the SD card 15 (step S302). The program data 23 including the configuration data 24 is copied to the DRAM 11 (step S303).

  Then, the program data 23 including the configuration data 24 in the DRAM 11 is copied by DMA transfer to the area of the user data 22 in the NAND flash memory 13 (step S304), and the process is terminated by power OFF (step S305).

  In the manufacturing process of the system, the program data 23 including the configuration data 24 may be written into the user data 22 area of the NAND flash memory 13 using the ROM writer 40.

  The program data 23 including the configuration data 24 written in the user data 22 area of the NAND flash memory 13 is NAND-type when the system power is turned on again and normal startup is performed in FIG. 15 (steps S300 and 301). The flash memory controller 12 reads the configuration data 24 in the user data 22, and the configuration data 21 is written in a specific area of the NAND flash memory 13 using a dedicated command (see the broken line arrow in FIG. 8).

  As described above, according to the fourth embodiment of the present invention, when the program data 23 including the configuration data 24 is written in the user data 22 area of the NAND flash memory 13, the NAND type at the normal startup of the system. The flash memory controller 12 reads the configuration data 24 in the user data 22 of the NAND flash memory 13 and the configuration data 21 in the specific area is written. Thereby, the NAND flash memory controller 12 can read the configuration data 21 written in the specific area of the NAND flash memory 13 at the time of start-up and change the setting to the operation specification corresponding to the NAND flash memory 13. .

(Fifth embodiment)
In the fifth embodiment, in the fourth embodiment, the configuration data 24 in the user data 22 is read at the normal startup of the system, and the setting value of the configuration data 21 written in the specific area using a dedicated command is used. There is a feature in the means to reflect.

  That is, when reflecting the set value of the configuration data 21 written in the specific area of the NAND flash memory 13 using a dedicated command, the entire control board may be turned on / off to restart. However, this causes inefficiency because startup processing other than reflecting the setting value of the configuration data 21 in the specific area is also performed. Therefore, in the fifth embodiment, unnecessary boot processing is performed while reflecting the setting value of the configuration data 21 by resetting only the NAND flash memory controller 12 and rebooting (rebooting). Therefore, it can be processed efficiently.

  As described above, according to the fifth embodiment of the present invention, when the set value of the configuration data 21 written in the specific area of the NAND flash memory 13 is reflected, only the NAND flash memory controller 12 is reset. Therefore, the setting value of the configuration data 21 can be reflected, and since it is not necessary to turn on / off the entire control board, the processing can be performed efficiently.

(Sixth embodiment)
In the sixth embodiment, in the fourth embodiment, the configuration data 24 included in the program data 23 stored in the user data 22 area of the NAND flash memory 13 is transferred to a specific area at every normal startup. Although it was copied, it is inefficient, and is characterized in that a flag for determining whether or not to copy the configuration data is provided.

  FIG. 10 is a configuration diagram of configuration data including the FLAG bit according to the sixth embodiment. As shown in FIG. 10, the FLAG bit is provided in bit 7 of Byte 7 in the configuration data, and the initial value is “1”.

  In the fourth embodiment, the CPU 10 reads and confirms the FLAG bit in the configuration data 24 (step S307 in FIG. 15). When the FLAG bit is “1” (step S308), the configuration data 24 in the user data is read and written to the configuration data 21 of the NAND flash memory 13 with a dedicated command (step S309). Thereafter, “0” is written to the FLAG bit to clear it (step S310). When the FLAG bit is “0”, the writing to the configuration data 21 is not performed, and the processing shifts to the normal main program execution.

  That is, the CPU 10 resets the NAND flash memory controller 12 (step S311), starts and initializes the NAND flash memory controller 12 (step S312), and transfers the user data 22 of the NAND flash memory 13 to the DRAM 11. Copy (step S313), jump the program counter to the address on the DRAM 11, and execute the main program.

  As described above, according to the sixth embodiment of the present invention, the flag for determining whether or not to copy the configuration data 24 in the user data of the NAND flash memory 13 to the configuration data 21 in the specific area at the normal startup time. Is provided in the configuration data, the useless copying operation can be omitted and the processing can be made efficient.

(Seventh embodiment)
In the seventh embodiment, in the fourth embodiment, the configuration data 24 included in the program data 23 stored in the user data 22 area of the NAND flash memory 13 is transferred to a specific area at every normal startup. Although it was copied, it is inefficient, and it is characterized in that it is determined using configuration data version information whether or not configuration data needs to be updated.

  FIG. 9 is a detailed configuration diagram of a NAND flash memory controller and a NAND flash memory according to the seventh embodiment, and FIG. 11 is a configuration of configuration data including version information according to the seventh embodiment. FIG. First, as shown in FIG. 9, a block called a configuration version 25 is provided in the user data 22 of the NAND flash memory 13 (the initial value is “0”). Also, in the configuration data 24 in the user data 22 of FIG. 9, version data as version information is provided in the Byte 7 in the configuration data 24 (initial value is “1”) as shown in FIG.

  In the seventh embodiment, the configuration is as described above, and the CPU 10 reads the version data (see FIG. 11) in the configuration data 24 in FIG. 9 at the normal startup corresponding to step S306 in FIG. Let the version value be A).

  Subsequently, the CPU 10 reads the configuration version 25 in the user data 22 in the NAND flash memory 13 (this version value is set as B). Then, both version values are compared, and the configuration data 24 is read only when A> B, and written to the configuration data 21 of the NAND flash memory 13 with a dedicated command (corresponding to step S309).

  Thereafter, the version value B is updated by writing the version value A into the configuration version 25. Since A = B at the time of update, the configuration data 24 in the user data of the NAND flash memory 13 is not copied to the configuration data 21 in the specific area at the normal startup.

  As described above, according to the seventh embodiment of the present invention, the configuration data 24 is stored in the specific area only when the version of the configuration data is updated by viewing the version information of the configuration data even during normal startup. The configuration data 21 is allowed to be copied and the useless copy operation is omitted, so that the processing can be made efficient.

  INDUSTRIAL APPLICABILITY The NAND flash memory control system according to the present invention is useful for an image forming apparatus or a network device having a NAND flash memory controller whose operation specifications can be changed according to various NAND flash memories storing program data. It is. In particular, the present invention is suitable for a NAND flash memory control system that can cope with specification changes that could not be expanded with the device ID of the NAND flash memory.

2 is a block diagram illustrating a schematic configuration of a control board of the copier according to the present embodiment. FIG. FIG. 2 is a detailed configuration diagram of a NAND flash memory controller and a NAND flash memory in FIG. 1. FIG. 3 is a diagram for explaining a configuration of a NAND ID of the NAND flash memory of FIG. 2. FIG. 3 is a diagram illustrating a configuration of configuration data of the NAND flash memory of FIG. 2. FIG. 5 is a configuration diagram of a dedicated command necessary for writing configuration data from a NAND flash memory controller to a specific area of a NAND flash memory. It is a schematic block diagram concerning 2nd Embodiment which writes data in a NAND type flash memory using an SD card. It is a schematic block diagram concerning 3rd Embodiment which writes configuration data to the specific area | region of NAND type flash memory using a configuration data writing jig. It is a schematic block diagram concerning 4th Embodiment when the program data containing configuration data are written in the NAND type flash memory. FIG. 14 is a detailed configuration diagram of a NAND flash memory controller and a NAND flash memory according to a seventh embodiment. It is a block diagram of the configuration data containing the FLAG bit concerning 6th Embodiment. It is a block diagram of the configuration data containing the version information concerning 7th Embodiment. 3 is a flowchart for explaining the operation of the control system of the NAND flash memory according to the first embodiment. It is a flowchart which shows the subroutine of step S101 of FIG. It is a flowchart explaining operation | movement of the control system of the NAND type flash memory concerning 2nd Embodiment. It is a flowchart explaining the operation | movement of 4th-6th embodiment.

Explanation of symbols

10 CPU
11 DRAM
12 NAND flash memory controller 13 NAND flash memory 14 NOR flash memory 15 SD card 20 NAND ID
21 Configuration Data 22 User Data 23 Program Data 24 Configuration Data 30 Configuration Data Writing Jig 40 ROM Writer 50 Configuration Version 121 CPU
122 ROM
123 RAM
124 NAND controller module 125 USB interface 126 GPIO

Claims (7)

A NAND flash memory control system that controls a NAND flash memory storing program data using a NAND flash memory controller,
The NAND flash memory controller reads the setting data stored in a specific area of the NAND flash memory and changes the operation specifications according to the NAND flash memory. Control system.   2. The NAND flash memory according to claim 1, wherein setting data stored in the external medium is written to the specific area when program data is written from the external medium to the NAND flash memory. Control system. A writing jig in which setting data of the NAND flash memory is stored;
2. The NAND flash memory control system according to claim 1, wherein the writing jig is connected to an interface of the NAND flash memory, and setting data is written to the specific area.   When the setting data is included in the program data stored in the NAND flash memory, the NAND flash memory controller copies the setting data in the program data after the system is booted, and the NAND flash memory 2. The NAND flash memory control system according to claim 1, wherein writing is performed in a specific area.   After the NAND flash memory controller copies and writes setting data to a specific area of the NAND flash memory, the NAND flash memory controller is reset and rebooted to reflect the setting value of the setting data The NAND flash memory control system according to claim 4.   5. The NAND flash memory control system according to claim 4, wherein a flag is provided in the setting data, and whether or not to copy the setting data is determined based on the flag.   5. The NAND flash memory control system according to claim 4, wherein version information is provided in the setting data, and whether to update the setting data is determined based on the version information.

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