CN1178277C - Low Temperature Formation Method for Back Ohmic Contacts in Vertical Devices - Google Patents

Abstract

The present invention includes a method for forming a metal-semiconductor ohmic contact (18) in a semiconductor device (10) having a plurality of epitaxial layers (14a-c), wherein the ohmic contact (18) is preferably formed after deposition of the epitaxial layers (14a-c). The present invention also includes a semiconductor device having a plurality of epitaxial layers and an ohmic contact.

Description

Low Temperature Formation Method for Back Ohmic Contacts in Vertical Devices

technical field

The invention relates to an ohmic contact for semiconductor materials. In particular, the present invention relates to a method of forming ohmic contacts for use in devices comprising multiple semiconductor materials.

Background technique

In the field of microelectronics, circuits are made by sequentially connecting semiconductor devices. In general, semiconductor devices operate by means of electric current in a specific circuit and are used to control that current to accomplish a specific task. In order to interconnect semiconductor devices, appropriate contacts must be made for the semiconductor devices. Due to their high electrical conductivity and other chemical properties, metals are the most effective and convenient materials for making contacts in such devices.

These metal contacts should interfere with minimal, or preferably, no interference with the operation of the device or the current-carrying metals. Furthermore, the metal contact must be physically and chemically compatible with the semiconductor material that the metal contact is made of or to which the metal contact is connected. A type of contact having these desirable properties is known as an "ohmic contact".

An ohmic contact is generally defined as a metal-semiconductor contact having a contact resistance that is negligible compared to the bulk or diffusion resistance of the semiconductor, see Sze, Physics of Semiconductor Devices, 2nd ed., 1981, p. 304. It is further stated in the article that a suitable ohmic contact will not significantly change the performance of the device connected to this ohmic contact, which can supply any required current, and whose voltage drop is equal to the voltage drop of the active area of the device quite small in comparison.

Ohmic contacts and methods of making them are well known in the art. For example, US Patents 5,409,859 and 5,323,022 to Glass et al. ("Glass patents") discuss an ohmic contact structure formed from platinum and p-type silicon carbide and methods of making the ohmic structure. In L. Spieb et al., "Al implantation of p-type SiC for ohmic contacts", Diamond and Related Materials, Vol. 6, pp. 1414-1419 (1997), J. Chen et al., "n-type β- Ohmic contacts and SiC are also discussed in "Preliminary conclusions on contact resistance of Re, Pt and Ta films on SiC", Materials Science and Engineering, B29, pp. 185-189 (1995), and WO 98/37584. Although ohmic contacts and methods for their manufacture are well known, known methods of producing ohmic contacts, especially using silicon carbide substrates, are difficult to implement even if applied correctly.

The problems associated with forming ohmic contacts are numerous and growing. The limited conductivity of semiconductors due to low hole or electron concentrations can hinder or even prevent the formation of ohmic contacts. Likewise, poor hole mobility or electron mobility within semiconductors can hinder or even prevent the formation of ohmic contacts. As discussed in the Glass patent, the difference in work function between the contact metal and the semiconductor creates a potential barrier that ultimately forms a contact with a modified (non-ohmic) current versus applied voltage relationship. Even if there are very different electron-hole concentrations between two semiconductor materials of the same close contact, a potential barrier (internal potential energy) exists such that a rectifying contact rather than an ohmic contact is formed. In the Glass patent these problems are addressed by inserting a SiC layer containing different p-type dopants between the p-type SiC substrate and the contact metal.

A more difficult problem is encountered in forming ohmic contacts for the new generation of gallium-indium-based semiconductor devices. Forming an ohmic contact between a semiconductor and a metal requires proper fusion of the semiconductor and contact metal at their interface. It is well known that selectively increasing the hole/electron concentration at the semiconductor interface where ohmic contact metal is deposited is an effective way to enhance the contact process for forming ohmic contacts. This process is generally achieved by ion implantation, which is considered a technique for selective doping in silicon and silicon carbide. However, in the case of silicon carbide, ion implantation is usually performed at elevated temperatures (typically greater than 600°C) in order to minimize damage to the silicon carbide crystal lattice. It is often required to "activate" the implanted ions in silicon overvoltage and at annealing temperatures in excess of 1600°C to achieve the desired high carrier concentration. The equipment used for this ion implantation technique is specialized and expensive equipment.

After high temperature ion implantation and subsequent annealing, contact metal is deposited on the surface of the implanted substrate and annealed at temperatures in excess of 900°C. This method of forming contacts on semiconductor devices containing gallium nitride or indium gallium nitride is not feasible because these compounds decompose at high temperatures.

One theoretical answer to this problem is to form ohmic contacts on the substrate before growing the fragile epitaxial layers (such as gallium nitride layers) necessary to complete the semiconductor device. However, this approach is undesirable because it inserts an unwanted impurity, ie, contact metal, into the epitaxial growth system. Impurity metals can affect epitaxial growth by interfering with lattice growth, doping, reaction speed, or all of these factors. In addition, metallic impurities can degrade the optical and electrical properties of the epitaxial layer.

Similarly, many semiconductor devices, such as metal-oxide-semiconductor field effect transistors ("MOSFETs"), require layers of semiconducting oxides, such as silicon dioxide. The high temperatures associated with conventional ion implantation techniques and the annealing process of the implant or contact metal create high stresses on the oxide layer that can damage the oxide layer, the semiconductor-oxide interface, and the device itself. Alternatively, it is impractical to form an ohmic contact before the oxide layer is created because the oxidizing environment used to form the oxide layer has an adverse effect on the ohmic contact.

Accordingly, there is a need for an economical and practical method of forming ohmic contacts for interfacing with semiconductor devices without the aforementioned manufacturing problems. There is also a need for a lower cost semiconductor device that includes ohmic contacts.

Contents of the invention

An object of the present invention is to provide a semiconductor device including an ohmic contact.

Another object of the present invention is to provide a semiconductor device comprising silicon nitride and an ohmic contact.

Yet another object of the present invention is to provide a semiconductor device comprising an ohmic contact with low manufacturing cost.

Yet another object of the present invention is to provide a method of forming a semiconductor device including an ohmic contact.

To achieve these objects, the present invention provides a method of forming an ohmic contact for silicon carbide in a semiconductor device, comprising the steps of implanting a selected dopant material into the surface of a silicon carbide substrate at room temperature, wherein the dopant is implanted with more than one implantation energy of 10-60 keV, thereby forming in the substrate a region of increased concentration of dopant material on the implanted surface, which increases away from the implanted surface The carrier concentration in the substrate is reduced; the first annealing is performed on the implanted silicon carbide substrate at a temperature of 800-1300 ° C; at least one non-implanted silicon carbide substrate is grown on the surface of the silicon carbide substrate opposite to the implanted surface. an epitaxial layer of a compound of silicon carbide whose decomposition temperature is lower than that of the silicon carbide substrate; depositing a layer of metal on the implanted surface of the silicon carbide substrate; and subsequent carbonization of the metal and the implanted The silicon substrate is subjected to a second anneal at a temperature lower than the temperature at which the compound forming the epitaxial layer is significantly degraded but high enough to form an ohmic bond between the implanted silicon carbide and the deposited metal. contacts.

To achieve these objects, the present invention also provides a semiconductor device having at least one conductive region on which an ohmic contact is formed, the semiconductor device comprising: a first surface, a second surface, a first conductivity type and an initial carrier A semiconductor substrate with carrier concentration; at least one epitaxial layer on the first surface of the semiconductor substrate, the decomposition temperature of the material constituting the epitaxial layer is lower than the decomposition temperature of the semiconductor substrate; a region in the sheet having a carrier concentration greater than said initial carrier concentration, the region extending from said second surface within said semiconductor substrate to a depth less than the total thickness of said semiconductor substrate; and a layer of metal deposited on said second surface of said semiconductor substrate, which forms an ohmic contact at the interface of said metal and said region of greater carrier concentration.

The present invention will be described in detail below in conjunction with the accompanying drawings showing typical embodiments, so that the foregoing and other objects, advantages and features of the present invention and their implementations will be more easily understood.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the present invention.

Figure 2 is a schematic cross-sectional view of a dopant implant applied in the method according to the invention.

Detailed ways

The present invention is a semiconductor device including an ohmic contact and a method of forming an ohmic contact.

It is readily understood by those skilled in the art of wide bandgap semiconductors such as silicon carbide and semiconductor devices formed therefrom that the present invention is most effective for making ohmic contacts and semiconductor devices utilizing n-type or p-type silicon carbide ("SiC") . Therefore, for convenience of explanation, the following description of the present invention and examples will be based on an embodiment of the present invention using SiC. However, those skilled in the art will readily recognize that other semiconductor materials, such as silicon, gallium nitride, aluminum gallium nitride, and indium gallium nitride, can also be conveniently used in the present invention. Aluminum gallium nitride and indium gallium nitride as used herein include compounds in which the mole percent of aluminum and gallium or indium and gallium is equal to 1.

In one of its principal aspects, the invention is a semiconductor device comprising a semiconductor substrate having an initial concentration of a dopant and an initial conductivity type. The semiconductor substrate can be n-type or p-type. The device also includes at least one epitaxial layer located near one surface of the semiconductor substrate.

The semiconductor device is characterized in that the semiconductor substrate is defined by a region of increased carrier concentration extending from the surface of the substrate opposite to the epitaxial layer to the surface adjacent to the epitaxial layer. A metal layer is deposited on the substrate in the region of increased carrier concentration, thereby forming an ohmic contact at the metal-substrate interface.

Referring now to FIG. 1 , a schematic diagram of a semiconductor device 10 in accordance with the present invention is depicted. Device 10 includes a semiconductor substrate 12 which, for ease of explanation, may be considered to be SiC. It should be understood, however, that other semiconductor materials, such as silicon, may be used as substrates in the practice of the present invention. SiC substrate 12 can be p-type or n-type.

Adjacent to the SiC substrate 12 are auxiliary components 14 necessary to complete the semiconductor device. For example, referring to FIG. 1, the semiconductor device may be a light emitting diode ("LED") having sequential epitaxial layers 14a, 14b and 14c of p-type and n-type semiconductor material. In preferred embodiments, the invention is a vertical semiconductor device, such as an LED, a metal-oxide-semiconductor field-effect transistor ("MOSFET"), a laser, or a Schottky rectifier. As will be discussed later, devices according to the invention are particularly suitable for use in vertical semiconductor devices comprising materials with a low melting point or low decomposition temperature. Such materials include gallium nitride, indium gallium nitride, and aluminum gallium nitride.

The device is also characterized by having a region of increased carrier concentration 16 on the back side of the semiconductor substrate. In other words, in the case of SiC, the carrier concentration is higher in the vicinity of the surface of the semiconductor substrate opposite to the epitaxial layer than in other portions of the substrate.

The boundary of the region 16 of increased carrier concentration is indicated by a dotted line, and the use of the dotted line indicates that there is no clear boundary of the carrier concentration when the substrate 12 changes abruptly. The carrier concentration decreases with increasing distance from the back of the substrate until the carrier concentration is equal to the initial carrier concentration. As will be discussed below, the region of increased carrier concentration is formed by room temperature ion implantation techniques using dopants typically associated with p-type and n-type semiconductor materials.

As shown in Figure 1, a preferred embodiment of the device comprises a nitrogen-doped n-type SiC substrate. It should be understood that n-type SiC formed from other n-type dopants may also be used in accordance with the present invention along with various p-type SiCs. SiC substrate 12 is preferably doped from low concentration to high concentration with an initial carrier concentration between about 1×10 ¹⁵ -1×10 ¹⁹ cm ⁻³ . The terms "low concentration" and "high concentration" are imprecise, and are deliberately employed to show that the initial carrier concentration can vary widely. Although the initial carrier concentration can vary widely, experiments have shown that doping the substrate from initially moderate to high concentrations provides the best results. Regions 16 having a higher carrier concentration than the rest of the substrate 12 are created by ion implanting a selected dopant material, such as nitrogen, on the surface opposite the epitaxial layer 14 . Preferably, the ion implantation to produce a region 16 of increased carrier concentration on the rear surface of the substrate is performed to such an extent that this region 16 has a carrier concentration of about 1×10 ¹⁸ -1×10 ²⁰ cm ⁻³ and always higher than the initial carrier concentration.

Those skilled in the art can recognize that the above-mentioned region of increased carrier concentration can also be formed during the growth of the substrate. However, difficulties associated with variable feed rates of the required dopants and other difficulties generally associated with crystal growth methods make this approach impractical.

Preferred n-type dopants for forming the carrier concentration increased region 16 are nitrogen, arsenic and phosphorus. Preferred p-type dopants for forming the carrier concentration increased region 16 are aluminum, boron and gallium.

Although applicants do not wish to be bound by a particular theory, evidence suggests that the region of increased carrier concentration 16 allows the creation of metal contacts with ohmic properties. In a preferred embodiment, a selected contact metal 18 with melting point, vapor pressure, and physical and chemical properties suitable for the entire semiconductor device is deposited on the surface of the SiC substrate in the region 16 of increased carrier concentration, so that An interface 20 is formed between the metal and the substrate. Preferred metals include nickel, palladium, platinum, aluminum and titanium, with nickel being most preferred. The device, including the metal and substrate, is then annealed at a temperature well below that to avoid damage to the device, especially any epitaxial layers, but above that sufficient to form an ohmic contact at the interface of the metal and substrate temperature.

Furthermore, although applicants do not wish to be bound by any particular theory, it appears that creating regions of increased carrier concentration to act as receptors for contact metals is useful. Thus, in another embodiment, the present invention includes a method of forming an ohmic contact for use in the semiconductor device described above.

In a broader sense, the invention is a method of forming metal-semiconductor contacts for use in semiconductor devices. The method includes implanting a selected dopant material into a semiconductor substrate having a first conductivity type, wherein the implanted dopant provides the same conductivity type as the substrate. For ease of discussion, it is assumed that the semiconductor substrate is a SiC substrate and that a dopant material is deposited into the surface of the SiC substrate. However, it will be readily recognized by those skilled in the art that the present invention may be readily applied to other semiconductor materials. An annealing step is performed after implanting the selected dopant material. In this annealing step, the implanted SiC substrate is annealed at a certain temperature for a sufficient time to activate the implanted dopant atoms to effectively increase the carrier concentration of the implanted dopant atoms in the SiC substrate. Contact metal is then deposited on the implanted surface of the SiC substrate. The deposited contact metal and the implanted surface of the SiC substrate are then annealed. This second annealing temperature is below the temperature at which any epitaxial layer formed on the substrate undergoes significant degradation and above the temperature sufficient to form an ohmic contact between the implanted SiC substrate and the deposited metal.

In preferred embodiments, the semiconductor substrate may comprise an n-type or p-type substrate with a low, medium or high concentration of initial dopant. For example, in the case of an n-type SiC substrate, the SiC substrate may have an initial dopant from about 1×10 ¹⁵ cm ^-3 (low concentration doping) to 1×10 ¹⁹ cm ^-3 (high concentration doping) concentration. The terms "low concentration", "medium concentration" or "high concentration" are imprecise and are used to indicate that the initial dopant concentration in the substrate material can vary. Tests have shown that substrates with medium to high doping concentrations achieve the best results of the invention.

Semiconductor material is then implanted into the selected dopant material and annealed. Preferably, the dopant implantation is performed at room temperature and the subsequent annealing is performed at a temperature between 800°C and 1300°C. Dopants generally associated with the conductivity type of the substrate can be used as dopants used in the implantation step. For example, when n-type SiC initially doped with nitrogen is used as the substrate, nitrogen can be used as the implanted dopant. Also, when p-type SiC initially doped with aluminum is used as the substrate, aluminum can be used as the implanted dopant. Other possible n-type dopants are arsenic and phosphorus. Instead boron and gallium can be used as alternative p-type dopants.

For those skilled in the art, it is readily recognized that the implantation of dopant material can be accomplished at elevated temperatures. In fact, in the case of SiC, high temperature implants are generally preferred in order to minimize damage to the SiC lattice structure. In the case of SiC, however, high temperature ion implantation limits the industrial applicability of the invention. Ion implantation equipment capable of heating the SiC substrate during implantation is unconventional, expensive, and used for research and development purposes rather than for low-cost, high-volume applications. Furthermore, when SiC substrates are heated to high temperatures, they must be heated and cooled at a rate that does not generate debris, thereby slowing down the production process.

Therefore, room temperature implantation is the preferred implantation method used in the present invention. It has been found that after room temperature ion implantation of dopants, an annealing step in a simple ventilated furnace capable of reaching 1300°C and capable of holding more than 100 substrate wafers gives satisfactory results and greatly increases yield.

The room temperature implantation of the dopant is preferably performed to create a region of increased carrier concentration near the implanted surface of the semiconductor substrate. Fig. 2 is a schematic diagram of an implantation process according to the present invention. In this example, ^an n-type SiC substrate 22 with ^an initial dopant concentration of about 1×10 ¹⁸ cm ⁻³ was treated with atomic nitrogen or bis Atomic nitrogen 24 is implanted. In some cases, more than one type of implantation energy can be used to produce a more slowly varying carrier concentration profile. The implantation process produces a region 26 with a depth of about 1000 angstroms near the implanted surface of the SiC substrate. The region 26 has a total chemical dopant concentration of about 1×10 ¹⁹ -1×10 ²⁰ cm ⁻³ and the implanted dopant concentration increases with the decreases with increasing distance from the injection surface. The dopant concentration outside the carrier concentration increased region 26 remains substantially the same as the initial dopant concentration. The boundary of region 26 of increased carrier concentration is shown in dashed lines, indicating that the change in carrier concentration between region 26 and the rest of the substrate is slow and insignificant. Those skilled in the art will readily vary the implant energy or dose to achieve the desired concentration and depth.

As mentioned above, it is necessary to anneal the implanted substrate. Annealing is required because some of the implanted dopant ions are not "active" when the implant is just completed. The term "activity" is used to describe the effectiveness of the implanted ions to affect the overall carrier concentration of the implanted substrate.

During implantation, the crystal lattice of the SiC substrate is generally impacted by dopant ions. These ions crash into the crystal lattice in which they reside. This impact does not result in a good insertion of the dopant ions into the existing crystal lattice. The initial positioning of many dopant ions prevents the ions from becoming "active" constituents of the crystal lattice, which are themselves damaged by the impact. Annealing (i.e., heating) the implanted SiC substrate provides a mechanism by which the implanted ions and the crystal lattice of the substrate rearrange in a more ordered manner and restoration occurs during dopant implantation damage.

The implantation process is described below, using only integers for ease of explanation. If 100 nitrogen ions are implanted into an n-type SiC substrate having an initial concentration of x nitrogen atoms, immediately after the implantation the substrate will have only the properties associated with a substrate containing "x+10" nitrogen ions. However, if the substrate is then annealed and the implanted ions allowed to localize in the crystal lattice, the substrate has characteristics associated with a substrate comprising "x+90" nitrogen ions.

Tests have shown that annealing a room temperature implanted SiC substrate at a temperature between about 1000°C and 1300°C for about 2 hours or less will give satisfactory results. The annealing temperature and time can be easily adjusted to achieve a more complete activation of the implanted dose.

A semiconductor device comprising the implanted substrate described above has at least one epitaxial layer. The epitaxial layer can be grown using any method known to those skilled in the art. In a preferred embodiment of the invention, the epitaxial layer is deposited prior to the dopant implantation of the substrate. However, the desired epitaxial layer or subsequently fabricated device may be made of a material that cannot withstand high temperature annealing of the implanted substrate, such as gallium nitride or silicon oxide, or the desired epitaxial layer or subsequently fabricated device may include such Material. In this case, the epitaxial layer may be formed after dopant implantation.

After the semiconductor substrate is implanted and a sufficiently annealed region of increased dopant concentration is established and any epitaxial layers are formed on the substrate, the metal selected to form the ohmic contact is applied to the surface of the substrate in the region of increased carrier concentration . The metal can be any metal commonly used to form electrical contacts that has a suitably high melting point and vapor pressure and that does not adversely interact with the substrate material. Preferred metals include nickel, palladium, platinum, titanium and aluminum, with nickel being most preferred.

Preferably, the contact metal is deposited on the surface of the substrate in a layer around 300 Angstroms thick. A second anneal is performed after deposition. However, this annealing is not high temperature and long time annealing. The annealing temperature is preferably less than about 1000°C and most preferably less than about 800°C, and the annealing time is preferably no longer than 20 minutes and most preferably no longer than 5 minutes. These temperatures and time periods are low enough to avoid damage to any epitaxial layers on the substrate. Annealing the contact metal on the semiconductor substrate creates an ohmic contact at the interface of the metal and the substrate.

In a more specific embodiment of the present invention, the first implantation of atomic nitrogen was performed at 50keV energy and 3×10 ¹⁴ cm ^-2 dose followed by the second implantation at 25keV and 5×10 ¹⁴ cm ^-2 by using an n-type SiC substrate. A second implantation results in a metal-semiconductor according to the invention. After implantation, activation annealing was performed in a furnace at a temperature of 1300° C. for 60-90 minutes in an argon atmosphere. Next, nickel contact metal is deposited on the implanted surface to a thickness of 2500 Angstroms. Contact annealing was then performed at 800° C. for 2 minutes in argon. The resulting ohmic contacts have satisfactory ohmic properties.

Those skilled in the art will recognize that contact annealing can also be performed in situ during epitaxial growth.

The present invention provides substantial benefits to devices such as vertical devices such as photodetectors, light-emitting diodes (LEDs), lasers; metal-oxide-semiconductor field-effect transistors (MOSFETs), power devices such as IGBTs, pn junctions, and Schottky rectifiers; and microwave devices such as SITs (Static Induction Transistors). In the case of detectors, LEDs and lasers, the epitaxially grown GaN and InGaN layers are not annealed at temperatures that would severely damage these layers. In the case of InGaN, the time spent at high temperatures becomes more critical as the indium content of the alloy increases. Reducing the back contact anneal temperature also reduces the potential for pyrolysis or decomposition of indium or gallium components in deformed heteroepitaxial films grown on SiC substrates.

In the case of power devices, a homoepitaxial film of SiC is grown on a substrate and thermally grown or regrown (reoxidized or annealed), the oxide plays an integral role in the device performance and lower annealing temperatures are useful. good. Back metal contacts cannot experience the oxidizing environment used to grow the SiC-silicon dioxide interface, therefore, back ohmic contacts must be deposited and annealed after silicon dioxide growth (re-oxidation or regrowth). Unfortunately, in the prior art, the subsequent annealing temperature not lower than 850°C (more typically 900-1050°C) used to form the contacts on the backside of the substrate would cause thermal expansion mismatch in SiC- Defects are generated at the silica interface. This is especially bad for MOSFETs and IGBTs.

SiC technology is in its infancy, and many proposed device and material structures still need to be verified or developed. Further development of this process could lead to even lower anneal temperatures, eventually resulting in the deposition of ohmic contacts between the metal and semiconductor (ie, without annealing).

In order to enable readers to realize the present invention without undue experimentation, the present invention has been described in detail in conjunction with certain preferred embodiments. However, those skilled in the art will readily recognize that many of the components and parameters of the present invention can be altered or altered to some extent without departing from the scope and spirit of the invention. Moreover, titles or titles, etc. are used to deepen readers' understanding of the text, and should not be considered as limiting the scope of the present invention. Only the following claims, along with their reasonable extensions and equivalents, determine the intellectual property rights of this invention.

Claims (20)

1. A method of forming an ohmic contact for silicon carbide in a semiconductor device, comprising the steps of: The selected dopant material is implanted into the surface of the silicon carbide substrate at room temperature, wherein the dopant is implanted with more than one implantation energy of 10-60keV, thereby forming the implanted regions of increased dopant material concentration on the surface, the carrier concentration in the substrate decreases away from the implanted surface; performing a first anneal on the implanted silicon carbide substrate at a temperature of 800-1300°C; growing at least one epitaxial layer of a compound other than silicon carbide having a decomposition temperature lower than that of the silicon carbide substrate on the surface of the silicon carbide substrate opposite the implanted surface; depositing a layer of metal on the implanted surface of the silicon carbide substrate; and subsequently The metal and the implanted silicon carbide substrate are subjected to a second annealing at a temperature lower than the temperature at which the compound forming the epitaxial layer is significantly degraded but high enough that the implanted carbonized An ohmic contact is formed between the silicon and the deposited metal. 2. The method of claim 1, wherein the step of growing an epitaxial layer on the silicon carbide substrate is performed before performing the first anneal on the implanted silicon carbide substrate. 3. The method of claim 1, wherein the step of growing an epitaxial layer on the silicon carbide substrate is performed after performing the first anneal on the implanted silicon carbide substrate. 4. The method of claim 1, wherein the selected dopant material is selected from the group consisting of nitrogen, aluminum, arsenic, phosphorus, boron and gallium. 5. The method of claim 1, wherein the first annealing of the implanted silicon carbide substrate is performed at a temperature between 1000-1300°C. 6. The method of claim 1, wherein the metal is selected from the group consisting of nickel, palladium, platinum, aluminum and titanium. 7. The method of claim 1, wherein the step of annealing the silicon carbide substrate and the deposited metal is performed at a temperature below 800° C. for no longer than 20 minutes. 8. A semiconductor device having at least one conductive region forming an ohmic contact thereon, the semiconductor device comprising: a semiconductor substrate having a first surface, a second surface, a first conductivity type, and an initial carrier concentration; at least one epitaxial layer on said first surface of said semiconductor substrate, the epitaxial layer is composed of a material having a decomposition temperature lower than that of the semiconductor substrate; A region in said semiconductor substrate having a carrier concentration greater than said initial carrier concentration extends from said second surface within said semiconductor substrate to a depth less than said semiconductor substrate. the overall thickness of the sheet; and A layer of metal deposited on the second surface of the semiconductor substrate that forms an ohmic contact at the interface of the metal and the region of greater carrier concentration. 9. The semiconductor device according to claim 8, wherein the semiconductor substrate is silicon carbide. 10. The semiconductor device of claim 8, wherein the implanted dopant material is selected from the group consisting of nitrogen, aluminum, arsenic, phosphorus, boron and gallium. 11. The semiconductor device according to claim 9, wherein the initial carrier concentration in silicon carbide is between 1×10 ¹⁵ -1×10 ¹⁹ cm ⁻³ . 12. The semiconductor device according to claim 11, wherein the carrier concentration in the region with a higher carrier concentration is between 1×10 ¹⁸ -1×10 ²⁰ cm ^-3 and greater than that in silicon carbide The initial carrier concentration. 13. The semiconductor device according to claim 8, wherein the epitaxial layer comprises gallium nitride, aluminum gallium nitride, indium gallium nitride, and silicon oxide, gallium oxide, aluminum oxide, and indium oxide select from the group. 14. The semiconductor device of claim 9, wherein the metal is selected from the group consisting of nickel, palladium, platinum, aluminum and titanium. 15. The semiconductor device according to claim 9, wherein: said region of greater carrier concentration is characterized by a gradual decrease in implanted dopant concentration from said second surface to said first surface; and The metal layer forming the ohmic contact is a nickel layer on the second surface of the silicon carbide semiconductor substrate. 16. The semiconductor device of claim 15, wherein the implanted dopant material is selected from the group consisting of nitrogen, aluminum, arsenic, phosphorus, boron and gallium. 17. The semiconductor device according to claim 15, wherein the initial carrier concentration in silicon carbide is between 1×10 ¹⁵ -1×10 ¹⁹ cm ⁻³ . 18. The semiconductor device according to claim 17, wherein the carrier concentration in the region with a higher carrier concentration is between 1×10 ¹⁸ -1×10 ²⁰ cm ⁻³ and greater than that in silicon carbide initial carrier concentration. 19. The semiconductor device according to claim 15, wherein the epitaxial layer is selected from gallium nitride, aluminum gallium nitride, indium gallium nitride, and silicon oxide, gallium oxide, aluminum oxide, and indium oxide select from the group. 20. The semiconductor device of claim 15, wherein the semiconductor device is a vertical device.

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