TWI281710B - Low temperature formation of backside ohmic contacts for vertical devices - Google Patents

Abstract

A method for forming an ohmic contact to silicon carbide for a semiconductor device comprises implanting impurity atoms into a surface of a silicon carbide substrate thereby forming a layer on the silicon carbide substrate having an increased concentration of impurity atoms, annealing the implanted silicon carbide substrate, and depositing a layer of metal on the implanted surface of the silicon carbide. The metal forms an ohmic contact ""as deposited"" on the silicon carbide substrate without the need for a post-deposition anneal step.

Description

1281710 (1) Description of the invention (Description of the invention should be stated: the technical field, prior art, content, embodiments and schematic description of the invention) FIELD OF THE INVENTION The invention relates to an ohmic contact to a semiconductor material. The invention is particularly relevant to the method of forming an ohmic contact to a device comprising a plurality of semiconductor materials. BACKGROUND OF THE INVENTION In the field of microelectronics, circuits are fabricated from serially connected semiconductor devices. In summary, the operation of a semiconductor device in a particular circuit is utilized to control the flow of current within a particular circuit to achieve a particular task. In order to connect the semiconductor device to the circuit, appropriate contact must be made on the semiconductor device. Due to its high conductivity and other characterization, the most suitable and most convenient material for making contact with such devices is metal. The metal contact between the semiconductor device and the circuit should have minimal or no better interference with the operation of the device or circuit. In addition, the metal contacts must be physically and chemically compatible with the semiconductor material from which they are fabricated or attached. The type of contact that exhibits the desired characteristics is known as ''ohmic contact'. An ohmic contact, often defined as a metal-semiconductor contact, has a negligible contact resistance relative to the body or distributed resistance of the semiconductor, as found in Sze's 'Physics of Semiconductor Devices'' Second Edition, 1981, page 304 . Further description of a suitable ohmic contact will not result in a significant change in the performance of the device to which it is attached, and may supply any desired current less than the voltage drop across the active region of the device with a suitable voltage drop. In this art, ohmic contacts and methods of making ohmic contacts are well known. For example, U.S. Patent Nos. 5,409,859 and 5,323,022 to Glass et al.

1281710 (7) "Glass Patent", which is hereby incorporated by reference in its entirety herein in its entirety in its entirety in its entirety, in the s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s However, known methods for making ohmic contacts, especially those using tantalum carbide substrates, are not easy to handle even if properly handled. The problems associated with obtaining ohmic contacts are numerous and continue to increase due to low holes or electrons. The concentration causes the conductivity of the semiconductor to be limited, which may hinder or even hinder the formation of ohmic contacts. Similarly, poor hole or electron mobility in the semiconductor may also hinder or even hinder the formation of ohmic contacts, as described in the Glass patent. The difference in work function between the ohmic metal and the semiconductor may cause the potential barrier to rise, causing the contact to rectify (non-ohmic) current flow to the applied voltage. Even if the two closely connected, the electron-hole concentration difference is high between the same semiconductor material, There may also be potential barriers (built-in potentials) that cause rectification rather than ohmic contact. In the Glass patent, These problems can be solved by inserting dissimilar P-type doped SiC between the p-type SiC substrate and the contact metal. The more serious problem is when forming a new generation of gallium and indium based semiconductor devices. Ou ohmic contact occurs. The ohmic contact between the semiconductor and the metal is formed, and the appropriate interface between the semiconductor and the contact metal interface is required. It is known that the selectivity increases the hole/electron concentration of the semiconductor surface where the metal is to be deposited. An effective method for intensifying the contact process to achieve ohmic contact. This process is generally carried out by selective doping techniques known in the art of germanium and tantalum carbide - ion implantation, but in the case of tantalum carbide, it is often required to be at high temperatures. Ion implantation (generally above 60 °C), carbonization

1281710 (3) The crystal lattice has the lowest damage. To "activate" the implanted atoms to achieve the desired high carrier concentration, it is often necessary to exceed the annealing temperature of 1600 ° C, and often under the silicon-over-pressure. The equipment needs to be special and expensive.

After high temperature ion implantation and subsequent annealing, the contact metal is deposited on the surface of the implanted substrate and annealed at a temperature exceeding 900 °C. This method of forming a contact on a semiconductor device having gallium nitride or indium gallium nitride is not easy to perform because these compounds decompose at high temperatures. One theoretical approach to solving this problem is to form an ohmic contact on the substrate before it becomes a broken epitaxial layer (e.g., a gallium nitride layer) required to complete the semiconductor device. However, this method is not desirable because it is necessary to bring undesired contaminants - contact metals into the stupid crystal system. The contaminated metal will affect epitaxial growth due to lattice growth, doping, reaction rate, or all of the above factors. In addition, metallic impurities can degrade the optical and electrical properties of the epitaxial layer.

Similarly, many semiconductor devices, such as MOSFETs, require a layer of semiconducting oxide (such as hafnium oxide). High temperatures associated with conventional ion implantation techniques and implant or contact metal annealing processes can highly attack the oxide layer, causing damage to the oxide layer, the semiconductor-oxide interface, and the device itself. Another alternative to forming an ohmic contact prior to the production of the oxide layer is also not feasible because the oxidizing environment used to form the oxide layer adversely affects the ohmic contact. It has been found that by increasing the temperature of the temperature-sensitive epitaxial layer on the niobium carbide (for example, a specific niobium nitride), the surface carrier concentration adjacent to the contact formation is increased; carbonization is achieved.矽 Annealing; adding metal 1282710 to the moon mark: (4) contact; then contact annealing, can successfully form an ohmic contact on carbonization. However, such a technique still requires a second annealing, and the image of the epitaxial layer is very large. The need to shape a viable and economical method of successful ohmic contact for semiconductor devices does not reveal the aforementioned manufacturing related problems. There is also a need for a semiconductor device type that requires ohmic contact and a lower manufacturing cost.

OBJECT AND SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device (including niobium carbide) which can be used in ohmic contact and which can be economically manufactured, and moreover, a metal selective for forming the ohmic contact can be selectively increased.

The present invention is compatible with the method for forming a metal-semiconductor ohmic contact for a semiconductor device. The method includes implanting a selected dopant material into a surface of a semiconductor substrate having an initial conductivity type. The implanted dopant has the same conductivity type as the semiconductor substrate. After annealing the implanted semiconductor substrate, dopant implantation is performed at a temperature and for a time sufficient to activate the implant dopant atoms and increase the effective carrier concentration. Metal is deposited on the implanted surface of the semiconductor material after annealing. In the present invention, the appropriate dopants and metals are selected to form an ohmic contact without the need for other annealing, thereby eliminating any adverse effects of such annealing on other portions of the structure. The present invention is also directed to the semiconductor device comprising a semiconductor substrate (having a surface and a first conductivity type). The semiconductor substrate includes a carrier concentration increasing region extending outward from the surface of the substrate. The device further comprises depositing a layer of metal on the surface of the substrate and forming a interface between the metal and the carrier concentration increasing region 1281710

(5) In ohmic contact. The above and other objects, advantages and features of the invention, and methods of accomplishing the same are described in the description of the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view of a semiconductor device in accordance with the present invention. Figure 2 is a schematic cross section of a dopant implant used in accordance with the method of the present invention

Figure. Figure 3 is a schematic cross-sectional view of a light-emitting diode according to the present invention. DETAILED DESCRIPTION OF THE INVENTION The present invention is a ohmic contact semiconductor device and a method of forming an ohmic contact.

Familiarity with wide bandgap semiconductors such as tantalum carbide and semiconductor devices formed therefrom will be appreciated that the present invention is most suitable for fabricating semiconductor devices employing η-type tantalum carbide (SiC) and ohmic contacts. For the sake of explanation, the following description and examples of the invention will be directed to a specific embodiment of the invention employing SiC. Those skilled in the art will readily appreciate that the present invention is readily available to semiconductor materials having other wide band gaps, such as Group III-nitrides (e.g., gallium nitride, aluminum gallium nitride, and indium gallium nitride). A broad aspect of the invention includes a semiconductor substrate having an initial dopant concentration that imparts an initial conductivity. In a preferred embodiment, the substrate is η-type tantalum carbide. A further feature of the patented semiconductor device is that the semiconductor substrate is defined by a carrier concentration region extending from a surface of the substrate relative to the stray layer to a region adjacent to the stupid layer 1271810 _ - (6) . A layer of metal is deposited on the substrate at the region where the concentration of the carrier is increased to form an ohmic contact between the metal and the substrate interface. In a preferred embodiment, the metal is selected from the group consisting of silver (A g ), slag (A1), nickel (Ni), titanium (Ti), and platinum (Pt).

Referring now to Figure 1, there is shown a schematic diagram of a semiconductor device 10 in accordance with the present invention. Device 10 includes a semiconductor substrate 12, which for purposes of illustration, is considered in terms of SiC. However, it should be understood that other wide bandgap semiconductor materials may also be employed as the substrate for use in the present invention.

Adjacent to the SiC substrate 12 is an additional component 14 required to complete the semiconductor device. For example, as shown in Fig. 1, the semiconductor device can be a light emitting diode (LED) having continuous epitaxial layers 14a, 14b and 14c of ρ-type and η-type semiconductor materials. In a preferred embodiment, the invention is in accordance with a semiconductor device, such as an LED, a MOSFET, a laser or a Schottky rectifier, which may be coupled to a conductive semiconductor substrate (on which Forming an electrical contact) consisting of several adjacent layers of epitaxial layers. As will be discussed later, semiconductor devices particularly suitable for use in accordance with the apparatus of the present invention include materials having a low melting point or a low dissociation temperature or a heat sensitive structure. Such materials include Group III nitrides, such as gallium nitride, indium gallium nitride, and aluminum gallium nitride, or devices that include sensitive interfaces such as the SiC-Si 02 interface. A further feature of the claimed invention is that there is a carrier concentration increasing zone 16 on the back side of the semiconductor substrate. In other words, the semiconductor substrate, in this case, S i C, has a carrier concentration at a substrate surface close to the epitaxial layer higher than that of the other portions of the substrate. A line drawn as a boundary of the carrier concentration increase region 16 is shown, indicating a significant boundary where there is no sudden change in the concentration of the carrier in the substrate 1 2 -10 1281710 Continuation of the Invention (7). The carrier concentration decreases as the distance from the backside surface of the substrate increases until the carrier concentration is equal to the initial carrier concentration. As will be described below, the carrier concentration increasing region is formed by ion implantation at room temperature using the relevant dopants conventionally used in semiconductor materials.

In the example shown in Fig. 1, a preferred embodiment of the device of the patent application (which is generally referred to as 10) includes a nitrogen-doped n-type SiC substrate. The SiC substrate 12 is slightly highly doped and has an initial carrier concentration of between about 1 X 1 0 15 and about 1 X 1 0 19 c π Γ 3 . ''Micro" and f'high'' are inaccurate representations, the purpose of which is to show a relatively large initial carrier concentration J by ion implantation of the selected dopant material on the surface opposite the epitaxial layer 14 A region 16 having a higher concentration of the carrier than the other portions of the substrate 1 2 is produced. The phosphorus (P) system is preferably implanted with dopants, and the degree of ion implantation performed can produce a carrier concentration of about 1 X on the back side of the substrate. The carrier concentration increasing region 16 of 1 0 19 to about lxl 02Q cnT3 is preferably higher than the initial carrier concentration.

Although the Applicant does not wish to be bound by a particular theory, evidence suggests that the formation of a carrier concentration increase region 16 produces a metal contact that exhibits ohmic properties, particularly when the region is formed by ion implantation. In a preferred embodiment, the selected contact metal 18 has a melting point, vapor pressure, and physical and chemical properties suitable for use in the overall semiconductor device, and is deposited on the surface of the Si substrate of the carrier concentration increasing region 16 , 俾 forms a metal to substrate interface 20. Preferred metals include silver, titanium, aluminum, nickel and platinum. Preferably, the work function of the selected metal is less than or equal to platinum. The preferred choice of metal depends on the application of the device. For example, for applications that focus on reflectance, either or silver may be preferred. In applications where demand is highly stable, the need for non-reactive contact metals (eg including Super-11 - 1281710 _ - (8) I sleeves continuation page

For high temperature applications, platinum is a preferred choice for contact metals. A particular advantage of the method of the present invention is the formation of light emitting diodes (LEDs) from Group 111 vapors (e.g., nitrides of Ga, Al and I?, and combinations of three and four). First, the need for a contact annealing step can improve the technique of adding a Group III nitride stray layer to the SiC substrate prior to the addition of the contact metal. In addition, as a doping additive, more metals are selected for ohmic contact. In particular, the ability to use a reflective metal such as silver (Ag) or aluminum (A1) as an ohmic contact greatly enhances the LED light output formed in this manner. Again, although the applicant does not wish to be bound by any particular theory, it is apparent that the increase in the concentration of the carrier as the acceptor of the contact metal has been effective. In another embodiment, the invention includes a method for forming an ohmic contact employed in the foregoing semiconductor device.

In a broad aspect, the invention is a method of forming a metal semiconductor contact for a semiconductor device. In a preferred embodiment, the method comprises implanting phosphorous in a η-type tantalum carbide substrate. However, those skilled in the art will readily appreciate that the present invention is readily available for use with other semiconductor materials. The selected dopant material is implanted followed by an annealing step. In this annealing step, the implanted SiC substrate is annealed at a temperature and time sufficient to activate the implanted phosphorus atoms, and the carrier concentration of the implant dopant atoms in the SiC substrate is effectively increased. A contact metal is then deposited on the implant surface of the SiC substrate. In a broader aspect, the semiconductor substrate can comprise an n-type or p-type substrate in which some micro, medium or high initial dopant concentration can be present. For example: When the substrate is η-type SiC, the SiC substrate may have an initial dopant concentration of from about lxl 015 cnT3 (slightly doped) to about lxl 019 cnT3 (highly doped). -12- 1281710 __月赖 (9) The words "slightly", "medium" and "height" are inaccurately used to refer to the initial concentration of the dopant in the Chen substrate material. Testing has shown that medium to high doped substrates achieve the best results of the present invention. Then, the phosphor is implanted on the η-type tantalum carbide substrate and annealed. Phosphor implantation is carried out at room temperature, and subsequent annealing at temperatures above about 1000 °C is preferred, preferably above about 130 °C. In a preferred embodiment, the η-type SiC is initially doped with nitrogen.

Those skilled in the art will readily appreciate that dopant material implantation can be performed at elevated temperatures. In fact, high temperature implantation is generally preferred in S i C, which reduces damage to the Si C lattice structure. However, in Si C, high temperature ion implantation can limit the economic use of the present invention. There are few ion implantation equipments with the heating capacity of the S i C substrate during the planting process, which are expensive and suitable for research and development rather than cheaper and larger quantities. Further, when the Si C substrate is heated at a high temperature, the heating and cooling rates are not caused to be broken, thereby making the production process sluggish.

In the present invention, a preferred method of planting at room temperature is employed. It has been found that after the phosphorus is deposited at room temperature, an annealing step of up to 130 ot: and in a simple exhaust furnace of 10 Å or more of the substrate wafer can be achieved, and satisfactory results can be achieved. The yield is greatly increased. It is preferred to implant the dopant at room temperature to produce a dopant concentration increase region near the implant surface of the semiconductor substrate. Figure 2 is a schematic representation of a planting process in accordance with the present invention. In this example, the η-type SiC substrate 22 has an initial dopant concentration of approximately lxl 018 cnT3, which is doped at 1 015 cm 2 or higher, and is implanted with phosphorus atoms at an electron volt energy of 25 to 100 Å. 2 4 for it. In some examples -13 - 1281710, the invention says the page of the day: (10)

In this case, more than one type of implant energy can be used to create a block or grade dopant distribution. By 'block distribution' is meant a dopant profile that maintains substantially the same level of dopant concentration within a predetermined thickness. A variety of implant energies can be utilized to achieve near block distribution. In a particular embodiment, the cloth The implantation process produces a region 26 near the implant surface of the SiC substrate, the depth of which is about 1000 angstroms, and the total chemical dopant concentration near the implant surface approaches 102 G to 1 021 cm·3, and the distance from the implant surface is increased. The concentration of the implant dopant in the distance is lower. The concentration of the dopant in the dopant concentration increasing region is substantially the same as the initial dopant concentration. The dopant concentration increasing region is bordered by a little line. In the table, it indicates that the change of the carrier concentration of the region 26 and other parts of the substrate is gradual and not sudden. It is understood by those skilled in the art that the implantation energy or doping is easy to change, and the concentration and thickness are achieved. For example: Multiple implants can be performed to create a thicker dopant concentration increase region, and ohmic contacts can be made even if some of the material is removed during subsequent processing steps.

As mentioned above, the implant substrate needs to be annealed. Annealing is necessary because some implanted dopants are not 'activated' after implantation. The activated π-element is used to describe the ability of the implanted ions to contribute to the carrier concentration of the overall implanted substrate. . During implantation, the lattice of the S1C substrate is essentially a dopant ion strike. These ions are fragmented into the crystal lattice in which they are present. This impact does not allow the dopant ions to be perfectly inserted into the existing crystal lattice. The initial position of many dopant ions prevents ions from becoming "activated" particles in the crystal lattice that may themselves be damaged by impact. Annealing (ie, heating) of the implanted S i C substrate provides a more orderly reconfigure of the lattice of the implanted ions and the substrate and self-dopant implantation period -14-1281710, __ (11) I Invention _ Continued mechanism of damage recovery caused by 10,000. The use of integers is for illustrative purposes only, and the implantation process can be viewed as secondary. If 100 phosphorus ions are implanted in the η-type S i C substrate with an initial concentration of X phosphorus ions, the substrate may only exhibit substrate-related features with ', +10' phosphor ions after initial implantation. However, if the substrate is subsequently annealed and the implant ions are moved into the crystal lattice, the substrate can exhibit substrate-related features with nx + 90'f phosphor ions. The annealing step "activation" is about 80 implanted phosphorus ion.

Tests have shown that the S i C substrate implanted at room temperature is annealed at temperatures above approximately 100 ° C, especially above approximately 130 ° C, for approximately two hours or less. Produce satisfactory results. Easy to adjust temperature and time, 俾 Achieve more complete implant doping activation.

The semiconductor device including the above implant substrate has at least one epitaxial layer. Any method known to those skilled in the art can be grown into an epitaxial layer. However, the desired epitaxial layer or subsequent fabrication apparatus may be made of a material that cannot withstand high temperature annealing of the implanted substrate (e.g., gallium nitride or tantalum oxide) or a material containing the same. In this example, an epitaxial layer can be formed after the dopant is implanted. If the epitaxial layer is made of a material that is resistant to high temperature annealing, such as a carbonized carbide layer, a layer of insect crystals can be formed prior to dopant implantation and activation. After the semiconductor substrate is implanted and a well-annealed dopant concentration region is established, the metal used to form the ohmic contact is selected and applied to the surface of the substrate at the region where the concentration of the carrier is increased. The metal can be any metal that is typically used to form electrical contacts, has a suitably high melting point and vapor pressure, and does not interact with substrate materials. Preferred metals include silver, imprint, titanium, and platinum. The work function of the metal is equal to or less than the work function of platinum. -15 - 1281710 __ (12) I. Description of the Invention Continued: It is preferable to deposit a contact metal on the surface of the substrate to form an ohmic contact layer. As described above, in the improvement of the method of the present application, phosphorus is used as the implant dopant for the ohmic contact which is selected for the contact metal and causes ohmic contact without any further annealing step.

In a more specific embodiment of the present invention, an ohmic contact according to the present invention is produced by using an η-type SiC substrate, wherein the substrate is first doped with 1015 cnT2 phosphorus atoms via 25 仟 electron volts, and the second implantation is performed. It is 50 仟 electron volts 1015 cm·2, and the third planting is 100 仟 electron volts 1〇15 cnT2. After the implantation, activation annealing was carried out at 1,300 ° C for 75 minutes in an argon-containing furnace. Titanium having a thickness of 150 angstroms was subsequently deposited as the contact metal on the implanted surface. The resulting contact exhibits appropriate ohmic properties without any further annealing.

The present invention can provide important advantages of vertical devices such as photodetectors, light emitting diodes (LEDs), lasers, power devices such as MOSFETs, and insulated gate bipolar transistors (IGBTs). ), pn junction and Schottky rectifier; and microwave devices such as SIT (static induction transistor). In the case of detectors, LEDs, and lasers, epitaxially grown lanthanide nitrides such as gallium nitride and indium gallium nitride layers do not require annealing that would cause severe damage to these layers. In the case of indium gallium nitride, the temperature rise time is more critical as the proportion of indium in the alloy increases. Eliminating the backside contact annealing temperature also reduces the chance of cleavage or dissociation of the indium or gallium component in the tightly packed epitaxial film grown on the SiC substrate. In the case of a power device, wherein the homoepitaxial epitaxial film of S i C is grown on the substrate, and the heat is grown or thermally grown (reoxidized or annealed) by the oxide in the package - 16 - 1281710 (13)

The role of performance is indispensable, and the lower annealing temperature is based on a large advantage. The backside metal contact cannot undergo the oxidizing environment required to grow into the SiC-ceria interface. After the growth of cerium oxide (reoxidation or re-growth), the ohmic contact on the back side must be deposited and annealed. Unfortunately, in the prior art, in order to subsequently form a contact on the back side of the substrate, an annealing temperature of about 85 ° C or higher (more typically 900 ° C to 1050 ° C) is required, which will result in a rate of thermal expansion. S i C - cerium oxide interface defects due to mismatch. This is particularly disadvantageous for Μ Ο S F E T and IG B T. The present invention has significant advantages in the manufacture and performance of these types of devices by the elimination of contact annealing.

In another aspect, the invention is a light emitting diode that can be implanted in an ohmic contact with the present invention. Fig. 3 is an exemplary illustration of a schematic form such as a light-emitting diode, generally designated 30. In this embodiment, the light emitting diode 30 includes an n-type tantalum carbide substrate 31 having first and second surfaces 32 and 33, respectively. The diode includes a III-nitride active layer 34 on the first surface 32 of the substrate 31. As described in the previous embodiment, the diode further includes a carrier concentration increasing region 35 located in the substrate 31 and extending from the second surface 33 of the substrate 31 to the first surface 32, and the region 35 It is characterized in that the phosphorus concentration decreases from the second surface 33 toward the first surface 32. On the second surface of the substrate there is an ohmic contact 36, on the opposite side of the device 30, another ohmic contact 37. In the illustrated embodiment, the diode 30 includes a beta plus p-type contact layer 40 that provides a portion of the conduction path between the active region 34 and the ohmic contact 37. Those skilled in the art and those skilled in the art will also appreciate that the active region 34 can be one or more of several structures, generally containing a homojunction, a single different -17-1281710 ^___ (14) I. Page junction, double heterojunction, superlattice and quantum well structure. These structures for the active zone 34 are well known in the art, and the exemplary devices and structures are found in serial numbers 60/29 4, 308, issued May 30, 2001, and 60/2 94,378, issued May 30, 2001. Co-transfer and trial applications. The contents of the two cases are fully incorporated herein by reference.

Similarly, the active region 34 and the structure forming the active region 34 are generally formed of one or more of a group 111 nitride. It is generally known that the compound is composed of gallium nitride, indium nitride, gallium nitride, and indium. Gallium gasification, bismuth S indium nitride and indium gallium nitride. Such compounds are also often abbreviated as abbreviations such as InxGaYAln_x_Y)N, and such abbreviations and their representative meanings are well known in the art and are not described herein.

In a more preferred embodiment, the ohmic contact 36 of the substrate 31 is selected from the group consisting of: Ming, Titanium, Zhen, Silver, and Flip. In some applications, silver has many advantages. It includes its high workability as a precious metal and its excellent electrical properties for contact. Silver and aluminum are particularly advantageous in light-emitting diodes due to their high reflection characteristics, which can improve the efficiency and output of optical devices such as LEDs 30. Other metals are more suitable for other applications. For example, titanium and nickel have superior electrical properties, but they are not highly reflective.

SiC technology is still in its infancy, and many of the proposed devices and material structures have not been examined or developed. Further development of this process may result in lower annealing temperatures, eventually requiring only ohmic contact between the metal and the semiconductor (ie, no annealing is required). The present invention has been described in detail with reference to the preferred preferred embodiments thereof, and the present invention can be practiced without the undue experiment. However, it is obvious that the skilled person can change or modify many of the components and parameters to a certain extent without departing from the scope and spirit of the invention. </ RTI> </ RTI> </ RTI> </ RTI> In addition, the name, title, etc. are provided to enhance the reader's understanding of the document, and should not limit the scope of the invention. The intellectual property rights of the present invention are defined only by the scope of the following patent application and its reasonable extension and equivalent. Illustrative symbol description 10 semiconductor device 12 SiC substrate 14 additional components 14a, b, c stray layer 16 dopant concentration increasing region 18 contact metal 20 interface 22 SiC substrate 24 implanted phosphorus atom 26 dopant concentration increasing region 28 Other parts of the substrate 30 Light-emitting diode 31 Substrate 32 First surface 33 Younger-one surface 34 Active layer 35 Doping concentration increasing region 36 Ohmic contact 37 Ohmic contact 40 Contact layer

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Claims (1)

1281710 ΓΤ Γ Γ . . 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 091 The method of ohmic contact, the method comprising: implanting phosphorus atoms in a surface of the η-type tantalum carbide substrate, thereby forming a phosphorus concentration increasing layer on the tantalum carbide substrate; and subsequently annealing the implanted tantalum carbide substrate; And subsequently depositing a layer of metal on the surface of the implanted carbon carbide, which constitutes an ohmic contact between the phosphorous-plated tantalum carbide and the deposited metal. 2. The method of claim 1, including at room temperature The method of claim 1, wherein the method of claim 1 includes, after the step of annealing the implanted tantalum carbide substrate, growing at least one surface of one of the tantalum carbide substrates opposite to the surface after implantation. 4. The method of claim 1, wherein the implanted tantalum carbide substrate is annealed at a temperature between about 1000 ° C and 1 300 ° C. For example, the scope of patent application is The method, wherein the substrate of the carbonized ruthenium substrate is annealed at a temperature equal to or higher than about 1 300 ° C. 6. The method of claim 1, wherein the metal is selected from the group consisting of titanium, In the group of nickel, silver and turn. 7 · The method of claim 1, wherein the phosphorus concentration continues to decrease with distance from the surface. 8 · The method of claim 1, wherein The phosphorus concentration in the predetermined thickness in the tantalum carbide substrate is substantially the same level. The method of claim 1, wherein the carrier concentration increasing layer is at least about 1000 angstroms thick. 1281710 [) Replacement page 1 0 • The method of claim 1 of the patent scope includes planting tanks at a plurality of implant energy levels. 1 1 · The method of claim 1, wherein the phosphorus is 1015cnT2 doped or higher at a planting energy level of 25 仟 electron volts. 1 2 . The method of claim 1 of the patent scope, further comprising implanting phosphorus at a concentration of 50 仟 electron volts to be doped with 15 _2 15 cm 2 or higher. 1 3 . The method of claim 12, further comprising implanting phosphorus at a concentration of 100 volts electron volts to a concentration of 10 _2 15 cm 2 or higher. A semiconductor device comprising: an annealed n-type tantalum carbide substrate having a first surface and a first at least one stray layer on the first surface of the disc fossil substrate; a phosphor concentration increasing region in the tantalum carbide substrate extending from the second surface of the substrate toward the first surface; and Depositing a layer of metal on the second surface of the semiconductor substrate, forming an ohmic contact at a interface between the metal and the carrier concentration increasing region, as in the semiconductor device of claim 14th, wherein The metal is selected from the group consisting of titanium, aluminum, nickel, silver, and platinum. 16. A semiconductor device comprising: an annealed tantalum carbide substrate having a first surface and a second surface, and an initial carrier concentration imparted to the substrate for η-type conduction; at least one stupid layer, And on the first surface of the carbonized carbide substrate; a carrier concentration increasing region in the annealed tantalum carbide substrate, -2-1281710 And extending from the second surface of the tantalum carbide substrate to the first surface, wherein the region is characterized in that a phosphorus concentration decreases from the second surface toward the first surface; and a second surface of the tantalum carbide substrate Ohmic contact. A semiconductor device according to claim 16 wherein the initial carrier concentration in the tantalum carbide substrate is higher than about lxl 〇 14 cm _3. 18. The semiconductor device of claim 14 or 17, wherein the carrier concentration in the carrier concentration increasing region is between about lxlO19 and lxl〇2G cnT3%, and is compared with other portions of the tantalum carbide substrate The carrier concentration is high. 19. The semiconductor device of claim 14 or 16, wherein the epitaxial layer is selected from the group consisting of tantalum carbide, a group III-nitride; and an oxide of lanthanum, gallium, aluminum or indium. 20. A light emitting diode comprising: an annealed n-type tantalum carbide substrate having first and second surfaces, respectively; a III-nitride active region on the first surface of the substrate An epitaxial layer on the active region; a carrier concentration increasing region in the tantalum carbide substrate extending from the second surface of the tantalum carbide substrate toward the first surface; An ohmic contact on the second surface; and an ohmic contact on the epitaxial layer. 2 1. The light-emitting diode of claim 20, wherein the carrier concentration increasing region is characterized in that the phosphorus concentration decreases from the second surface toward the first surface. 1281710 月月修#) is replacing page I m—Δ—— I 2 2. The light-emitting diode of claim 20, wherein the active region comprises a structure selected from the group consisting of a homojunction junction, a single heterojunction junction, a double heterojunction junction, a superlattice lattice, and a quantum well. In the group. 2 3. The light-emitting diode of claim 22, wherein one or more portions of the structure are selected from the group consisting of gallium nitride, aluminum nitride, indium nitride, aluminum gallium nitride, and indium gallium nitride In the group consisting of chain indium nitride and sinter indium gallium nitride. 24. The light-emitting diode of claim 20, wherein the active region is selected from the group consisting of gallium nitride, aluminum nitride, indium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium nitride, and aluminum. In the group consisting of indium gallium nitride. The light-emitting diode of claim 20, wherein the ohmic contact to the substrate is selected from the group consisting of titanium, aluminum, nickel, silver, and platinum. stupid